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From: Kuldeep Singh <kuldeep.singh@oss.qualcomm.com>
To: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>,
	Ulf Hansson <ulfh@kernel.org>, Rob Herring <robh@kernel.org>,
	Krzysztof Kozlowski <krzk+dt@kernel.org>,
	Conor Dooley <conor+dt@kernel.org>,
	Bjorn Andersson <andersson@kernel.org>,
	Konrad Dybcio <konradybcio@kernel.org>,
	cros-qcom-dts-watchers@chromium.org
Cc: linux-arm-msm@vger.kernel.org, linux-mmc@vger.kernel.org,
	devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
	Neeraj Soni <neeraj.soni@oss.qualcomm.com>
Subject: Re: [PATCH v8 2/3] arm64: dts: qcom: kodiak: enable inline crypto engine for SDHC
Date: Mon, 29 Jun 2026 18:02:39 +0530	[thread overview]
Message-ID: <d3be45ab-0390-4d0e-8d5b-330a48c529a1@oss.qualcomm.com> (raw)
In-Reply-To: <ba96f5e3-6b6e-40b6-b6c1-300e862e8ee4@oss.qualcomm.com>

On 29-06-2026 17:24, Konrad Dybcio wrote:
> On 6/29/26 9:35 AM, Kuldeep Singh wrote:
>> From: Neeraj Soni <neeraj.soni@oss.qualcomm.com>
>>
>> Add the dedicated ICE node for kodiak and reference it from the SDHC
>> controller via qcom,ice.
>>
>> Keep the ICE node disabled by default in kodiak.dtsi and enable it in
>> board DTS files where the corresponding SDHC node is enabled.
> 
> Is there a reason to disable it in the first place?
> 
> Keeping it enabled it would ensure that the core is parked
> if it was left on by the bootloader
Yes, observed an issue on kodiak Soc which supports both ufs-ice and
sdhc-ice.

CRYPTO_INLINE_ENGINE flag can be set to m via 2 configs MMC_CRYPTO and
SCSI_UFS_CRYPTO. In default defconfig, SCSI_UFS_CRYPTO is enabled
default and hence, CRYPTO_INLINE_ENGINE is enabled irrespective of
MMC_CRYPTO state.
https://elixir.bootlin.com/linux/v7.1.2/source/arch/arm64/configs/defconfig#L1325
https://elixir.bootlin.com/linux/v7.1.2/source/drivers/mmc/host/Kconfig#L614
https://elixir.bootlin.com/linux/v7.1.2/source/drivers/ufs/host/Kconfig#L62

Kodiak Soc supporting both ufs/sdhc results in initiating both ice
instances which in turn votes the clock in driver. In general, ice clock
suspend/resume sequence is later controller by ufs/sdhc controller once
the corresponding ice instance is initialised.

Since, qcs6490-rb3gen2(having only ufs storage) doesn't have emmc
storage but sdhc-ice DT node still probes the driver, later sdhci-msm
never takes ice instance(as sdhc_1 is disabled) but ice-clocks are
remained voted on.

This results in an issue and hence, trying to fix it by enabling ice
only when corresponding storage controller is enabled be it ufs or sdhc.
ufs/sdhc are default disabled and enabled per DTS, hence following same
convention with ice DT nodes too.

I am planning to update other DTs too with same change.
Suggestions are welcome!

-- 
Regards
Kuldeep


  reply	other threads:[~2026-06-29 12:32 UTC|newest]

Thread overview: 14+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-06-29  7:35 [PATCH v8 0/3] Enable sdhc inline crypto engine for kodiak and monaco Kuldeep Singh
2026-06-29  7:35 ` [PATCH v8 1/3] dt-bindings: mmc: sdhci-msm: add ICE phandle Kuldeep Singh
2026-07-06 15:46   ` Ulf Hansson
2026-06-29  7:35 ` [PATCH v8 2/3] arm64: dts: qcom: kodiak: enable inline crypto engine for SDHC Kuldeep Singh
2026-06-29 11:54   ` Konrad Dybcio
2026-06-29 12:32     ` Kuldeep Singh [this message]
2026-06-29 13:56       ` Konrad Dybcio
2026-06-30 10:23         ` Kuldeep Singh
2026-06-30 11:25           ` Konrad Dybcio
2026-07-06 11:03             ` Kuldeep Singh
2026-08-28 12:57             ` Abel Vesa
2026-08-28 19:07               ` Konrad Dybcio
2026-08-31 16:08                 ` Abel Vesa
2026-06-29  7:35 ` [PATCH v8 3/3] arm64: dts: qcom: monaco: " Kuldeep Singh

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