From: Kuldeep Singh <kuldeep.singh@oss.qualcomm.com>
To: Ulf Hansson <ulfh@kernel.org>, Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>,
Bjorn Andersson <andersson@kernel.org>,
Konrad Dybcio <konradybcio@kernel.org>,
cros-qcom-dts-watchers@chromium.org
Cc: linux-arm-msm@vger.kernel.org, linux-mmc@vger.kernel.org,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
Neeraj Soni <neeraj.soni@oss.qualcomm.com>,
Abhinaba Rakshit <abhinaba.rakshit@oss.qualcomm.com>,
Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>,
Kuldeep Singh <kuldeep.singh@oss.qualcomm.com>,
Abel Vesa <abelvesa@kernel.org>
Subject: [PATCH v8 1/3] dt-bindings: mmc: sdhci-msm: add ICE phandle
Date: Mon, 29 Jun 2026 13:05:31 +0530 [thread overview]
Message-ID: <20260629-ice_emmc_support-v8-1-1a26e1717b85@oss.qualcomm.com> (raw)
In-Reply-To: <20260629-ice_emmc_support-v8-0-1a26e1717b85@oss.qualcomm.com>
From: Neeraj Soni <neeraj.soni@oss.qualcomm.com>
On newer Qualcomm SoCs (starting with sc7280/kodiak), ICE is modelled
as a dedicated DT node. Add the optional qcom,ice phandle to reference
that node from the SDHCI controller.
When qcom,ice is present, disallow an embedded ICE register region in
the SDHCI node to avoid double modelling. Older SoCs without qcom,ice
remain valid.
Co-developed-by: Abel Vesa <abel.vesa@linaro.org>
Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
Co-developed-by: Abhinaba Rakshit <abhinaba.rakshit@oss.qualcomm.com>
Signed-off-by: Abhinaba Rakshit <abhinaba.rakshit@oss.qualcomm.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Signed-off-by: Neeraj Soni <neeraj.soni@oss.qualcomm.com>
Signed-off-by: Kuldeep Singh <kuldeep.singh@oss.qualcomm.com>
---
.../devicetree/bindings/mmc/qcom,sdhci-msm.yaml | 95 +++++++++++++++-------
1 file changed, 67 insertions(+), 28 deletions(-)
diff --git a/Documentation/devicetree/bindings/mmc/qcom,sdhci-msm.yaml b/Documentation/devicetree/bindings/mmc/qcom,sdhci-msm.yaml
index bd558a11b792..b3fcc1673c10 100644
--- a/Documentation/devicetree/bindings/mmc/qcom,sdhci-msm.yaml
+++ b/Documentation/devicetree/bindings/mmc/qcom,sdhci-msm.yaml
@@ -145,6 +145,11 @@ properties:
$ref: /schemas/types.yaml#/definitions/uint32
description: platform specific settings for DLL_CONFIG reg.
+ qcom,ice:
+ $ref: /schemas/types.yaml#/definitions/phandle
+ description:
+ phandle to the Inline Crypto Engine (ICE) hardware block for this controller.
+
iommus:
minItems: 1
maxItems: 8
@@ -198,35 +203,69 @@ allOf:
enum:
- qcom,sdhci-msm-v4
then:
- properties:
- reg:
- minItems: 2
- items:
- - description: Host controller register map
- - description: SD Core register map
- - description: CQE register map
- - description: Inline Crypto Engine register map
- reg-names:
- minItems: 2
- items:
- - const: hc
- - const: core
- - const: cqhci
- - const: ice
+ if:
+ required:
+ - qcom,ice
+ then:
+ properties:
+ reg:
+ minItems: 2
+ items:
+ - description: Host controller register map
+ - description: SD Core register map
+ - description: CQE register map
+ reg-names:
+ minItems: 2
+ items:
+ - const: hc
+ - const: core
+ - const: cqhci
+ else:
+ properties:
+ reg:
+ minItems: 2
+ items:
+ - description: Host controller register map
+ - description: SD Core register map
+ - description: CQE register map
+ - description: Inline Crypto Engine register map
+ reg-names:
+ minItems: 2
+ items:
+ - const: hc
+ - const: core
+ - const: cqhci
+ - const: ice
else:
- properties:
- reg:
- minItems: 1
- items:
- - description: Host controller register map
- - description: CQE register map
- - description: Inline Crypto Engine register map
- reg-names:
- minItems: 1
- items:
- - const: hc
- - const: cqhci
- - const: ice
+ if:
+ required:
+ - qcom,ice
+ then:
+ properties:
+ reg:
+ minItems: 1
+ items:
+ - description: Host controller register map
+ - description: CQE register map
+ reg-names:
+ minItems: 1
+ items:
+ - const: hc
+ - const: cqhci
+ else:
+ properties:
+ reg:
+ minItems: 1
+ items:
+ - description: Host controller register map
+ - description: CQE register map
+ - description: Inline Crypto Engine register map
+ reg-names:
+ minItems: 1
+ items:
+ - const: hc
+ - const: cqhci
+ - const: ice
unevaluatedProperties: false
--
2.34.1
next prev parent reply other threads:[~2026-06-29 7:36 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-06-29 7:35 [PATCH v8 0/3] Enable sdhc inline crypto engine for kodiak and monaco Kuldeep Singh
2026-06-29 7:35 ` Kuldeep Singh [this message]
2026-07-06 15:46 ` [PATCH v8 1/3] dt-bindings: mmc: sdhci-msm: add ICE phandle Ulf Hansson
2026-06-29 7:35 ` [PATCH v8 2/3] arm64: dts: qcom: kodiak: enable inline crypto engine for SDHC Kuldeep Singh
2026-06-29 11:54 ` Konrad Dybcio
2026-06-29 12:32 ` Kuldeep Singh
2026-06-29 13:56 ` Konrad Dybcio
2026-06-30 10:23 ` Kuldeep Singh
2026-06-30 11:25 ` Konrad Dybcio
2026-07-06 11:03 ` Kuldeep Singh
2026-08-28 12:57 ` Abel Vesa
2026-08-28 19:07 ` Konrad Dybcio
2026-08-31 16:08 ` Abel Vesa
2026-06-29 7:35 ` [PATCH v8 3/3] arm64: dts: qcom: monaco: " Kuldeep Singh
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