Re: [PATCH] arm64: dts: qcom: lemans: add DT changes to enable MDSS1 and DPU

[Mahadevan P <mahadevan.p@oss.qualcomm.com>]

On 9/26/2025 3:11 AM, Dmitry Baryshkov wrote:
> On Thu, Sep 25, 2025 at 02:28:07PM +0530, Mahadevan wrote:
>> Add devicetree changes to enable second Mobile Display
>> Subsystem (MDSS1) and its Display Processing Unit(DPU) for
>> Qualcomm LEMANS platform.
> No outputs? Should it be enabled on any of the devices?

Outputs  and enablement are include as part of this series:
https://lore.kernel.org/all/20250926085956.2346179-1-quic_mkuntuma@quicinc.com/
I will update the commit message to use the phrase "to support" for 
better clarity.

>
>> Signed-off-by: Mahadevan <mahadevan.p@oss.qualcomm.com>
>> ---
>>   arch/arm64/boot/dts/qcom/lemans.dtsi | 88 ++++++++++++++++++++++++++++++++++++
>>   1 file changed, 88 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/qcom/lemans.dtsi b/arch/arm64/boot/dts/qcom/lemans.dtsi
>> index 48f753002fc459a3e9fac0c0e98cbec6013fea0f..45c11c050d3f8853701fd20cf647aef5c6a9a8c9 100644
>> --- a/arch/arm64/boot/dts/qcom/lemans.dtsi
>> +++ b/arch/arm64/boot/dts/qcom/lemans.dtsi
>> @@ -6751,6 +6751,94 @@ compute-cb@3 {
>>   			};
>>   		};
>>   
>> +		mdss1: display-subsystem@22000000 {
> Why do you need this label?

display-controller@22001000 is using mdss1 as interrupt parent.

>
>> +			compatible = "qcom,sa8775p-mdss";
>> +			reg = <0x0 0x22000000 0x0 0x1000>;
>> +			reg-names = "mdss";
>> +
>> +			/* same path used twice */
>> +			interconnects = <&mmss_noc MASTER_MDP_CORE1_0 QCOM_ICC_TAG_ALWAYS
>> +					 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
>> +					<&mmss_noc MASTER_MDP_CORE1_1 QCOM_ICC_TAG_ALWAYS
>> +					 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
>> +					<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
>> +					 &config_noc SLAVE_DISPLAY_CFG QCOM_ICC_TAG_ACTIVE_ONLY>;
>> +			interconnect-names = "mdp0-mem",
>> +					     "mdp1-mem",
>> +					     "cpu-cfg";
>> +
>> +			resets = <&dispcc1 MDSS_DISP_CC_MDSS_CORE_BCR>;
>> +
>> +			power-domains = <&dispcc1 MDSS_DISP_CC_MDSS_CORE_GDSC>;
>> +
>> +			clocks = <&dispcc1 MDSS_DISP_CC_MDSS_AHB_CLK>,
>> +				 <&gcc GCC_DISP1_HF_AXI_CLK>,
>> +				 <&dispcc1 MDSS_DISP_CC_MDSS_MDP_CLK>;
>> +
>> +			interrupts = <GIC_SPI 865 IRQ_TYPE_LEVEL_HIGH>;
>> +			interrupt-controller;
>> +			#interrupt-cells = <1>;
>> +
>> +			iommus = <&apps_smmu 0x1800 0x402>;
>> +
>> +			#address-cells = <2>;
>> +			#size-cells = <2>;
>> +			ranges;
>> +
>> +			status = "disabled";
>> +
>> +			mdss1_mdp: display-controller@22001000 {
> Why do you need this label?

will remove.

>
>> +				compatible = "qcom,sa8775p-dpu";
>> +				reg = <0x0 0x22001000 0x0 0x8f000>,
>> +				      <0x0 0x220b0000 0x0 0x3000>;
>> +				reg-names = "mdp", "vbif";
>> +
>> +				clocks = <&gcc GCC_DISP1_HF_AXI_CLK>,
>> +					 <&dispcc1 MDSS_DISP_CC_MDSS_AHB_CLK>,
>> +					 <&dispcc1 MDSS_DISP_CC_MDSS_MDP_LUT_CLK>,
>> +					 <&dispcc1 MDSS_DISP_CC_MDSS_MDP_CLK>,
>> +					 <&dispcc1 MDSS_DISP_CC_MDSS_VSYNC_CLK>;
>> +				clock-names = "nrt_bus",
>> +					      "iface",
>> +					      "lut",
>> +					      "core",
>> +					      "vsync";
>> +
>> +				assigned-clocks = <&dispcc1 MDSS_DISP_CC_MDSS_VSYNC_CLK>;
>> +				assigned-clock-rates = <19200000>;
>> +
>> +				operating-points-v2 = <&mdss1_mdp_opp_table>;
>> +				power-domains = <&rpmhpd SA8775P_MMCX>;
>> +
>> +				interrupt-parent = <&mdss1>;
>> +				interrupts = <0>;
>> +
>> +				mdss1_mdp_opp_table: opp-table {
>> +					compatible = "operating-points-v2";
>> +
>> +					opp-375000000 {
>> +						opp-hz = /bits/ 64 <375000000>;
>> +						required-opps = <&rpmhpd_opp_svs_l1>;
>> +					};
>> +
>> +					opp-500000000 {
>> +						opp-hz = /bits/ 64 <500000000>;
>> +						required-opps = <&rpmhpd_opp_nom>;
>> +					};
>> +
>> +					opp-575000000 {
>> +						opp-hz = /bits/ 64 <575000000>;
>> +						required-opps = <&rpmhpd_opp_turbo>;
>> +					};
>> +
>> +					opp-650000000 {
>> +						opp-hz = /bits/ 64 <650000000>;
>> +						required-opps = <&rpmhpd_opp_turbo_l1>;
>> +					};
>> +				};
>> +			};
>> +		};
>> +
>>   		dispcc1: clock-controller@22100000 {
>>   			compatible = "qcom,sa8775p-dispcc1";
>>   			reg = <0x0 0x22100000 0x0 0x20000>;
>>
>> ---
>> base-commit: 846bd2225ec3cfa8be046655e02b9457ed41973e
>> change-id: 20250923-lemans_dual-c03ad5c84a84
>>
>> Best regards,
>> -- 
>> Mahadevan <mahadevan.p@oss.qualcomm.com>
>>
Thanks,
Mahadevan