* [PATCH] arm64: dts: qcom: lemans: add DT changes to enable MDSS1 and DPU
@ 2025-09-25 8:58 Mahadevan
2025-09-25 10:49 ` Konrad Dybcio
2025-09-25 21:41 ` Dmitry Baryshkov
0 siblings, 2 replies; 7+ messages in thread
From: Mahadevan @ 2025-09-25 8:58 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Dmitry Baryshkov
Cc: linux-arm-msm, devicetree, linux-kernel, Mahadevan
Add devicetree changes to enable second Mobile Display
Subsystem (MDSS1) and its Display Processing Unit(DPU) for
Qualcomm LEMANS platform.
Signed-off-by: Mahadevan <mahadevan.p@oss.qualcomm.com>
---
arch/arm64/boot/dts/qcom/lemans.dtsi | 88 ++++++++++++++++++++++++++++++++++++
1 file changed, 88 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/lemans.dtsi b/arch/arm64/boot/dts/qcom/lemans.dtsi
index 48f753002fc459a3e9fac0c0e98cbec6013fea0f..45c11c050d3f8853701fd20cf647aef5c6a9a8c9 100644
--- a/arch/arm64/boot/dts/qcom/lemans.dtsi
+++ b/arch/arm64/boot/dts/qcom/lemans.dtsi
@@ -6751,6 +6751,94 @@ compute-cb@3 {
};
};
+ mdss1: display-subsystem@22000000 {
+ compatible = "qcom,sa8775p-mdss";
+ reg = <0x0 0x22000000 0x0 0x1000>;
+ reg-names = "mdss";
+
+ /* same path used twice */
+ interconnects = <&mmss_noc MASTER_MDP_CORE1_0 QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
+ <&mmss_noc MASTER_MDP_CORE1_1 QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &config_noc SLAVE_DISPLAY_CFG QCOM_ICC_TAG_ACTIVE_ONLY>;
+ interconnect-names = "mdp0-mem",
+ "mdp1-mem",
+ "cpu-cfg";
+
+ resets = <&dispcc1 MDSS_DISP_CC_MDSS_CORE_BCR>;
+
+ power-domains = <&dispcc1 MDSS_DISP_CC_MDSS_CORE_GDSC>;
+
+ clocks = <&dispcc1 MDSS_DISP_CC_MDSS_AHB_CLK>,
+ <&gcc GCC_DISP1_HF_AXI_CLK>,
+ <&dispcc1 MDSS_DISP_CC_MDSS_MDP_CLK>;
+
+ interrupts = <GIC_SPI 865 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+
+ iommus = <&apps_smmu 0x1800 0x402>;
+
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ status = "disabled";
+
+ mdss1_mdp: display-controller@22001000 {
+ compatible = "qcom,sa8775p-dpu";
+ reg = <0x0 0x22001000 0x0 0x8f000>,
+ <0x0 0x220b0000 0x0 0x3000>;
+ reg-names = "mdp", "vbif";
+
+ clocks = <&gcc GCC_DISP1_HF_AXI_CLK>,
+ <&dispcc1 MDSS_DISP_CC_MDSS_AHB_CLK>,
+ <&dispcc1 MDSS_DISP_CC_MDSS_MDP_LUT_CLK>,
+ <&dispcc1 MDSS_DISP_CC_MDSS_MDP_CLK>,
+ <&dispcc1 MDSS_DISP_CC_MDSS_VSYNC_CLK>;
+ clock-names = "nrt_bus",
+ "iface",
+ "lut",
+ "core",
+ "vsync";
+
+ assigned-clocks = <&dispcc1 MDSS_DISP_CC_MDSS_VSYNC_CLK>;
+ assigned-clock-rates = <19200000>;
+
+ operating-points-v2 = <&mdss1_mdp_opp_table>;
+ power-domains = <&rpmhpd SA8775P_MMCX>;
+
+ interrupt-parent = <&mdss1>;
+ interrupts = <0>;
+
+ mdss1_mdp_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ opp-375000000 {
+ opp-hz = /bits/ 64 <375000000>;
+ required-opps = <&rpmhpd_opp_svs_l1>;
+ };
+
+ opp-500000000 {
+ opp-hz = /bits/ 64 <500000000>;
+ required-opps = <&rpmhpd_opp_nom>;
+ };
+
+ opp-575000000 {
+ opp-hz = /bits/ 64 <575000000>;
+ required-opps = <&rpmhpd_opp_turbo>;
+ };
+
+ opp-650000000 {
+ opp-hz = /bits/ 64 <650000000>;
+ required-opps = <&rpmhpd_opp_turbo_l1>;
+ };
+ };
+ };
+ };
+
dispcc1: clock-controller@22100000 {
compatible = "qcom,sa8775p-dispcc1";
reg = <0x0 0x22100000 0x0 0x20000>;
---
base-commit: 846bd2225ec3cfa8be046655e02b9457ed41973e
change-id: 20250923-lemans_dual-c03ad5c84a84
Best regards,
--
Mahadevan <mahadevan.p@oss.qualcomm.com>
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH] arm64: dts: qcom: lemans: add DT changes to enable MDSS1 and DPU
2025-09-25 8:58 [PATCH] arm64: dts: qcom: lemans: add DT changes to enable MDSS1 and DPU Mahadevan
@ 2025-09-25 10:49 ` Konrad Dybcio
2025-09-25 21:45 ` Dmitry Baryshkov
2025-09-25 21:41 ` Dmitry Baryshkov
1 sibling, 1 reply; 7+ messages in thread
From: Konrad Dybcio @ 2025-09-25 10:49 UTC (permalink / raw)
To: Mahadevan, Bjorn Andersson, Konrad Dybcio, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Dmitry Baryshkov
Cc: linux-arm-msm, devicetree, linux-kernel
On 9/25/25 10:58 AM, Mahadevan wrote:
> Add devicetree changes to enable second Mobile Display
> Subsystem (MDSS1) and its Display Processing Unit(DPU) for
> Qualcomm LEMANS platform.
No need to scream.. "lemans" or "LeMans">
> Signed-off-by: Mahadevan <mahadevan.p@oss.qualcomm.com>
Please include your full name in git config
> ---
> arch/arm64/boot/dts/qcom/lemans.dtsi | 88 ++++++++++++++++++++++++++++++++++++
> 1 file changed, 88 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/lemans.dtsi b/arch/arm64/boot/dts/qcom/lemans.dtsi
> index 48f753002fc459a3e9fac0c0e98cbec6013fea0f..45c11c050d3f8853701fd20cf647aef5c6a9a8c9 100644
> --- a/arch/arm64/boot/dts/qcom/lemans.dtsi
> +++ b/arch/arm64/boot/dts/qcom/lemans.dtsi
> @@ -6751,6 +6751,94 @@ compute-cb@3 {
> };
> };
>
> + mdss1: display-subsystem@22000000 {
> + compatible = "qcom,sa8775p-mdss";
> + reg = <0x0 0x22000000 0x0 0x1000>;
> + reg-names = "mdss";
> +
> + /* same path used twice */
this comment is misleading
> + interconnects = <&mmss_noc MASTER_MDP_CORE1_0 QCOM_ICC_TAG_ALWAYS
> + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
> + <&mmss_noc MASTER_MDP_CORE1_1 QCOM_ICC_TAG_ALWAYS
> + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
> + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
> + &config_noc SLAVE_DISPLAY_CFG QCOM_ICC_TAG_ACTIVE_ONLY>;
> + interconnect-names = "mdp0-mem",
> + "mdp1-mem",
> + "cpu-cfg";
> +
> + resets = <&dispcc1 MDSS_DISP_CC_MDSS_CORE_BCR>;
> +
> + power-domains = <&dispcc1 MDSS_DISP_CC_MDSS_CORE_GDSC>;
> +
> + clocks = <&dispcc1 MDSS_DISP_CC_MDSS_AHB_CLK>,
> + <&gcc GCC_DISP1_HF_AXI_CLK>,
> + <&dispcc1 MDSS_DISP_CC_MDSS_MDP_CLK>;
> +
> + interrupts = <GIC_SPI 865 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-controller;
> + #interrupt-cells = <1>;
> +
> + iommus = <&apps_smmu 0x1800 0x402>;
> +
> + #address-cells = <2>;
> + #size-cells = <2>;
> + ranges;
> +
> + status = "disabled";
> +
> + mdss1_mdp: display-controller@22001000 {
> + compatible = "qcom,sa8775p-dpu";
Adding nothing more but the DPU isn't very useful at all
and doesn't really let you test the hardware (since you don't
provide a sink)
Konrad
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH] arm64: dts: qcom: lemans: add DT changes to enable MDSS1 and DPU
2025-09-25 8:58 [PATCH] arm64: dts: qcom: lemans: add DT changes to enable MDSS1 and DPU Mahadevan
2025-09-25 10:49 ` Konrad Dybcio
@ 2025-09-25 21:41 ` Dmitry Baryshkov
2025-09-26 9:24 ` Mahadevan P
1 sibling, 1 reply; 7+ messages in thread
From: Dmitry Baryshkov @ 2025-09-25 21:41 UTC (permalink / raw)
To: Mahadevan
Cc: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, linux-arm-msm, devicetree, linux-kernel
On Thu, Sep 25, 2025 at 02:28:07PM +0530, Mahadevan wrote:
> Add devicetree changes to enable second Mobile Display
> Subsystem (MDSS1) and its Display Processing Unit(DPU) for
> Qualcomm LEMANS platform.
No outputs? Should it be enabled on any of the devices?
>
> Signed-off-by: Mahadevan <mahadevan.p@oss.qualcomm.com>
> ---
> arch/arm64/boot/dts/qcom/lemans.dtsi | 88 ++++++++++++++++++++++++++++++++++++
> 1 file changed, 88 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/lemans.dtsi b/arch/arm64/boot/dts/qcom/lemans.dtsi
> index 48f753002fc459a3e9fac0c0e98cbec6013fea0f..45c11c050d3f8853701fd20cf647aef5c6a9a8c9 100644
> --- a/arch/arm64/boot/dts/qcom/lemans.dtsi
> +++ b/arch/arm64/boot/dts/qcom/lemans.dtsi
> @@ -6751,6 +6751,94 @@ compute-cb@3 {
> };
> };
>
> + mdss1: display-subsystem@22000000 {
Why do you need this label?
> + compatible = "qcom,sa8775p-mdss";
> + reg = <0x0 0x22000000 0x0 0x1000>;
> + reg-names = "mdss";
> +
> + /* same path used twice */
> + interconnects = <&mmss_noc MASTER_MDP_CORE1_0 QCOM_ICC_TAG_ALWAYS
> + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
> + <&mmss_noc MASTER_MDP_CORE1_1 QCOM_ICC_TAG_ALWAYS
> + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
> + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
> + &config_noc SLAVE_DISPLAY_CFG QCOM_ICC_TAG_ACTIVE_ONLY>;
> + interconnect-names = "mdp0-mem",
> + "mdp1-mem",
> + "cpu-cfg";
> +
> + resets = <&dispcc1 MDSS_DISP_CC_MDSS_CORE_BCR>;
> +
> + power-domains = <&dispcc1 MDSS_DISP_CC_MDSS_CORE_GDSC>;
> +
> + clocks = <&dispcc1 MDSS_DISP_CC_MDSS_AHB_CLK>,
> + <&gcc GCC_DISP1_HF_AXI_CLK>,
> + <&dispcc1 MDSS_DISP_CC_MDSS_MDP_CLK>;
> +
> + interrupts = <GIC_SPI 865 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-controller;
> + #interrupt-cells = <1>;
> +
> + iommus = <&apps_smmu 0x1800 0x402>;
> +
> + #address-cells = <2>;
> + #size-cells = <2>;
> + ranges;
> +
> + status = "disabled";
> +
> + mdss1_mdp: display-controller@22001000 {
Why do you need this label?
> + compatible = "qcom,sa8775p-dpu";
> + reg = <0x0 0x22001000 0x0 0x8f000>,
> + <0x0 0x220b0000 0x0 0x3000>;
> + reg-names = "mdp", "vbif";
> +
> + clocks = <&gcc GCC_DISP1_HF_AXI_CLK>,
> + <&dispcc1 MDSS_DISP_CC_MDSS_AHB_CLK>,
> + <&dispcc1 MDSS_DISP_CC_MDSS_MDP_LUT_CLK>,
> + <&dispcc1 MDSS_DISP_CC_MDSS_MDP_CLK>,
> + <&dispcc1 MDSS_DISP_CC_MDSS_VSYNC_CLK>;
> + clock-names = "nrt_bus",
> + "iface",
> + "lut",
> + "core",
> + "vsync";
> +
> + assigned-clocks = <&dispcc1 MDSS_DISP_CC_MDSS_VSYNC_CLK>;
> + assigned-clock-rates = <19200000>;
> +
> + operating-points-v2 = <&mdss1_mdp_opp_table>;
> + power-domains = <&rpmhpd SA8775P_MMCX>;
> +
> + interrupt-parent = <&mdss1>;
> + interrupts = <0>;
> +
> + mdss1_mdp_opp_table: opp-table {
> + compatible = "operating-points-v2";
> +
> + opp-375000000 {
> + opp-hz = /bits/ 64 <375000000>;
> + required-opps = <&rpmhpd_opp_svs_l1>;
> + };
> +
> + opp-500000000 {
> + opp-hz = /bits/ 64 <500000000>;
> + required-opps = <&rpmhpd_opp_nom>;
> + };
> +
> + opp-575000000 {
> + opp-hz = /bits/ 64 <575000000>;
> + required-opps = <&rpmhpd_opp_turbo>;
> + };
> +
> + opp-650000000 {
> + opp-hz = /bits/ 64 <650000000>;
> + required-opps = <&rpmhpd_opp_turbo_l1>;
> + };
> + };
> + };
> + };
> +
> dispcc1: clock-controller@22100000 {
> compatible = "qcom,sa8775p-dispcc1";
> reg = <0x0 0x22100000 0x0 0x20000>;
>
> ---
> base-commit: 846bd2225ec3cfa8be046655e02b9457ed41973e
> change-id: 20250923-lemans_dual-c03ad5c84a84
>
> Best regards,
> --
> Mahadevan <mahadevan.p@oss.qualcomm.com>
>
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH] arm64: dts: qcom: lemans: add DT changes to enable MDSS1 and DPU
2025-09-25 10:49 ` Konrad Dybcio
@ 2025-09-25 21:45 ` Dmitry Baryshkov
0 siblings, 0 replies; 7+ messages in thread
From: Dmitry Baryshkov @ 2025-09-25 21:45 UTC (permalink / raw)
To: Konrad Dybcio
Cc: Mahadevan, Bjorn Andersson, Konrad Dybcio, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, linux-arm-msm, devicetree,
linux-kernel
On Thu, Sep 25, 2025 at 12:49:48PM +0200, Konrad Dybcio wrote:
> On 9/25/25 10:58 AM, Mahadevan wrote:
> > Add devicetree changes to enable second Mobile Display
> > Subsystem (MDSS1) and its Display Processing Unit(DPU) for
> > Qualcomm LEMANS platform.
>
> No need to scream.. "lemans" or "LeMans">
> > Signed-off-by: Mahadevan <mahadevan.p@oss.qualcomm.com>
>
> Please include your full name in git config
>
> > ---
> > arch/arm64/boot/dts/qcom/lemans.dtsi | 88 ++++++++++++++++++++++++++++++++++++
> > 1 file changed, 88 insertions(+)
> >
> > diff --git a/arch/arm64/boot/dts/qcom/lemans.dtsi b/arch/arm64/boot/dts/qcom/lemans.dtsi
> > index 48f753002fc459a3e9fac0c0e98cbec6013fea0f..45c11c050d3f8853701fd20cf647aef5c6a9a8c9 100644
> > --- a/arch/arm64/boot/dts/qcom/lemans.dtsi
> > +++ b/arch/arm64/boot/dts/qcom/lemans.dtsi
> > @@ -6751,6 +6751,94 @@ compute-cb@3 {
> > };
> > };
> >
> > + mdss1: display-subsystem@22000000 {
> > + compatible = "qcom,sa8775p-mdss";
> > + reg = <0x0 0x22000000 0x0 0x1000>;
> > + reg-names = "mdss";
> > +
> > + /* same path used twice */
>
> this comment is misleading
>
> > + interconnects = <&mmss_noc MASTER_MDP_CORE1_0 QCOM_ICC_TAG_ALWAYS
> > + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
> > + <&mmss_noc MASTER_MDP_CORE1_1 QCOM_ICC_TAG_ALWAYS
> > + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
> > + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
> > + &config_noc SLAVE_DISPLAY_CFG QCOM_ICC_TAG_ACTIVE_ONLY>;
> > + interconnect-names = "mdp0-mem",
> > + "mdp1-mem",
> > + "cpu-cfg";
> > +
> > + resets = <&dispcc1 MDSS_DISP_CC_MDSS_CORE_BCR>;
> > +
> > + power-domains = <&dispcc1 MDSS_DISP_CC_MDSS_CORE_GDSC>;
> > +
> > + clocks = <&dispcc1 MDSS_DISP_CC_MDSS_AHB_CLK>,
> > + <&gcc GCC_DISP1_HF_AXI_CLK>,
> > + <&dispcc1 MDSS_DISP_CC_MDSS_MDP_CLK>;
> > +
> > + interrupts = <GIC_SPI 865 IRQ_TYPE_LEVEL_HIGH>;
> > + interrupt-controller;
> > + #interrupt-cells = <1>;
> > +
> > + iommus = <&apps_smmu 0x1800 0x402>;
> > +
> > + #address-cells = <2>;
> > + #size-cells = <2>;
> > + ranges;
> > +
> > + status = "disabled";
> > +
> > + mdss1_mdp: display-controller@22001000 {
> > + compatible = "qcom,sa8775p-dpu";
>
> Adding nothing more but the DPU isn't very useful at all
> and doesn't really let you test the hardware (since you don't
> provide a sink)
Only with writeback.
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH] arm64: dts: qcom: lemans: add DT changes to enable MDSS1 and DPU
2025-09-25 21:41 ` Dmitry Baryshkov
@ 2025-09-26 9:24 ` Mahadevan P
2025-09-26 10:43 ` Konrad Dybcio
2025-10-17 22:50 ` Bjorn Andersson
0 siblings, 2 replies; 7+ messages in thread
From: Mahadevan P @ 2025-09-26 9:24 UTC (permalink / raw)
To: Dmitry Baryshkov
Cc: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, linux-arm-msm, devicetree, linux-kernel
On 9/26/2025 3:11 AM, Dmitry Baryshkov wrote:
> On Thu, Sep 25, 2025 at 02:28:07PM +0530, Mahadevan wrote:
>> Add devicetree changes to enable second Mobile Display
>> Subsystem (MDSS1) and its Display Processing Unit(DPU) for
>> Qualcomm LEMANS platform.
> No outputs? Should it be enabled on any of the devices?
Outputs and enablement are include as part of this series:
https://lore.kernel.org/all/20250926085956.2346179-1-quic_mkuntuma@quicinc.com/
I will update the commit message to use the phrase "to support" for
better clarity.
>
>> Signed-off-by: Mahadevan <mahadevan.p@oss.qualcomm.com>
>> ---
>> arch/arm64/boot/dts/qcom/lemans.dtsi | 88 ++++++++++++++++++++++++++++++++++++
>> 1 file changed, 88 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/qcom/lemans.dtsi b/arch/arm64/boot/dts/qcom/lemans.dtsi
>> index 48f753002fc459a3e9fac0c0e98cbec6013fea0f..45c11c050d3f8853701fd20cf647aef5c6a9a8c9 100644
>> --- a/arch/arm64/boot/dts/qcom/lemans.dtsi
>> +++ b/arch/arm64/boot/dts/qcom/lemans.dtsi
>> @@ -6751,6 +6751,94 @@ compute-cb@3 {
>> };
>> };
>>
>> + mdss1: display-subsystem@22000000 {
> Why do you need this label?
display-controller@22001000 is using mdss1 as interrupt parent.
>
>> + compatible = "qcom,sa8775p-mdss";
>> + reg = <0x0 0x22000000 0x0 0x1000>;
>> + reg-names = "mdss";
>> +
>> + /* same path used twice */
>> + interconnects = <&mmss_noc MASTER_MDP_CORE1_0 QCOM_ICC_TAG_ALWAYS
>> + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
>> + <&mmss_noc MASTER_MDP_CORE1_1 QCOM_ICC_TAG_ALWAYS
>> + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
>> + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
>> + &config_noc SLAVE_DISPLAY_CFG QCOM_ICC_TAG_ACTIVE_ONLY>;
>> + interconnect-names = "mdp0-mem",
>> + "mdp1-mem",
>> + "cpu-cfg";
>> +
>> + resets = <&dispcc1 MDSS_DISP_CC_MDSS_CORE_BCR>;
>> +
>> + power-domains = <&dispcc1 MDSS_DISP_CC_MDSS_CORE_GDSC>;
>> +
>> + clocks = <&dispcc1 MDSS_DISP_CC_MDSS_AHB_CLK>,
>> + <&gcc GCC_DISP1_HF_AXI_CLK>,
>> + <&dispcc1 MDSS_DISP_CC_MDSS_MDP_CLK>;
>> +
>> + interrupts = <GIC_SPI 865 IRQ_TYPE_LEVEL_HIGH>;
>> + interrupt-controller;
>> + #interrupt-cells = <1>;
>> +
>> + iommus = <&apps_smmu 0x1800 0x402>;
>> +
>> + #address-cells = <2>;
>> + #size-cells = <2>;
>> + ranges;
>> +
>> + status = "disabled";
>> +
>> + mdss1_mdp: display-controller@22001000 {
> Why do you need this label?
will remove.
>
>> + compatible = "qcom,sa8775p-dpu";
>> + reg = <0x0 0x22001000 0x0 0x8f000>,
>> + <0x0 0x220b0000 0x0 0x3000>;
>> + reg-names = "mdp", "vbif";
>> +
>> + clocks = <&gcc GCC_DISP1_HF_AXI_CLK>,
>> + <&dispcc1 MDSS_DISP_CC_MDSS_AHB_CLK>,
>> + <&dispcc1 MDSS_DISP_CC_MDSS_MDP_LUT_CLK>,
>> + <&dispcc1 MDSS_DISP_CC_MDSS_MDP_CLK>,
>> + <&dispcc1 MDSS_DISP_CC_MDSS_VSYNC_CLK>;
>> + clock-names = "nrt_bus",
>> + "iface",
>> + "lut",
>> + "core",
>> + "vsync";
>> +
>> + assigned-clocks = <&dispcc1 MDSS_DISP_CC_MDSS_VSYNC_CLK>;
>> + assigned-clock-rates = <19200000>;
>> +
>> + operating-points-v2 = <&mdss1_mdp_opp_table>;
>> + power-domains = <&rpmhpd SA8775P_MMCX>;
>> +
>> + interrupt-parent = <&mdss1>;
>> + interrupts = <0>;
>> +
>> + mdss1_mdp_opp_table: opp-table {
>> + compatible = "operating-points-v2";
>> +
>> + opp-375000000 {
>> + opp-hz = /bits/ 64 <375000000>;
>> + required-opps = <&rpmhpd_opp_svs_l1>;
>> + };
>> +
>> + opp-500000000 {
>> + opp-hz = /bits/ 64 <500000000>;
>> + required-opps = <&rpmhpd_opp_nom>;
>> + };
>> +
>> + opp-575000000 {
>> + opp-hz = /bits/ 64 <575000000>;
>> + required-opps = <&rpmhpd_opp_turbo>;
>> + };
>> +
>> + opp-650000000 {
>> + opp-hz = /bits/ 64 <650000000>;
>> + required-opps = <&rpmhpd_opp_turbo_l1>;
>> + };
>> + };
>> + };
>> + };
>> +
>> dispcc1: clock-controller@22100000 {
>> compatible = "qcom,sa8775p-dispcc1";
>> reg = <0x0 0x22100000 0x0 0x20000>;
>>
>> ---
>> base-commit: 846bd2225ec3cfa8be046655e02b9457ed41973e
>> change-id: 20250923-lemans_dual-c03ad5c84a84
>>
>> Best regards,
>> --
>> Mahadevan <mahadevan.p@oss.qualcomm.com>
>>
Thanks,
Mahadevan
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH] arm64: dts: qcom: lemans: add DT changes to enable MDSS1 and DPU
2025-09-26 9:24 ` Mahadevan P
@ 2025-09-26 10:43 ` Konrad Dybcio
2025-10-17 22:50 ` Bjorn Andersson
1 sibling, 0 replies; 7+ messages in thread
From: Konrad Dybcio @ 2025-09-26 10:43 UTC (permalink / raw)
To: Mahadevan P, Dmitry Baryshkov
Cc: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, linux-arm-msm, devicetree, linux-kernel
On 9/26/25 11:24 AM, Mahadevan P wrote:
>
> On 9/26/2025 3:11 AM, Dmitry Baryshkov wrote:
>> On Thu, Sep 25, 2025 at 02:28:07PM +0530, Mahadevan wrote:
>>> Add devicetree changes to enable second Mobile Display
>>> Subsystem (MDSS1) and its Display Processing Unit(DPU) for
>>> Qualcomm LEMANS platform.
>> No outputs? Should it be enabled on any of the devices?
>
> Outputs and enablement are include as part of this series:
> https://lore.kernel.org/all/20250926085956.2346179-1-quic_mkuntuma@quicinc.com/
Why send two very related and interdependent series separately?
It only makes it harder for the recipients to manage and track your
patches (there are ~100 emails flowing in daily, now more because
of recent SoC announcements)
Konrad
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH] arm64: dts: qcom: lemans: add DT changes to enable MDSS1 and DPU
2025-09-26 9:24 ` Mahadevan P
2025-09-26 10:43 ` Konrad Dybcio
@ 2025-10-17 22:50 ` Bjorn Andersson
1 sibling, 0 replies; 7+ messages in thread
From: Bjorn Andersson @ 2025-10-17 22:50 UTC (permalink / raw)
To: Mahadevan P
Cc: Dmitry Baryshkov, Konrad Dybcio, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, linux-arm-msm, devicetree,
linux-kernel
On Fri, Sep 26, 2025 at 02:54:17PM +0530, Mahadevan P wrote:
>
> On 9/26/2025 3:11 AM, Dmitry Baryshkov wrote:
> > On Thu, Sep 25, 2025 at 02:28:07PM +0530, Mahadevan wrote:
> > > Add devicetree changes to enable second Mobile Display
> > > Subsystem (MDSS1) and its Display Processing Unit(DPU) for
> > > Qualcomm LEMANS platform.
> > No outputs? Should it be enabled on any of the devices?
>
> Outputs and enablement are include as part of this series:
> https://lore.kernel.org/all/20250926085956.2346179-1-quic_mkuntuma@quicinc.com/
> I will update the commit message to use the phrase "to support" for better
> clarity.
>
Have Mani include your patch in his series, with you as author and him
adding his signed-off-by after yours.
That way you're managing the dependency on your side, rather than
relying on others doing that work for you.
Thank you,
Bjorn
> >
> > > Signed-off-by: Mahadevan <mahadevan.p@oss.qualcomm.com>
> > > ---
> > > arch/arm64/boot/dts/qcom/lemans.dtsi | 88 ++++++++++++++++++++++++++++++++++++
> > > 1 file changed, 88 insertions(+)
> > >
> > > diff --git a/arch/arm64/boot/dts/qcom/lemans.dtsi b/arch/arm64/boot/dts/qcom/lemans.dtsi
> > > index 48f753002fc459a3e9fac0c0e98cbec6013fea0f..45c11c050d3f8853701fd20cf647aef5c6a9a8c9 100644
> > > --- a/arch/arm64/boot/dts/qcom/lemans.dtsi
> > > +++ b/arch/arm64/boot/dts/qcom/lemans.dtsi
> > > @@ -6751,6 +6751,94 @@ compute-cb@3 {
> > > };
> > > };
> > > + mdss1: display-subsystem@22000000 {
> > Why do you need this label?
>
> display-controller@22001000 is using mdss1 as interrupt parent.
>
> >
> > > + compatible = "qcom,sa8775p-mdss";
> > > + reg = <0x0 0x22000000 0x0 0x1000>;
> > > + reg-names = "mdss";
> > > +
> > > + /* same path used twice */
> > > + interconnects = <&mmss_noc MASTER_MDP_CORE1_0 QCOM_ICC_TAG_ALWAYS
> > > + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
> > > + <&mmss_noc MASTER_MDP_CORE1_1 QCOM_ICC_TAG_ALWAYS
> > > + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
> > > + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
> > > + &config_noc SLAVE_DISPLAY_CFG QCOM_ICC_TAG_ACTIVE_ONLY>;
> > > + interconnect-names = "mdp0-mem",
> > > + "mdp1-mem",
> > > + "cpu-cfg";
> > > +
> > > + resets = <&dispcc1 MDSS_DISP_CC_MDSS_CORE_BCR>;
> > > +
> > > + power-domains = <&dispcc1 MDSS_DISP_CC_MDSS_CORE_GDSC>;
> > > +
> > > + clocks = <&dispcc1 MDSS_DISP_CC_MDSS_AHB_CLK>,
> > > + <&gcc GCC_DISP1_HF_AXI_CLK>,
> > > + <&dispcc1 MDSS_DISP_CC_MDSS_MDP_CLK>;
> > > +
> > > + interrupts = <GIC_SPI 865 IRQ_TYPE_LEVEL_HIGH>;
> > > + interrupt-controller;
> > > + #interrupt-cells = <1>;
> > > +
> > > + iommus = <&apps_smmu 0x1800 0x402>;
> > > +
> > > + #address-cells = <2>;
> > > + #size-cells = <2>;
> > > + ranges;
> > > +
> > > + status = "disabled";
> > > +
> > > + mdss1_mdp: display-controller@22001000 {
> > Why do you need this label?
>
> will remove.
>
> >
> > > + compatible = "qcom,sa8775p-dpu";
> > > + reg = <0x0 0x22001000 0x0 0x8f000>,
> > > + <0x0 0x220b0000 0x0 0x3000>;
> > > + reg-names = "mdp", "vbif";
> > > +
> > > + clocks = <&gcc GCC_DISP1_HF_AXI_CLK>,
> > > + <&dispcc1 MDSS_DISP_CC_MDSS_AHB_CLK>,
> > > + <&dispcc1 MDSS_DISP_CC_MDSS_MDP_LUT_CLK>,
> > > + <&dispcc1 MDSS_DISP_CC_MDSS_MDP_CLK>,
> > > + <&dispcc1 MDSS_DISP_CC_MDSS_VSYNC_CLK>;
> > > + clock-names = "nrt_bus",
> > > + "iface",
> > > + "lut",
> > > + "core",
> > > + "vsync";
> > > +
> > > + assigned-clocks = <&dispcc1 MDSS_DISP_CC_MDSS_VSYNC_CLK>;
> > > + assigned-clock-rates = <19200000>;
> > > +
> > > + operating-points-v2 = <&mdss1_mdp_opp_table>;
> > > + power-domains = <&rpmhpd SA8775P_MMCX>;
> > > +
> > > + interrupt-parent = <&mdss1>;
> > > + interrupts = <0>;
> > > +
> > > + mdss1_mdp_opp_table: opp-table {
> > > + compatible = "operating-points-v2";
> > > +
> > > + opp-375000000 {
> > > + opp-hz = /bits/ 64 <375000000>;
> > > + required-opps = <&rpmhpd_opp_svs_l1>;
> > > + };
> > > +
> > > + opp-500000000 {
> > > + opp-hz = /bits/ 64 <500000000>;
> > > + required-opps = <&rpmhpd_opp_nom>;
> > > + };
> > > +
> > > + opp-575000000 {
> > > + opp-hz = /bits/ 64 <575000000>;
> > > + required-opps = <&rpmhpd_opp_turbo>;
> > > + };
> > > +
> > > + opp-650000000 {
> > > + opp-hz = /bits/ 64 <650000000>;
> > > + required-opps = <&rpmhpd_opp_turbo_l1>;
> > > + };
> > > + };
> > > + };
> > > + };
> > > +
> > > dispcc1: clock-controller@22100000 {
> > > compatible = "qcom,sa8775p-dispcc1";
> > > reg = <0x0 0x22100000 0x0 0x20000>;
> > >
> > > ---
> > > base-commit: 846bd2225ec3cfa8be046655e02b9457ed41973e
> > > change-id: 20250923-lemans_dual-c03ad5c84a84
> > >
> > > Best regards,
> > > --
> > > Mahadevan <mahadevan.p@oss.qualcomm.com>
> > >
> Thanks,
> Mahadevan
^ permalink raw reply [flat|nested] 7+ messages in thread
end of thread, other threads:[~2025-10-17 22:48 UTC | newest]
Thread overview: 7+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2025-09-25 8:58 [PATCH] arm64: dts: qcom: lemans: add DT changes to enable MDSS1 and DPU Mahadevan
2025-09-25 10:49 ` Konrad Dybcio
2025-09-25 21:45 ` Dmitry Baryshkov
2025-09-25 21:41 ` Dmitry Baryshkov
2025-09-26 9:24 ` Mahadevan P
2025-09-26 10:43 ` Konrad Dybcio
2025-10-17 22:50 ` Bjorn Andersson
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