* [PATCH v6 1/8] arm64: dts: ti: am62p: Rename am62p-{}.dtsi to am62p-j722s-common-{}.dtsi
2024-06-12 13:24 [PATCH v6 0/8] Add PCIe, SERDES and USB DT support for J722S Siddharth Vadapalli
@ 2024-06-12 13:24 ` Siddharth Vadapalli
2024-06-14 9:45 ` Roger Quadros
2024-06-12 13:24 ` [PATCH v6 2/8] arm64: dts: ti: k3-am62p-j722s: Move AM62P specific USB1 to am62p-main.dtsi Siddharth Vadapalli
` (6 subsequent siblings)
7 siblings, 1 reply; 13+ messages in thread
From: Siddharth Vadapalli @ 2024-06-12 13:24 UTC (permalink / raw)
To: nm, vigneshr, afd, kristo, robh, krzk+dt, conor+dt, rogerq
Cc: devicetree, linux-kernel, linux-arm-kernel, u-kumar1,
danishanwar, srk, s-vadapalli
The AM62P and J722S SoCs share most of the peripherals. With the aim of
reusing the existing k3-am62p-{mcu,main,thermal,wakeup}.dtsi files for
J722S SoC, rename them to indicate that they are shared with the J722S SoC.
The peripherals that are not shared will be moved in the upcoming patches
to the respective k3-{soc}-{mcu,main,wakeup}.dtsi files without "common" in
the filename, emphasizing that they are not shared.
Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
Acked-by: Andrew Davis <afd@ti.com>
---
v5:
https://lore.kernel.org/r/20240604085252.3686037-2-s-vadapalli@ti.com/
Changes since v5:
- k3-am62p.dtsi is left as-is, instead of changing it to
k3-am62p-j722s-common.dtsi.
- Renamed k3-am62p-thermal.dtsi to k3-am62p-j722s-common-thermal.dtsi.
...k3-am62p-main.dtsi => k3-am62p-j722s-common-main.dtsi} | 3 ++-
.../{k3-am62p-mcu.dtsi => k3-am62p-j722s-common-mcu.dtsi} | 3 ++-
...2p-thermal.dtsi => k3-am62p-j722s-common-thermal.dtsi} | 0
...m62p-wakeup.dtsi => k3-am62p-j722s-common-wakeup.dtsi} | 3 ++-
arch/arm64/boot/dts/ti/k3-am62p.dtsi | 8 ++++----
5 files changed, 10 insertions(+), 7 deletions(-)
rename arch/arm64/boot/dts/ti/{k3-am62p-main.dtsi => k3-am62p-j722s-common-main.dtsi} (99%)
rename arch/arm64/boot/dts/ti/{k3-am62p-mcu.dtsi => k3-am62p-j722s-common-mcu.dtsi} (98%)
rename arch/arm64/boot/dts/ti/{k3-am62p-thermal.dtsi => k3-am62p-j722s-common-thermal.dtsi} (100%)
rename arch/arm64/boot/dts/ti/{k3-am62p-wakeup.dtsi => k3-am62p-j722s-common-wakeup.dtsi} (97%)
diff --git a/arch/arm64/boot/dts/ti/k3-am62p-main.dtsi b/arch/arm64/boot/dts/ti/k3-am62p-j722s-common-main.dtsi
similarity index 99%
rename from arch/arm64/boot/dts/ti/k3-am62p-main.dtsi
rename to arch/arm64/boot/dts/ti/k3-am62p-j722s-common-main.dtsi
index 900d1f9530a2..bf6384ba824a 100644
--- a/arch/arm64/boot/dts/ti/k3-am62p-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-am62p-j722s-common-main.dtsi
@@ -1,6 +1,7 @@
// SPDX-License-Identifier: GPL-2.0-only OR MIT
/*
- * Device Tree file for the AM62P main domain peripherals
+ * Device Tree file for the MAIN domain peripherals shared by AM62P and J722S
+ *
* Copyright (C) 2023-2024 Texas Instruments Incorporated - https://www.ti.com/
*/
diff --git a/arch/arm64/boot/dts/ti/k3-am62p-mcu.dtsi b/arch/arm64/boot/dts/ti/k3-am62p-j722s-common-mcu.dtsi
similarity index 98%
rename from arch/arm64/boot/dts/ti/k3-am62p-mcu.dtsi
rename to arch/arm64/boot/dts/ti/k3-am62p-j722s-common-mcu.dtsi
index b973b550eb9d..1d4e5fc8b4e0 100644
--- a/arch/arm64/boot/dts/ti/k3-am62p-mcu.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-am62p-j722s-common-mcu.dtsi
@@ -1,6 +1,7 @@
// SPDX-License-Identifier: GPL-2.0-only OR MIT
/*
- * Device Tree file for the AM62P MCU domain peripherals
+ * Device Tree file for the MCU domain peripherals shared by AM62P and J722S
+ *
* Copyright (C) 2023-2024 Texas Instruments Incorporated - https://www.ti.com/
*/
diff --git a/arch/arm64/boot/dts/ti/k3-am62p-thermal.dtsi b/arch/arm64/boot/dts/ti/k3-am62p-j722s-common-thermal.dtsi
similarity index 100%
rename from arch/arm64/boot/dts/ti/k3-am62p-thermal.dtsi
rename to arch/arm64/boot/dts/ti/k3-am62p-j722s-common-thermal.dtsi
diff --git a/arch/arm64/boot/dts/ti/k3-am62p-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-am62p-j722s-common-wakeup.dtsi
similarity index 97%
rename from arch/arm64/boot/dts/ti/k3-am62p-wakeup.dtsi
rename to arch/arm64/boot/dts/ti/k3-am62p-j722s-common-wakeup.dtsi
index c71d9624ea27..f6ec6e8e171d 100644
--- a/arch/arm64/boot/dts/ti/k3-am62p-wakeup.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-am62p-j722s-common-wakeup.dtsi
@@ -1,6 +1,7 @@
// SPDX-License-Identifier: GPL-2.0-only OR MIT
/*
- * Device Tree file for the AM62P wakeup domain peripherals
+ * Device Tree file for the WAKEUP domain peripherals shared by AM62P and J722S
+ *
* Copyright (C) 2023-2024 Texas Instruments Incorporated - https://www.ti.com/
*/
diff --git a/arch/arm64/boot/dts/ti/k3-am62p.dtsi b/arch/arm64/boot/dts/ti/k3-am62p.dtsi
index 94babc412575..2d11c80107b5 100644
--- a/arch/arm64/boot/dts/ti/k3-am62p.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-am62p.dtsi
@@ -116,10 +116,10 @@ cbass_wakeup: bus@b00000 {
};
};
- #include "k3-am62p-thermal.dtsi"
+ #include "k3-am62p-j722s-common-thermal.dtsi"
};
/* Now include peripherals for each bus segment */
-#include "k3-am62p-main.dtsi"
-#include "k3-am62p-mcu.dtsi"
-#include "k3-am62p-wakeup.dtsi"
+#include "k3-am62p-j722s-common-main.dtsi"
+#include "k3-am62p-j722s-common-mcu.dtsi"
+#include "k3-am62p-j722s-common-wakeup.dtsi"
--
2.40.1
^ permalink raw reply [flat|nested] 13+ messages in thread* Re: [PATCH v6 1/8] arm64: dts: ti: am62p: Rename am62p-{}.dtsi to am62p-j722s-common-{}.dtsi
2024-06-12 13:24 ` [PATCH v6 1/8] arm64: dts: ti: am62p: Rename am62p-{}.dtsi to am62p-j722s-common-{}.dtsi Siddharth Vadapalli
@ 2024-06-14 9:45 ` Roger Quadros
0 siblings, 0 replies; 13+ messages in thread
From: Roger Quadros @ 2024-06-14 9:45 UTC (permalink / raw)
To: Siddharth Vadapalli, nm, vigneshr, afd, kristo, robh, krzk+dt, conor+dt
Cc: devicetree, linux-kernel, linux-arm-kernel, u-kumar1, danishanwar, srk
On 12/06/2024 16:24, Siddharth Vadapalli wrote:
> The AM62P and J722S SoCs share most of the peripherals. With the aim of
> reusing the existing k3-am62p-{mcu,main,thermal,wakeup}.dtsi files for
> J722S SoC, rename them to indicate that they are shared with the J722S SoC.
>
> The peripherals that are not shared will be moved in the upcoming patches
> to the respective k3-{soc}-{mcu,main,wakeup}.dtsi files without "common" in
> the filename, emphasizing that they are not shared.
>
> Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
> Acked-by: Andrew Davis <afd@ti.com>
Acked-by: Roger Quadros <rogerq@kernel.org>
^ permalink raw reply [flat|nested] 13+ messages in thread
* [PATCH v6 2/8] arm64: dts: ti: k3-am62p-j722s: Move AM62P specific USB1 to am62p-main.dtsi
2024-06-12 13:24 [PATCH v6 0/8] Add PCIe, SERDES and USB DT support for J722S Siddharth Vadapalli
2024-06-12 13:24 ` [PATCH v6 1/8] arm64: dts: ti: am62p: Rename am62p-{}.dtsi to am62p-j722s-common-{}.dtsi Siddharth Vadapalli
@ 2024-06-12 13:24 ` Siddharth Vadapalli
2024-06-12 13:24 ` [PATCH v6 3/8] arm64: dts: ti: k3-j722s: Add main domain peripherals specific to J722S Siddharth Vadapalli
` (5 subsequent siblings)
7 siblings, 0 replies; 13+ messages in thread
From: Siddharth Vadapalli @ 2024-06-12 13:24 UTC (permalink / raw)
To: nm, vigneshr, afd, kristo, robh, krzk+dt, conor+dt, rogerq
Cc: devicetree, linux-kernel, linux-arm-kernel, u-kumar1,
danishanwar, srk, s-vadapalli
The USB1 instance of USB controller on AM62P is different from the USB1
instance of USB controller on J722S. Thus, move the USB1 instance from
the shared "k3-am62p-j722s-common-main.dtsi" file to the AM62p specific
"k3-am62p-main.dtsi" file. Include "k3-am62p-main.dtsi" in "k3-am62p.dtsi".
Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
Acked-by: Roger Quadros <rogerq@kernel.org>
---
v5:
https://lore.kernel.org/r/20240604085252.3686037-3-s-vadapalli@ti.com/
Changes since v5:
- Since this v6 series contains "k3-am62p.dtsi" rather than
"k3-am62p-j722s-common.dtsi", the equivalent change of the v5 patch
applies to "k3-am62p.dtsi" in the current patch.
- Collected Acked-by tag from Roger Quadros <rogerq@kernel.org>
.../dts/ti/k3-am62p-j722s-common-main.dtsi | 26 --------------
arch/arm64/boot/dts/ti/k3-am62p-main.dtsi | 34 +++++++++++++++++++
arch/arm64/boot/dts/ti/k3-am62p.dtsi | 3 ++
3 files changed, 37 insertions(+), 26 deletions(-)
create mode 100644 arch/arm64/boot/dts/ti/k3-am62p-main.dtsi
diff --git a/arch/arm64/boot/dts/ti/k3-am62p-j722s-common-main.dtsi b/arch/arm64/boot/dts/ti/k3-am62p-j722s-common-main.dtsi
index bf6384ba824a..80d2e559a473 100644
--- a/arch/arm64/boot/dts/ti/k3-am62p-j722s-common-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-am62p-j722s-common-main.dtsi
@@ -662,32 +662,6 @@ usb0: usb@31000000 {
};
};
- usbss1: usb@f910000 {
- compatible = "ti,am62-usb";
- reg = <0x00 0x0f910000 0x00 0x800>,
- <0x00 0x0f918000 0x00 0x400>;
- clocks = <&k3_clks 162 3>;
- clock-names = "ref";
- ti,syscon-phy-pll-refclk = <&usb1_phy_ctrl 0x0>;
- #address-cells = <2>;
- #size-cells = <2>;
- power-domains = <&k3_pds 179 TI_SCI_PD_EXCLUSIVE>;
- ranges;
- status = "disabled";
-
- usb1: usb@31100000 {
- compatible = "snps,dwc3";
- reg = <0x00 0x31100000 0x00 0x50000>;
- interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>, /* irq.0 */
- <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>; /* irq.0 */
- interrupt-names = "host", "peripheral";
- maximum-speed = "high-speed";
- dr_mode = "otg";
- snps,usb2-gadget-lpm-disable;
- snps,usb2-lpm-disable;
- };
- };
-
fss: bus@fc00000 {
compatible = "simple-bus";
reg = <0x00 0x0fc00000 0x00 0x70000>;
diff --git a/arch/arm64/boot/dts/ti/k3-am62p-main.dtsi b/arch/arm64/boot/dts/ti/k3-am62p-main.dtsi
new file mode 100644
index 000000000000..9caab7db5440
--- /dev/null
+++ b/arch/arm64/boot/dts/ti/k3-am62p-main.dtsi
@@ -0,0 +1,34 @@
+// SPDX-License-Identifier: GPL-2.0-only OR MIT
+/*
+ * Device Tree file for the AM62P MAIN domain peripherals
+ *
+ * Copyright (C) 2023-2024 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+&cbass_main {
+ usbss1: usb@f910000 {
+ compatible = "ti,am62-usb";
+ reg = <0x00 0x0f910000 0x00 0x800>,
+ <0x00 0x0f918000 0x00 0x400>;
+ clocks = <&k3_clks 162 3>;
+ clock-names = "ref";
+ ti,syscon-phy-pll-refclk = <&usb1_phy_ctrl 0x0>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ power-domains = <&k3_pds 179 TI_SCI_PD_EXCLUSIVE>;
+ ranges;
+ status = "disabled";
+
+ usb1: usb@31100000 {
+ compatible = "snps,dwc3";
+ reg = <0x00 0x31100000 0x00 0x50000>;
+ interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>, /* irq.0 */
+ <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>; /* irq.0 */
+ interrupt-names = "host", "peripheral";
+ maximum-speed = "high-speed";
+ dr_mode = "otg";
+ snps,usb2-gadget-lpm-disable;
+ snps,usb2-lpm-disable;
+ };
+ };
+};
diff --git a/arch/arm64/boot/dts/ti/k3-am62p.dtsi b/arch/arm64/boot/dts/ti/k3-am62p.dtsi
index 2d11c80107b5..75a15c368c11 100644
--- a/arch/arm64/boot/dts/ti/k3-am62p.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-am62p.dtsi
@@ -123,3 +123,6 @@ cbass_wakeup: bus@b00000 {
#include "k3-am62p-j722s-common-main.dtsi"
#include "k3-am62p-j722s-common-mcu.dtsi"
#include "k3-am62p-j722s-common-wakeup.dtsi"
+
+/* Include AM62P specific peripherals */
+#include "k3-am62p-main.dtsi"
--
2.40.1
^ permalink raw reply [flat|nested] 13+ messages in thread* [PATCH v6 3/8] arm64: dts: ti: k3-j722s: Add main domain peripherals specific to J722S
2024-06-12 13:24 [PATCH v6 0/8] Add PCIe, SERDES and USB DT support for J722S Siddharth Vadapalli
2024-06-12 13:24 ` [PATCH v6 1/8] arm64: dts: ti: am62p: Rename am62p-{}.dtsi to am62p-j722s-common-{}.dtsi Siddharth Vadapalli
2024-06-12 13:24 ` [PATCH v6 2/8] arm64: dts: ti: k3-am62p-j722s: Move AM62P specific USB1 to am62p-main.dtsi Siddharth Vadapalli
@ 2024-06-12 13:24 ` Siddharth Vadapalli
2024-06-12 13:24 ` [PATCH v6 4/8] arm64: dts: ti: k3-j722s: Switch to k3-am62p-j722s-common-{}.dtsi includes Siddharth Vadapalli
` (4 subsequent siblings)
7 siblings, 0 replies; 13+ messages in thread
From: Siddharth Vadapalli @ 2024-06-12 13:24 UTC (permalink / raw)
To: nm, vigneshr, afd, kristo, robh, krzk+dt, conor+dt, rogerq
Cc: devicetree, linux-kernel, linux-arm-kernel, u-kumar1,
danishanwar, srk, s-vadapalli
Introduce the "k3-j722s-main.dtsi" file to contain main domain peripherals
that are specific to J722S SoC and are not shared with AM62P. The USB1
instance of the USB controller on J722S is different from that on AM62P.
Thus, add the USB1 node in "k3-j722s-main.dtsi".
Co-developed-by: Ravi Gunasekaran <r-gunasekaran@ti.com>
Signed-off-by: Ravi Gunasekaran <r-gunasekaran@ti.com>
Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
Acked-by: Roger Quadros <rogerq@kernel.org>
---
v5:
https://lore.kernel.org/r/20240604085252.3686037-4-s-vadapalli@ti.com/
Changes since v5:
- Collected Acked-by tag from Roger Quadros <rogerq@kernel.org>
arch/arm64/boot/dts/ti/k3-j722s-main.dtsi | 40 +++++++++++++++++++++++
1 file changed, 40 insertions(+)
create mode 100644 arch/arm64/boot/dts/ti/k3-j722s-main.dtsi
diff --git a/arch/arm64/boot/dts/ti/k3-j722s-main.dtsi b/arch/arm64/boot/dts/ti/k3-j722s-main.dtsi
new file mode 100644
index 000000000000..84378fc839d6
--- /dev/null
+++ b/arch/arm64/boot/dts/ti/k3-j722s-main.dtsi
@@ -0,0 +1,40 @@
+// SPDX-License-Identifier: GPL-2.0-only OR MIT
+/*
+ * Device Tree file for the J722S MAIN domain peripherals
+ *
+ * Copyright (C) 2023-2024 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+&cbass_main {
+ usbss1: usb@f920000 {
+ compatible = "ti,j721e-usb";
+ reg = <0x00 0x0f920000 0x00 0x100>;
+ power-domains = <&k3_pds 278 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 278 3>, <&k3_clks 278 1>;
+ clock-names = "ref", "lpm";
+ assigned-clocks = <&k3_clks 278 3>; /* USB2_REFCLK */
+ assigned-clock-parents = <&k3_clks 278 4>; /* HF0SC0 */
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+ status = "disabled";
+
+ usb1: usb@31200000{
+ compatible = "cdns,usb3";
+ reg = <0x00 0x31200000 0x00 0x10000>,
+ <0x00 0x31210000 0x00 0x10000>,
+ <0x00 0x31220000 0x00 0x10000>;
+ reg-names = "otg",
+ "xhci",
+ "dev";
+ interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>, /* irq.0 */
+ <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>, /* irq.6 */
+ <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>; /* otgirq */
+ interrupt-names = "host",
+ "peripheral",
+ "otg";
+ maximum-speed = "super-speed";
+ dr_mode = "otg";
+ };
+ };
+};
--
2.40.1
^ permalink raw reply [flat|nested] 13+ messages in thread* [PATCH v6 4/8] arm64: dts: ti: k3-j722s: Switch to k3-am62p-j722s-common-{}.dtsi includes
2024-06-12 13:24 [PATCH v6 0/8] Add PCIe, SERDES and USB DT support for J722S Siddharth Vadapalli
` (2 preceding siblings ...)
2024-06-12 13:24 ` [PATCH v6 3/8] arm64: dts: ti: k3-j722s: Add main domain peripherals specific to J722S Siddharth Vadapalli
@ 2024-06-12 13:24 ` Siddharth Vadapalli
2024-06-14 9:46 ` Roger Quadros
2024-06-12 13:24 ` [PATCH v6 5/8] arm64: dts: ti: k3-j722s: Move MAIN domain overrides to k3-j722s-main.dtsi Siddharth Vadapalli
` (3 subsequent siblings)
7 siblings, 1 reply; 13+ messages in thread
From: Siddharth Vadapalli @ 2024-06-12 13:24 UTC (permalink / raw)
To: nm, vigneshr, afd, kristo, robh, krzk+dt, conor+dt, rogerq
Cc: devicetree, linux-kernel, linux-arm-kernel, u-kumar1,
danishanwar, srk, s-vadapalli
Update "k3-j722s.dtsi" to include "k3-am62p-j722s-common-{}".dtsi files in
order to reuse the nodes shared with AM62P. Also include the J722S specific
"k3-j722s-main.dtsi".
Since the J7 family of SoCs has the k3-{soc}.dtsi file organized as:
k3-{soc}.dtsi = CPU + Cache + CBASS-Ranges + "Peripheral-Includes"
switch the "k3-j722s.dtsi" file to the same convention.
Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
---
v5:
https://lore.kernel.org/r/20240604085252.3686037-5-s-vadapalli@ti.com/
Changes since v5:
- Rather than including "k3-am62p-j722s-common.dtsi" which is the
equivalent of "k3-am62p.dtsi" in the current series, k3-j722s.dtsi
includes "k3-am62p-j722s-common-{}.dtsi" and "k3-j722s-main.dtsi".
Also, to match the J7 family of SoCs, the CPU, Cache and CBASS-Ranges
are included in "k3-j722s.dtsi".
arch/arm64/boot/dts/ti/k3-j722s.dtsi | 158 ++++++++++++++++++++++++++-
1 file changed, 157 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/ti/k3-j722s.dtsi b/arch/arm64/boot/dts/ti/k3-j722s.dtsi
index c75744edb143..1bcbc9152ff0 100644
--- a/arch/arm64/boot/dts/ti/k3-j722s.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j722s.dtsi
@@ -10,11 +10,133 @@
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/soc/ti,sci_pm_domain.h>
-#include "k3-am62p5.dtsi"
+#include "k3-pinctrl.h"
/ {
model = "Texas Instruments K3 J722S SoC";
compatible = "ti,j722s";
+ interrupt-parent = <&gic500>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu-map {
+ cluster0: cluster0 {
+ core0 {
+ cpu = <&cpu0>;
+ };
+
+ core1 {
+ cpu = <&cpu1>;
+ };
+
+ core2 {
+ cpu = <&cpu2>;
+ };
+
+ core3 {
+ cpu = <&cpu3>;
+ };
+ };
+ };
+
+ cpu0: cpu@0 {
+ compatible = "arm,cortex-a53";
+ reg = <0x000>;
+ device_type = "cpu";
+ enable-method = "psci";
+ i-cache-size = <0x8000>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>;
+ d-cache-size = <0x8000>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <128>;
+ next-level-cache = <&l2_0>;
+ clocks = <&k3_clks 135 0>;
+ };
+
+ cpu1: cpu@1 {
+ compatible = "arm,cortex-a53";
+ reg = <0x001>;
+ device_type = "cpu";
+ enable-method = "psci";
+ i-cache-size = <0x8000>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>;
+ d-cache-size = <0x8000>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <128>;
+ next-level-cache = <&l2_0>;
+ clocks = <&k3_clks 136 0>;
+ };
+
+ cpu2: cpu@2 {
+ compatible = "arm,cortex-a53";
+ reg = <0x002>;
+ device_type = "cpu";
+ enable-method = "psci";
+ i-cache-size = <0x8000>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>;
+ d-cache-size = <0x8000>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <128>;
+ next-level-cache = <&l2_0>;
+ clocks = <&k3_clks 137 0>;
+ };
+
+ cpu3: cpu@3 {
+ compatible = "arm,cortex-a53";
+ reg = <0x003>;
+ device_type = "cpu";
+ enable-method = "psci";
+ i-cache-size = <0x8000>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>;
+ d-cache-size = <0x8000>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <128>;
+ next-level-cache = <&l2_0>;
+ clocks = <&k3_clks 138 0>;
+ };
+ };
+
+ l2_0: l2-cache0 {
+ compatible = "cache";
+ cache-unified;
+ cache-level = <2>;
+ cache-size = <0x80000>;
+ cache-line-size = <64>;
+ cache-sets = <512>;
+ };
+
+ firmware {
+ optee {
+ compatible = "linaro,optee-tz";
+ method = "smc";
+ };
+
+ psci: psci {
+ compatible = "arm,psci-1.0";
+ method = "smc";
+ };
+ };
+
+ a53_timer0: timer-cl0-cpu0 {
+ compatible = "arm,armv8-timer";
+ interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, /* cntpsirq */
+ <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, /* cntpnsirq */
+ <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, /* cntvirq */
+ <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; /* cnthpirq */
+ };
+
+ pmu: pmu {
+ compatible = "arm,cortex-a53-pmu";
+ interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
+ };
cbass_main: bus@f0000 {
compatible = "simple-bus";
@@ -74,9 +196,43 @@ cbass_main: bus@f0000 {
<0x00 0x43000000 0x00 0x43000000 0x00 0x00020000>,
<0x00 0x78000000 0x00 0x78000000 0x00 0x00008000>,
<0x00 0x78100000 0x00 0x78100000 0x00 0x00008000>;
+
+ cbass_mcu: bus@4000000 {
+ compatible = "simple-bus";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges = <0x00 0x04000000 0x00 0x04000000 0x00 0x01ff1400>, /* Peripheral window */
+ <0x00 0x79000000 0x00 0x79000000 0x00 0x00008000>, /* MCU R5 ATCM */
+ <0x00 0x79020000 0x00 0x79020000 0x00 0x00008000>, /* MCU R5 BTCM */
+ <0x00 0x79100000 0x00 0x79100000 0x00 0x00040000>, /* MCU IRAM0 */
+ <0x00 0x79140000 0x00 0x79140000 0x00 0x00040000>; /* MCU IRAM1 */
+ bootph-all;
+ };
+
+ cbass_wakeup: bus@b00000 {
+ compatible = "simple-bus";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges = <0x00 0x00b00000 0x00 0x00b00000 0x00 0x00002400>, /* VTM */
+ <0x00 0x2b000000 0x00 0x2b000000 0x00 0x00300400>, /* Peripheral Window */
+ <0x00 0x43000000 0x00 0x43000000 0x00 0x00020000>, /* WKUP CTRL MMR */
+ <0x00 0x78000000 0x00 0x78000000 0x00 0x00008000>, /* DM R5 ATCM*/
+ <0x00 0x78100000 0x00 0x78100000 0x00 0x00008000>; /* DM R5 BTCM*/
+ bootph-all;
+ };
};
+
+ #include "k3-am62p-j722s-common-thermal.dtsi"
};
+/* Include peripherals shared with AM62P */
+#include "k3-am62p-j722s-common-main.dtsi"
+#include "k3-am62p-j722s-common-mcu.dtsi"
+#include "k3-am62p-j722s-common-wakeup.dtsi"
+
+/* Include J722S specific peripherals */
+#include "k3-j722s-main.dtsi"
+
/* Main domain overrides */
&inta_main_dmss {
--
2.40.1
^ permalink raw reply [flat|nested] 13+ messages in thread* Re: [PATCH v6 4/8] arm64: dts: ti: k3-j722s: Switch to k3-am62p-j722s-common-{}.dtsi includes
2024-06-12 13:24 ` [PATCH v6 4/8] arm64: dts: ti: k3-j722s: Switch to k3-am62p-j722s-common-{}.dtsi includes Siddharth Vadapalli
@ 2024-06-14 9:46 ` Roger Quadros
0 siblings, 0 replies; 13+ messages in thread
From: Roger Quadros @ 2024-06-14 9:46 UTC (permalink / raw)
To: Siddharth Vadapalli, nm, vigneshr, afd, kristo, robh, krzk+dt, conor+dt
Cc: devicetree, linux-kernel, linux-arm-kernel, u-kumar1, danishanwar, srk
On 12/06/2024 16:24, Siddharth Vadapalli wrote:
> Update "k3-j722s.dtsi" to include "k3-am62p-j722s-common-{}".dtsi files in
> order to reuse the nodes shared with AM62P. Also include the J722S specific
> "k3-j722s-main.dtsi".
>
> Since the J7 family of SoCs has the k3-{soc}.dtsi file organized as:
> k3-{soc}.dtsi = CPU + Cache + CBASS-Ranges + "Peripheral-Includes"
> switch the "k3-j722s.dtsi" file to the same convention.
>
> Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
Acked-by: Roger Quadros <rogerq@kernel.org>
^ permalink raw reply [flat|nested] 13+ messages in thread
* [PATCH v6 5/8] arm64: dts: ti: k3-j722s: Move MAIN domain overrides to k3-j722s-main.dtsi
2024-06-12 13:24 [PATCH v6 0/8] Add PCIe, SERDES and USB DT support for J722S Siddharth Vadapalli
` (3 preceding siblings ...)
2024-06-12 13:24 ` [PATCH v6 4/8] arm64: dts: ti: k3-j722s: Switch to k3-am62p-j722s-common-{}.dtsi includes Siddharth Vadapalli
@ 2024-06-12 13:24 ` Siddharth Vadapalli
2024-06-14 9:53 ` Roger Quadros
2024-06-12 13:24 ` [PATCH v6 6/8] arm64: dts: ti: k3-serdes: Add SERDES0/SERDES1 lane-muxing macros for J722S Siddharth Vadapalli
` (2 subsequent siblings)
7 siblings, 1 reply; 13+ messages in thread
From: Siddharth Vadapalli @ 2024-06-12 13:24 UTC (permalink / raw)
To: nm, vigneshr, afd, kristo, robh, krzk+dt, conor+dt, rogerq
Cc: devicetree, linux-kernel, linux-arm-kernel, u-kumar1,
danishanwar, srk, s-vadapalli
Since the MAIN domain peripherals specific to J722S SoC are present in the
"k3-j722s-main.dtsi" file, move the overrides for the MAIN domain from the
"k3-j722s.dtsi" file to the "k3-j722s-main.dtsi" file.
Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
---
This patch has been newly introduced in this series and doesn't have a
Changelog.
arch/arm64/boot/dts/ti/k3-j722s-main.dtsi | 11 +++++++++++
arch/arm64/boot/dts/ti/k3-j722s.dtsi | 11 -----------
2 files changed, 11 insertions(+), 11 deletions(-)
diff --git a/arch/arm64/boot/dts/ti/k3-j722s-main.dtsi b/arch/arm64/boot/dts/ti/k3-j722s-main.dtsi
index 84378fc839d6..b75dab8230c2 100644
--- a/arch/arm64/boot/dts/ti/k3-j722s-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j722s-main.dtsi
@@ -38,3 +38,14 @@ usb1: usb@31200000{
};
};
};
+
+/* MAIN domain overrides */
+
+&inta_main_dmss {
+ ti,interrupt-ranges = <7 71 21>;
+};
+
+&oc_sram {
+ reg = <0x00 0x70000000 0x00 0x40000>;
+ ranges = <0x00 0x00 0x70000000 0x40000>;
+};
diff --git a/arch/arm64/boot/dts/ti/k3-j722s.dtsi b/arch/arm64/boot/dts/ti/k3-j722s.dtsi
index 1bcbc9152ff0..14c6c6a332ef 100644
--- a/arch/arm64/boot/dts/ti/k3-j722s.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j722s.dtsi
@@ -232,14 +232,3 @@ cbass_wakeup: bus@b00000 {
/* Include J722S specific peripherals */
#include "k3-j722s-main.dtsi"
-
-/* Main domain overrides */
-
-&inta_main_dmss {
- ti,interrupt-ranges = <7 71 21>;
-};
-
-&oc_sram {
- reg = <0x00 0x70000000 0x00 0x40000>;
- ranges = <0x00 0x00 0x70000000 0x40000>;
-};
--
2.40.1
^ permalink raw reply [flat|nested] 13+ messages in thread* Re: [PATCH v6 5/8] arm64: dts: ti: k3-j722s: Move MAIN domain overrides to k3-j722s-main.dtsi
2024-06-12 13:24 ` [PATCH v6 5/8] arm64: dts: ti: k3-j722s: Move MAIN domain overrides to k3-j722s-main.dtsi Siddharth Vadapalli
@ 2024-06-14 9:53 ` Roger Quadros
2024-06-14 14:59 ` Siddharth Vadapalli
0 siblings, 1 reply; 13+ messages in thread
From: Roger Quadros @ 2024-06-14 9:53 UTC (permalink / raw)
To: Siddharth Vadapalli, nm, vigneshr, afd, kristo, robh, krzk+dt, conor+dt
Cc: devicetree, linux-kernel, linux-arm-kernel, u-kumar1, danishanwar, srk
Hi Siddharth,
On 12/06/2024 16:24, Siddharth Vadapalli wrote:
> Since the MAIN domain peripherals specific to J722S SoC are present in the
> "k3-j722s-main.dtsi" file, move the overrides for the MAIN domain from the
> "k3-j722s.dtsi" file to the "k3-j722s-main.dtsi" file.
Overrides is kind of a misnomer here. It looks like these are J722S specific
changes.
>
> Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
> ---
> This patch has been newly introduced in this series and doesn't have a
> Changelog.
>
> arch/arm64/boot/dts/ti/k3-j722s-main.dtsi | 11 +++++++++++
> arch/arm64/boot/dts/ti/k3-j722s.dtsi | 11 -----------
> 2 files changed, 11 insertions(+), 11 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/ti/k3-j722s-main.dtsi b/arch/arm64/boot/dts/ti/k3-j722s-main.dtsi
> index 84378fc839d6..b75dab8230c2 100644
> --- a/arch/arm64/boot/dts/ti/k3-j722s-main.dtsi
> +++ b/arch/arm64/boot/dts/ti/k3-j722s-main.dtsi
> @@ -38,3 +38,14 @@ usb1: usb@31200000{
> };
> };
> };
> +
> +/* MAIN domain overrides */
> +
> +&inta_main_dmss {
> + ti,interrupt-ranges = <7 71 21>;
> +};
> +
> +&oc_sram {
> + reg = <0x00 0x70000000 0x00 0x40000>;
> + ranges = <0x00 0x00 0x70000000 0x40000>;
> +};
> diff --git a/arch/arm64/boot/dts/ti/k3-j722s.dtsi b/arch/arm64/boot/dts/ti/k3-j722s.dtsi
> index 1bcbc9152ff0..14c6c6a332ef 100644
> --- a/arch/arm64/boot/dts/ti/k3-j722s.dtsi
> +++ b/arch/arm64/boot/dts/ti/k3-j722s.dtsi
> @@ -232,14 +232,3 @@ cbass_wakeup: bus@b00000 {
>
> /* Include J722S specific peripherals */
> #include "k3-j722s-main.dtsi"
> -
> -/* Main domain overrides */
> -
> -&inta_main_dmss {
> - ti,interrupt-ranges = <7 71 21>;
> -};
> -
> -&oc_sram {
> - reg = <0x00 0x70000000 0x00 0x40000>;
> - ranges = <0x00 0x00 0x70000000 0x40000>;
> -};
These are originally set in k3-am62p-j722s-common-main.dtsi
which cannot be as they are not common to both SoCs.
Should we be moving the AM62 specific portion into k3-am62p-main.dtsi.
So they are no longer overrides but SoC specific changes?
--
cheers,
-roger
^ permalink raw reply [flat|nested] 13+ messages in thread* Re: [PATCH v6 5/8] arm64: dts: ti: k3-j722s: Move MAIN domain overrides to k3-j722s-main.dtsi
2024-06-14 9:53 ` Roger Quadros
@ 2024-06-14 14:59 ` Siddharth Vadapalli
0 siblings, 0 replies; 13+ messages in thread
From: Siddharth Vadapalli @ 2024-06-14 14:59 UTC (permalink / raw)
To: Roger Quadros
Cc: Siddharth Vadapalli, nm, vigneshr, afd, kristo, robh, krzk+dt,
conor+dt, devicetree, linux-kernel, linux-arm-kernel, u-kumar1,
danishanwar, srk
On Fri, Jun 14, 2024 at 12:53:37PM +0300, Roger Quadros wrote:
> Hi Siddharth,
[...]
> > --- a/arch/arm64/boot/dts/ti/k3-j722s.dtsi
> > +++ b/arch/arm64/boot/dts/ti/k3-j722s.dtsi
> > @@ -232,14 +232,3 @@ cbass_wakeup: bus@b00000 {
> >
> > /* Include J722S specific peripherals */
> > #include "k3-j722s-main.dtsi"
> > -
> > -/* Main domain overrides */
> > -
> > -&inta_main_dmss {
> > - ti,interrupt-ranges = <7 71 21>;
> > -};
> > -
> > -&oc_sram {
> > - reg = <0x00 0x70000000 0x00 0x40000>;
> > - ranges = <0x00 0x00 0x70000000 0x40000>;
> > -};
> These are originally set in k3-am62p-j722s-common-main.dtsi
> which cannot be as they are not common to both SoCs.
>
> Should we be moving the AM62 specific portion into k3-am62p-main.dtsi.
>
> So they are no longer overrides but SoC specific changes?
Roger,
Thank you for reviewing the patch. I will remove the above properties
within the respective nodes of k3-am62p-j722s-common-main.dtsi and add
them to match the respective SoC in k3-{soc}-main.dtsi.
Regards,
Siddharth.
^ permalink raw reply [flat|nested] 13+ messages in thread
* [PATCH v6 6/8] arm64: dts: ti: k3-serdes: Add SERDES0/SERDES1 lane-muxing macros for J722S
2024-06-12 13:24 [PATCH v6 0/8] Add PCIe, SERDES and USB DT support for J722S Siddharth Vadapalli
` (4 preceding siblings ...)
2024-06-12 13:24 ` [PATCH v6 5/8] arm64: dts: ti: k3-j722s: Move MAIN domain overrides to k3-j722s-main.dtsi Siddharth Vadapalli
@ 2024-06-12 13:24 ` Siddharth Vadapalli
2024-06-12 13:24 ` [PATCH v6 7/8] arm64: dts: ti: k3-j722s-main: Add SERDES and PCIe support Siddharth Vadapalli
2024-06-12 13:24 ` [PATCH v6 8/8] arm64: dts: ti: k3-j722s: Enable PCIe and USB support on J722S-EVM Siddharth Vadapalli
7 siblings, 0 replies; 13+ messages in thread
From: Siddharth Vadapalli @ 2024-06-12 13:24 UTC (permalink / raw)
To: nm, vigneshr, afd, kristo, robh, krzk+dt, conor+dt, rogerq
Cc: devicetree, linux-kernel, linux-arm-kernel, u-kumar1,
danishanwar, srk, s-vadapalli
The SERDES0 and SERDES1 instances of SERDES on J722S are single lane
SERDES which are individually muxed across different peripherals.
LANE0 of SERDES0 is muxed between USB and CPSW while LANE0 of SERDES1 is
muxed between PCIe and CPSW.
Define the lane-muxing macros to be used as the idle state values.
Co-developed-by: Ravi Gunasekaran <r-gunasekaran@ti.com>
Signed-off-by: Ravi Gunasekaran <r-gunasekaran@ti.com>
Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
Reviewed-by: Roger Quadros <rogerq@kernel.org>
---
v5:
https://lore.kernel.org/r/20240604085252.3686037-6-s-vadapalli@ti.com/
Changes since v5:
- Collected Reviewed-by tag from Roger Quadros <rogerq@kernel.org>
arch/arm64/boot/dts/ti/k3-serdes.h | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/arch/arm64/boot/dts/ti/k3-serdes.h b/arch/arm64/boot/dts/ti/k3-serdes.h
index a011ad893b44..ef3606068140 100644
--- a/arch/arm64/boot/dts/ti/k3-serdes.h
+++ b/arch/arm64/boot/dts/ti/k3-serdes.h
@@ -201,4 +201,12 @@
#define J784S4_SERDES4_LANE3_USB 0x2
#define J784S4_SERDES4_LANE3_IP4_UNUSED 0x3
+/* J722S */
+
+#define J722S_SERDES0_LANE0_USB 0x0
+#define J722S_SERDES0_LANE0_QSGMII_LANE2 0x1
+
+#define J722S_SERDES1_LANE0_PCIE0_LANE0 0x0
+#define J722S_SERDES1_LANE0_QSGMII_LANE1 0x1
+
#endif /* DTS_ARM64_TI_K3_SERDES_H */
--
2.40.1
^ permalink raw reply [flat|nested] 13+ messages in thread* [PATCH v6 7/8] arm64: dts: ti: k3-j722s-main: Add SERDES and PCIe support
2024-06-12 13:24 [PATCH v6 0/8] Add PCIe, SERDES and USB DT support for J722S Siddharth Vadapalli
` (5 preceding siblings ...)
2024-06-12 13:24 ` [PATCH v6 6/8] arm64: dts: ti: k3-serdes: Add SERDES0/SERDES1 lane-muxing macros for J722S Siddharth Vadapalli
@ 2024-06-12 13:24 ` Siddharth Vadapalli
2024-06-12 13:24 ` [PATCH v6 8/8] arm64: dts: ti: k3-j722s: Enable PCIe and USB support on J722S-EVM Siddharth Vadapalli
7 siblings, 0 replies; 13+ messages in thread
From: Siddharth Vadapalli @ 2024-06-12 13:24 UTC (permalink / raw)
To: nm, vigneshr, afd, kristo, robh, krzk+dt, conor+dt, rogerq
Cc: devicetree, linux-kernel, linux-arm-kernel, u-kumar1,
danishanwar, srk, s-vadapalli
J722S SoC has two instances of SERDES namely SERDES0 and SERDES1 and one
instance of PCIe namely PCIe0. Both SERDES0 and SERDES1 are single lane
SERDES. The PCIe0 instance of PCIe is a Gen3 single lane PCIe controller.
Since SERDES and PCIe are not present on AM62P SoC, add the device-tree
nodes corresponding to them in the J722S SoC specific "k3-j722s-main.dtsi"
file.
Co-developed-by: Ravi Gunasekaran <r-gunasekaran@ti.com>
Signed-off-by: Ravi Gunasekaran <r-gunasekaran@ti.com>
Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
Acked-by: Roger Quadros <rogerq@kernel.org>
---
v5:
https://lore.kernel.org/r/20240604085252.3686037-7-s-vadapalli@ti.com/
Changes since v5:
- Collected Acked-by tag from Roger Quadros <rogerq@kernel.org>
arch/arm64/boot/dts/ti/k3-j722s-main.dtsi | 133 ++++++++++++++++++++++
1 file changed, 133 insertions(+)
diff --git a/arch/arm64/boot/dts/ti/k3-j722s-main.dtsi b/arch/arm64/boot/dts/ti/k3-j722s-main.dtsi
index b75dab8230c2..e1465daa0c96 100644
--- a/arch/arm64/boot/dts/ti/k3-j722s-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j722s-main.dtsi
@@ -5,7 +5,123 @@
* Copyright (C) 2023-2024 Texas Instruments Incorporated - https://www.ti.com/
*/
+#include <dt-bindings/phy/phy-cadence.h>
+#include <dt-bindings/phy/phy-ti.h>
+
+/ {
+ serdes_refclk: clk-0 {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <0>;
+ };
+};
+
&cbass_main {
+ serdes_wiz0: phy@f000000 {
+ compatible = "ti,am64-wiz-10g";
+ ranges = <0x0f000000 0x0 0x0f000000 0x00010000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ power-domains = <&k3_pds 279 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 279 0>, <&k3_clks 279 1>, <&serdes_refclk>;
+ clock-names = "fck", "core_ref_clk", "ext_ref_clk";
+ num-lanes = <1>;
+ #reset-cells = <1>;
+ #clock-cells = <1>;
+
+ assigned-clocks = <&k3_clks 279 1>;
+ assigned-clock-parents = <&k3_clks 279 5>;
+
+ serdes0: serdes@f000000 {
+ compatible = "ti,j721e-serdes-10g";
+ reg = <0x0f000000 0x00010000>;
+ reg-names = "torrent_phy";
+ resets = <&serdes_wiz0 0>;
+ reset-names = "torrent_reset";
+ clocks = <&serdes_wiz0 TI_WIZ_PLL0_REFCLK>,
+ <&serdes_wiz0 TI_WIZ_PHY_EN_REFCLK>;
+ clock-names = "refclk", "phy_en_refclk";
+ assigned-clocks = <&serdes_wiz0 TI_WIZ_PLL0_REFCLK>,
+ <&serdes_wiz0 TI_WIZ_PLL1_REFCLK>,
+ <&serdes_wiz0 TI_WIZ_REFCLK_DIG>;
+ assigned-clock-parents = <&k3_clks 279 1>,
+ <&k3_clks 279 1>,
+ <&k3_clks 279 1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #clock-cells = <1>;
+
+ status = "disabled"; /* Needs lane config */
+ };
+ };
+
+ serdes_wiz1: phy@f010000 {
+ compatible = "ti,am64-wiz-10g";
+ ranges = <0x0f010000 0x0 0x0f010000 0x00010000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ power-domains = <&k3_pds 280 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 280 0>, <&k3_clks 280 1>, <&serdes_refclk>;
+ clock-names = "fck", "core_ref_clk", "ext_ref_clk";
+ num-lanes = <1>;
+ #reset-cells = <1>;
+ #clock-cells = <1>;
+
+ assigned-clocks = <&k3_clks 280 1>;
+ assigned-clock-parents = <&k3_clks 280 5>;
+
+ serdes1: serdes@f010000 {
+ compatible = "ti,j721e-serdes-10g";
+ reg = <0x0f010000 0x00010000>;
+ reg-names = "torrent_phy";
+ resets = <&serdes_wiz1 0>;
+ reset-names = "torrent_reset";
+ clocks = <&serdes_wiz1 TI_WIZ_PLL0_REFCLK>,
+ <&serdes_wiz1 TI_WIZ_PHY_EN_REFCLK>;
+ clock-names = "refclk", "phy_en_refclk";
+ assigned-clocks = <&serdes_wiz1 TI_WIZ_PLL0_REFCLK>,
+ <&serdes_wiz1 TI_WIZ_PLL1_REFCLK>,
+ <&serdes_wiz1 TI_WIZ_REFCLK_DIG>;
+ assigned-clock-parents = <&k3_clks 280 1>,
+ <&k3_clks 280 1>,
+ <&k3_clks 280 1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #clock-cells = <1>;
+
+ status = "disabled"; /* Needs lane config */
+ };
+ };
+
+ pcie0_rc: pcie@f102000 {
+ compatible = "ti,j722s-pcie-host", "ti,j721e-pcie-host";
+ reg = <0x00 0x0f102000 0x00 0x1000>,
+ <0x00 0x0f100000 0x00 0x400>,
+ <0x00 0x0d000000 0x00 0x00800000>,
+ <0x00 0x68000000 0x00 0x00001000>;
+ reg-names = "intd_cfg", "user_cfg", "reg", "cfg";
+ ranges = <0x01000000 0x00 0x68001000 0x00 0x68001000 0x00 0x0010000>,
+ <0x02000000 0x00 0x68011000 0x00 0x68011000 0x00 0x7fef000>;
+ dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>;
+ interrupt-names = "link_state";
+ interrupts = <GIC_SPI 99 IRQ_TYPE_EDGE_RISING>;
+ device_type = "pci";
+ max-link-speed = <3>;
+ num-lanes = <1>;
+ power-domains = <&k3_pds 259 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 259 0>, <&serdes1 CDNS_TORRENT_REFCLK_DRIVER>;
+ clock-names = "fck", "pcie_refclk";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ bus-range = <0x0 0xff>;
+ vendor-id = <0x104c>;
+ device-id = <0xb010>;
+ cdns,no-bar-match-nbits = <64>;
+ ti,syscon-pcie-ctrl = <&pcie0_ctrl 0x0>;
+ msi-map = <0x0 &gic_its 0x0 0x10000>;
+ status = "disabled";
+ };
+
usbss1: usb@f920000 {
compatible = "ti,j721e-usb";
reg = <0x00 0x0f920000 0x00 0x100>;
@@ -39,6 +155,23 @@ usb1: usb@31200000{
};
};
+&main_conf {
+ serdes_ln_ctrl: mux-controller@4080 {
+ compatible = "reg-mux";
+ reg = <0x4080 0x14>;
+ #mux-control-cells = <1>;
+ mux-reg-masks = <0x00 0x3>, /* SERDES0 lane0 select */
+ <0x10 0x3>; /* SERDES1 lane0 select */
+ };
+};
+
+&wkup_conf {
+ pcie0_ctrl: pcie0-ctrl@4070 {
+ compatible = "ti,j784s4-pcie-ctrl", "syscon";
+ reg = <0x4070 0x4>;
+ };
+};
+
/* MAIN domain overrides */
&inta_main_dmss {
--
2.40.1
^ permalink raw reply [flat|nested] 13+ messages in thread* [PATCH v6 8/8] arm64: dts: ti: k3-j722s: Enable PCIe and USB support on J722S-EVM
2024-06-12 13:24 [PATCH v6 0/8] Add PCIe, SERDES and USB DT support for J722S Siddharth Vadapalli
` (6 preceding siblings ...)
2024-06-12 13:24 ` [PATCH v6 7/8] arm64: dts: ti: k3-j722s-main: Add SERDES and PCIe support Siddharth Vadapalli
@ 2024-06-12 13:24 ` Siddharth Vadapalli
7 siblings, 0 replies; 13+ messages in thread
From: Siddharth Vadapalli @ 2024-06-12 13:24 UTC (permalink / raw)
To: nm, vigneshr, afd, kristo, robh, krzk+dt, conor+dt, rogerq
Cc: devicetree, linux-kernel, linux-arm-kernel, u-kumar1,
danishanwar, srk, s-vadapalli
Enable PCIe0 instance of PCIe in Root Complex mode of operation with Lane 0
of the SERDES1 instance of SERDES. Also enable USB0 instance of USB to
interface with the Type-C port via the USB hub, by configuring the pin P05
of the GPIO expander on the EVM. Enable USB1 instance of USB in SuperSpeed
mode of operation with Lane 0 of the SERDES0 instance of SERDES.
Co-developed-by: Ravi Gunasekaran <r-gunasekaran@ti.com>
Signed-off-by: Ravi Gunasekaran <r-gunasekaran@ti.com>
Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
Acked-by: Roger Quadros <rogerq@kernel.org>
---
v5:
https://lore.kernel.org/r/20240604085252.3686037-7-s-vadapalli@ti.com/
Changes since v5:
- Collected Acked-by tag from Roger Quadros <rogerq@kernel.org>
arch/arm64/boot/dts/ti/k3-j722s-evm.dts | 73 +++++++++++++++++++++++++
1 file changed, 73 insertions(+)
diff --git a/arch/arm64/boot/dts/ti/k3-j722s-evm.dts b/arch/arm64/boot/dts/ti/k3-j722s-evm.dts
index bf3c246d13d1..253b02f0437d 100644
--- a/arch/arm64/boot/dts/ti/k3-j722s-evm.dts
+++ b/arch/arm64/boot/dts/ti/k3-j722s-evm.dts
@@ -9,7 +9,9 @@
/dts-v1/;
#include <dt-bindings/net/ti-dp83867.h>
+#include <dt-bindings/phy/phy.h>
#include "k3-j722s.dtsi"
+#include "k3-serdes.h"
/ {
compatible = "ti,j722s-evm", "ti,j722s";
@@ -202,6 +204,12 @@ J722S_IOPAD(0x0130, PIN_OUTPUT, 0) /* (AG26) RGMII1_TXC */
J722S_IOPAD(0x012c, PIN_OUTPUT, 0) /* (AF25) RGMII1_TX_CTL */
>;
};
+
+ main_usb1_pins_default: main-usb1-default-pins {
+ pinctrl-single,pins = <
+ J722S_IOPAD(0x0258, PIN_INPUT, 0) /* (B27) USB1_DRVVBUS */
+ >;
+ };
};
&cpsw3g {
@@ -301,6 +309,13 @@ exp1: gpio@23 {
"PCIe0_1L_RC_RSTz", "PCIe0_1L_PRSNT#",
"ENET1_EXP_SPARE2", "ENET1_EXP_PWRDN",
"PD_I2ENET1_I2CMUX_SELC_IRQ", "ENET1_EXP_RESETZ";
+
+ p05-hog {
+ /* P05 - USB2.0_MUX_SEL */
+ gpio-hog;
+ gpios = <5 GPIO_ACTIVE_HIGH>;
+ output-high;
+ };
};
};
@@ -384,3 +399,61 @@ &sdhci1 {
status = "okay";
bootph-all;
};
+
+&serdes_ln_ctrl {
+ idle-states = <J722S_SERDES0_LANE0_USB>,
+ <J722S_SERDES1_LANE0_PCIE0_LANE0>;
+};
+
+&serdes0 {
+ status = "okay";
+ serdes0_usb_link: phy@0 {
+ reg = <0>;
+ cdns,num-lanes = <1>;
+ #phy-cells = <0>;
+ cdns,phy-type = <PHY_TYPE_USB3>;
+ resets = <&serdes_wiz0 1>;
+ };
+};
+
+&serdes1 {
+ status = "okay";
+ serdes1_pcie_link: phy@0 {
+ reg = <0>;
+ cdns,num-lanes = <1>;
+ #phy-cells = <0>;
+ cdns,phy-type = <PHY_TYPE_PCIE>;
+ resets = <&serdes_wiz1 1>;
+ };
+};
+
+&pcie0_rc {
+ reset-gpios = <&exp1 18 GPIO_ACTIVE_HIGH>;
+ phys = <&serdes1_pcie_link>;
+ phy-names = "pcie-phy";
+ status = "okay";
+};
+
+&usbss0 {
+ ti,vbus-divider;
+ status = "okay";
+};
+
+&usb0 {
+ dr_mode = "otg";
+ usb-role-switch;
+};
+
+&usbss1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&main_usb1_pins_default>;
+ ti,vbus-divider;
+ status = "okay";
+};
+
+&usb1 {
+ dr_mode = "host";
+ maximum-speed = "super-speed";
+ phys = <&serdes0_usb_link>;
+ phy-names = "cdns3,usb3-phy";
+};
--
2.40.1
^ permalink raw reply [flat|nested] 13+ messages in thread