* [PATCH v3 RESEND 1/6] x86/amd_nb: Add AMD Family 17h A0-AF IDs
2022-07-19 19:52 [PATCH v3 RESEND 0/6] Add support for upcoming chips to k10temp and amd_nb Mario Limonciello
@ 2022-07-19 19:52 ` Mario Limonciello
2022-07-19 19:52 ` [PATCH v3 RESEND 2/6] x86/amd_nb: Add Family 19h model 70h-7Fh IDs Mario Limonciello
` (7 subsequent siblings)
8 siblings, 0 replies; 12+ messages in thread
From: Mario Limonciello @ 2022-07-19 19:52 UTC (permalink / raw)
To: Clemens Ladisch, Thomas Gleixner, Ingo Molnar, Borislav Petkov,
dave.hansen
Cc: linux-hwmon, Guenter Roeck, babu.moger, yazen.ghannam,
linux-kernel, x86, Mario Limonciello, Bjorn Helgaas
Add support for SMN communication on Family 17h Model A0h.
Signed-off-by: Mario Limonciello <mario.limonciello@amd.com>
Reviewed-by: Yazen Ghannam <yazen.ghannam@amd.com>
Acked-by: Bjorn Helgaas <bhelgaas@google.com> # pci_ids.h
---
arch/x86/kernel/amd_nb.c | 5 +++++
include/linux/pci_ids.h | 1 +
2 files changed, 6 insertions(+)
diff --git a/arch/x86/kernel/amd_nb.c b/arch/x86/kernel/amd_nb.c
index 190e0f7633755..60c7bd525237a 100644
--- a/arch/x86/kernel/amd_nb.c
+++ b/arch/x86/kernel/amd_nb.c
@@ -19,12 +19,14 @@
#define PCI_DEVICE_ID_AMD_17H_M10H_ROOT 0x15d0
#define PCI_DEVICE_ID_AMD_17H_M30H_ROOT 0x1480
#define PCI_DEVICE_ID_AMD_17H_M60H_ROOT 0x1630
+#define PCI_DEVICE_ID_AMD_17H_MA0H_ROOT 0x14b5
#define PCI_DEVICE_ID_AMD_19H_M10H_ROOT 0x14a4
#define PCI_DEVICE_ID_AMD_17H_DF_F4 0x1464
#define PCI_DEVICE_ID_AMD_17H_M10H_DF_F4 0x15ec
#define PCI_DEVICE_ID_AMD_17H_M30H_DF_F4 0x1494
#define PCI_DEVICE_ID_AMD_17H_M60H_DF_F4 0x144c
#define PCI_DEVICE_ID_AMD_17H_M70H_DF_F4 0x1444
+#define PCI_DEVICE_ID_AMD_17H_MA0H_DF_F4 0x1728
#define PCI_DEVICE_ID_AMD_19H_DF_F4 0x1654
#define PCI_DEVICE_ID_AMD_19H_M10H_DF_F4 0x14b1
#define PCI_DEVICE_ID_AMD_19H_M40H_ROOT 0x14b5
@@ -41,6 +43,7 @@ static const struct pci_device_id amd_root_ids[] = {
{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_17H_M10H_ROOT) },
{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_17H_M30H_ROOT) },
{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_17H_M60H_ROOT) },
+ { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_17H_MA0H_ROOT) },
{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_19H_M10H_ROOT) },
{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_19H_M40H_ROOT) },
{}
@@ -61,6 +64,7 @@ static const struct pci_device_id amd_nb_misc_ids[] = {
{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_17H_M10H_DF_F3) },
{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_17H_M30H_DF_F3) },
{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_17H_M60H_DF_F3) },
+ { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_17H_MA0H_DF_F3) },
{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_CNB17H_F3) },
{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_17H_M70H_DF_F3) },
{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_19H_DF_F3) },
@@ -81,6 +85,7 @@ static const struct pci_device_id amd_nb_link_ids[] = {
{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_17H_M30H_DF_F4) },
{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_17H_M60H_DF_F4) },
{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_17H_M70H_DF_F4) },
+ { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_17H_MA0H_DF_F4) },
{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_19H_DF_F4) },
{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_19H_M10H_DF_F4) },
{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_19H_M40H_DF_F4) },
diff --git a/include/linux/pci_ids.h b/include/linux/pci_ids.h
index 0178823ce8c20..ec1c226d13e60 100644
--- a/include/linux/pci_ids.h
+++ b/include/linux/pci_ids.h
@@ -556,6 +556,7 @@
#define PCI_DEVICE_ID_AMD_17H_M30H_DF_F3 0x1493
#define PCI_DEVICE_ID_AMD_17H_M60H_DF_F3 0x144b
#define PCI_DEVICE_ID_AMD_17H_M70H_DF_F3 0x1443
+#define PCI_DEVICE_ID_AMD_17H_MA0H_DF_F3 0x1727
#define PCI_DEVICE_ID_AMD_19H_DF_F3 0x1653
#define PCI_DEVICE_ID_AMD_19H_M10H_DF_F3 0x14b0
#define PCI_DEVICE_ID_AMD_19H_M40H_DF_F3 0x167c
--
2.25.1
^ permalink raw reply [flat|nested] 12+ messages in thread* [PATCH v3 RESEND 2/6] x86/amd_nb: Add Family 19h model 70h-7Fh IDs
2022-07-19 19:52 [PATCH v3 RESEND 0/6] Add support for upcoming chips to k10temp and amd_nb Mario Limonciello
2022-07-19 19:52 ` [PATCH v3 RESEND 1/6] x86/amd_nb: Add AMD Family 17h A0-AF IDs Mario Limonciello
@ 2022-07-19 19:52 ` Mario Limonciello
2022-07-19 19:52 ` [PATCH v3 RESEND 3/6] x86/amd_nb: Add Family 19h model 60h-6Fh IDs Mario Limonciello
` (6 subsequent siblings)
8 siblings, 0 replies; 12+ messages in thread
From: Mario Limonciello @ 2022-07-19 19:52 UTC (permalink / raw)
To: Clemens Ladisch, Thomas Gleixner, Ingo Molnar, Borislav Petkov,
dave.hansen
Cc: linux-hwmon, Guenter Roeck, babu.moger, yazen.ghannam,
linux-kernel, x86, Mario Limonciello
Add support for SMN communication on Family 19h Model 70h.
Signed-off-by: Mario Limonciello <mario.limonciello@amd.com>
Reviewed-by: Yazen Ghannam <yazen.ghannam@amd.com>
Acked-by: Guenter Roeck <linux@roeck-us.net>
---
arch/x86/kernel/amd_nb.c | 4 ++++
include/linux/pci_ids.h | 1 +
2 files changed, 5 insertions(+)
diff --git a/arch/x86/kernel/amd_nb.c b/arch/x86/kernel/amd_nb.c
index 60c7bd525237a..cb7a40378ed3c 100644
--- a/arch/x86/kernel/amd_nb.c
+++ b/arch/x86/kernel/amd_nb.c
@@ -21,6 +21,7 @@
#define PCI_DEVICE_ID_AMD_17H_M60H_ROOT 0x1630
#define PCI_DEVICE_ID_AMD_17H_MA0H_ROOT 0x14b5
#define PCI_DEVICE_ID_AMD_19H_M10H_ROOT 0x14a4
+#define PCI_DEVICE_ID_AMD_19H_M70H_ROOT 0x14e8
#define PCI_DEVICE_ID_AMD_17H_DF_F4 0x1464
#define PCI_DEVICE_ID_AMD_17H_M10H_DF_F4 0x15ec
#define PCI_DEVICE_ID_AMD_17H_M30H_DF_F4 0x1494
@@ -32,6 +33,7 @@
#define PCI_DEVICE_ID_AMD_19H_M40H_ROOT 0x14b5
#define PCI_DEVICE_ID_AMD_19H_M40H_DF_F4 0x167d
#define PCI_DEVICE_ID_AMD_19H_M50H_DF_F4 0x166e
+#define PCI_DEVICE_ID_AMD_19H_M70H_DF_F4 0x14f4
/* Protect the PCI config register pairs used for SMN. */
static DEFINE_MUTEX(smn_mutex);
@@ -46,6 +48,7 @@ static const struct pci_device_id amd_root_ids[] = {
{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_17H_MA0H_ROOT) },
{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_19H_M10H_ROOT) },
{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_19H_M40H_ROOT) },
+ { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_19H_M70H_ROOT) },
{}
};
@@ -71,6 +74,7 @@ static const struct pci_device_id amd_nb_misc_ids[] = {
{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_19H_M10H_DF_F3) },
{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_19H_M40H_DF_F3) },
{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_19H_M50H_DF_F3) },
+ { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_19H_M70H_DF_F3) },
{}
};
diff --git a/include/linux/pci_ids.h b/include/linux/pci_ids.h
index ec1c226d13e60..32a1f85ff0de1 100644
--- a/include/linux/pci_ids.h
+++ b/include/linux/pci_ids.h
@@ -561,6 +561,7 @@
#define PCI_DEVICE_ID_AMD_19H_M10H_DF_F3 0x14b0
#define PCI_DEVICE_ID_AMD_19H_M40H_DF_F3 0x167c
#define PCI_DEVICE_ID_AMD_19H_M50H_DF_F3 0x166d
+#define PCI_DEVICE_ID_AMD_19H_M70H_DF_F3 0x14f3
#define PCI_DEVICE_ID_AMD_CNB17H_F3 0x1703
#define PCI_DEVICE_ID_AMD_LANCE 0x2000
#define PCI_DEVICE_ID_AMD_LANCE_HOME 0x2001
--
2.25.1
^ permalink raw reply [flat|nested] 12+ messages in thread* [PATCH v3 RESEND 3/6] x86/amd_nb: Add Family 19h model 60h-6Fh IDs
2022-07-19 19:52 [PATCH v3 RESEND 0/6] Add support for upcoming chips to k10temp and amd_nb Mario Limonciello
2022-07-19 19:52 ` [PATCH v3 RESEND 1/6] x86/amd_nb: Add AMD Family 17h A0-AF IDs Mario Limonciello
2022-07-19 19:52 ` [PATCH v3 RESEND 2/6] x86/amd_nb: Add Family 19h model 70h-7Fh IDs Mario Limonciello
@ 2022-07-19 19:52 ` Mario Limonciello
2022-07-19 19:52 ` [PATCH v3 RESEND 4/6] hwmon: (k10temp): Add support for family 17h models A0h-AFh Mario Limonciello
` (5 subsequent siblings)
8 siblings, 0 replies; 12+ messages in thread
From: Mario Limonciello @ 2022-07-19 19:52 UTC (permalink / raw)
To: Clemens Ladisch, Thomas Gleixner, Ingo Molnar, Borislav Petkov,
dave.hansen
Cc: linux-hwmon, Guenter Roeck, babu.moger, yazen.ghannam,
linux-kernel, x86, Mario Limonciello
Add support for SMN communication on Family 19h Model 60h.
Signed-off-by: Mario Limonciello <mario.limonciello@amd.com>
Reviewed-by: Yazen Ghannam <yazen.ghannam@amd.com>
---
arch/x86/kernel/amd_nb.c | 4 ++++
include/linux/pci_ids.h | 1 +
2 files changed, 5 insertions(+)
diff --git a/arch/x86/kernel/amd_nb.c b/arch/x86/kernel/amd_nb.c
index cb7a40378ed3c..4266b64631a46 100644
--- a/arch/x86/kernel/amd_nb.c
+++ b/arch/x86/kernel/amd_nb.c
@@ -21,6 +21,7 @@
#define PCI_DEVICE_ID_AMD_17H_M60H_ROOT 0x1630
#define PCI_DEVICE_ID_AMD_17H_MA0H_ROOT 0x14b5
#define PCI_DEVICE_ID_AMD_19H_M10H_ROOT 0x14a4
+#define PCI_DEVICE_ID_AMD_19H_M60H_ROOT 0x14d8
#define PCI_DEVICE_ID_AMD_19H_M70H_ROOT 0x14e8
#define PCI_DEVICE_ID_AMD_17H_DF_F4 0x1464
#define PCI_DEVICE_ID_AMD_17H_M10H_DF_F4 0x15ec
@@ -33,6 +34,7 @@
#define PCI_DEVICE_ID_AMD_19H_M40H_ROOT 0x14b5
#define PCI_DEVICE_ID_AMD_19H_M40H_DF_F4 0x167d
#define PCI_DEVICE_ID_AMD_19H_M50H_DF_F4 0x166e
+#define PCI_DEVICE_ID_AMD_19H_M60H_DF_F4 0x14e4
#define PCI_DEVICE_ID_AMD_19H_M70H_DF_F4 0x14f4
/* Protect the PCI config register pairs used for SMN. */
@@ -48,6 +50,7 @@ static const struct pci_device_id amd_root_ids[] = {
{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_17H_MA0H_ROOT) },
{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_19H_M10H_ROOT) },
{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_19H_M40H_ROOT) },
+ { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_19H_M60H_ROOT) },
{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_19H_M70H_ROOT) },
{}
};
@@ -74,6 +77,7 @@ static const struct pci_device_id amd_nb_misc_ids[] = {
{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_19H_M10H_DF_F3) },
{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_19H_M40H_DF_F3) },
{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_19H_M50H_DF_F3) },
+ { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_19H_M60H_DF_F3) },
{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_19H_M70H_DF_F3) },
{}
};
diff --git a/include/linux/pci_ids.h b/include/linux/pci_ids.h
index 32a1f85ff0de1..7fa460ccf7fa1 100644
--- a/include/linux/pci_ids.h
+++ b/include/linux/pci_ids.h
@@ -561,6 +561,7 @@
#define PCI_DEVICE_ID_AMD_19H_M10H_DF_F3 0x14b0
#define PCI_DEVICE_ID_AMD_19H_M40H_DF_F3 0x167c
#define PCI_DEVICE_ID_AMD_19H_M50H_DF_F3 0x166d
+#define PCI_DEVICE_ID_AMD_19H_M60H_DF_F3 0x14e3
#define PCI_DEVICE_ID_AMD_19H_M70H_DF_F3 0x14f3
#define PCI_DEVICE_ID_AMD_CNB17H_F3 0x1703
#define PCI_DEVICE_ID_AMD_LANCE 0x2000
--
2.25.1
^ permalink raw reply [flat|nested] 12+ messages in thread* [PATCH v3 RESEND 4/6] hwmon: (k10temp): Add support for family 17h models A0h-AFh
2022-07-19 19:52 [PATCH v3 RESEND 0/6] Add support for upcoming chips to k10temp and amd_nb Mario Limonciello
` (2 preceding siblings ...)
2022-07-19 19:52 ` [PATCH v3 RESEND 3/6] x86/amd_nb: Add Family 19h model 60h-6Fh IDs Mario Limonciello
@ 2022-07-19 19:52 ` Mario Limonciello
2022-07-19 19:52 ` [PATCH v3 RESEND 5/6] hwmon: (k10temp): Add support for family 19h models 70h-7Fh Mario Limonciello
` (4 subsequent siblings)
8 siblings, 0 replies; 12+ messages in thread
From: Mario Limonciello @ 2022-07-19 19:52 UTC (permalink / raw)
To: Clemens Ladisch, Thomas Gleixner, Ingo Molnar, Borislav Petkov,
dave.hansen
Cc: linux-hwmon, Guenter Roeck, babu.moger, yazen.ghannam,
linux-kernel, x86, Mario Limonciello
Add the support for CCD offsets used on family 17h models A0h-AFh.
Signed-off-by: Mario Limonciello <mario.limonciello@amd.com>
Acked-by: Guenter Roeck <linux@roeck-us.net>
---
drivers/hwmon/k10temp.c | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/drivers/hwmon/k10temp.c b/drivers/hwmon/k10temp.c
index 4e239bd75b1da..5f831e74bc51b 100644
--- a/drivers/hwmon/k10temp.c
+++ b/drivers/hwmon/k10temp.c
@@ -428,6 +428,10 @@ static int k10temp_probe(struct pci_dev *pdev, const struct pci_device_id *id)
data->ccd_offset = 0x154;
k10temp_get_ccd_support(pdev, data, 8);
break;
+ case 0xa0 ... 0xaf:
+ data->ccd_offset = 0x300;
+ k10temp_get_ccd_support(pdev, data, 8);
+ break;
}
} else if (boot_cpu_data.x86 == 0x19) {
data->temp_adjust_mask = ZEN_CUR_TEMP_RANGE_SEL_MASK;
@@ -489,6 +493,7 @@ static const struct pci_device_id k10temp_id_table[] = {
{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_17H_M30H_DF_F3) },
{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_17H_M60H_DF_F3) },
{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_17H_M70H_DF_F3) },
+ { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_17H_MA0H_DF_F3) },
{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_19H_DF_F3) },
{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_19H_M10H_DF_F3) },
{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_19H_M40H_DF_F3) },
--
2.25.1
^ permalink raw reply [flat|nested] 12+ messages in thread* [PATCH v3 RESEND 5/6] hwmon: (k10temp): Add support for family 19h models 70h-7Fh
2022-07-19 19:52 [PATCH v3 RESEND 0/6] Add support for upcoming chips to k10temp and amd_nb Mario Limonciello
` (3 preceding siblings ...)
2022-07-19 19:52 ` [PATCH v3 RESEND 4/6] hwmon: (k10temp): Add support for family 17h models A0h-AFh Mario Limonciello
@ 2022-07-19 19:52 ` Mario Limonciello
2022-07-19 19:52 ` [PATCH v3 RESEND 6/6] hwmon: (k10temp): Add support for family 19h models 60h-6Fh Mario Limonciello
` (3 subsequent siblings)
8 siblings, 0 replies; 12+ messages in thread
From: Mario Limonciello @ 2022-07-19 19:52 UTC (permalink / raw)
To: Clemens Ladisch, Thomas Gleixner, Ingo Molnar, Borislav Petkov,
dave.hansen
Cc: linux-hwmon, Guenter Roeck, babu.moger, yazen.ghannam,
linux-kernel, x86, Mario Limonciello
Add the support for CCD offsets used on family 19h models 70h-7Fh.
Signed-off-by: Mario Limonciello <mario.limonciello@amd.com>
Acked-by: Guenter Roeck <linux@roeck-us.net>
---
drivers/hwmon/k10temp.c | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/drivers/hwmon/k10temp.c b/drivers/hwmon/k10temp.c
index 5f831e74bc51b..5f37e2e7833e7 100644
--- a/drivers/hwmon/k10temp.c
+++ b/drivers/hwmon/k10temp.c
@@ -449,6 +449,10 @@ static int k10temp_probe(struct pci_dev *pdev, const struct pci_device_id *id)
data->ccd_offset = 0x300;
k10temp_get_ccd_support(pdev, data, 8);
break;
+ case 0x70 ... 0x7f:
+ data->ccd_offset = 0x308;
+ k10temp_get_ccd_support(pdev, data, 8);
+ break;
case 0x10 ... 0x1f:
case 0xa0 ... 0xaf:
data->ccd_offset = 0x300;
@@ -498,6 +502,7 @@ static const struct pci_device_id k10temp_id_table[] = {
{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_19H_M10H_DF_F3) },
{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_19H_M40H_DF_F3) },
{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_19H_M50H_DF_F3) },
+ { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_19H_M70H_DF_F3) },
{ PCI_VDEVICE(HYGON, PCI_DEVICE_ID_AMD_17H_DF_F3) },
{}
};
--
2.25.1
^ permalink raw reply [flat|nested] 12+ messages in thread* [PATCH v3 RESEND 6/6] hwmon: (k10temp): Add support for family 19h models 60h-6Fh
2022-07-19 19:52 [PATCH v3 RESEND 0/6] Add support for upcoming chips to k10temp and amd_nb Mario Limonciello
` (4 preceding siblings ...)
2022-07-19 19:52 ` [PATCH v3 RESEND 5/6] hwmon: (k10temp): Add support for family 19h models 70h-7Fh Mario Limonciello
@ 2022-07-19 19:52 ` Mario Limonciello
2022-07-20 14:45 ` [PATCH v3 RESEND 0/6] Add support for upcoming chips to k10temp and amd_nb Borislav Petkov
` (2 subsequent siblings)
8 siblings, 0 replies; 12+ messages in thread
From: Mario Limonciello @ 2022-07-19 19:52 UTC (permalink / raw)
To: Clemens Ladisch, Thomas Gleixner, Ingo Molnar, Borislav Petkov,
dave.hansen
Cc: linux-hwmon, Guenter Roeck, babu.moger, yazen.ghannam,
linux-kernel, x86, Mario Limonciello
Add the support for CCD offsets used on family 19h models 60h-6Fh.
Signed-off-by: Mario Limonciello <mario.limonciello@amd.com>
Acked-by: Guenter Roeck <linux@roeck-us.net>
---
drivers/hwmon/k10temp.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/hwmon/k10temp.c b/drivers/hwmon/k10temp.c
index 5f37e2e7833e7..5a9d47a229e40 100644
--- a/drivers/hwmon/k10temp.c
+++ b/drivers/hwmon/k10temp.c
@@ -449,6 +449,7 @@ static int k10temp_probe(struct pci_dev *pdev, const struct pci_device_id *id)
data->ccd_offset = 0x300;
k10temp_get_ccd_support(pdev, data, 8);
break;
+ case 0x60 ... 0x6f:
case 0x70 ... 0x7f:
data->ccd_offset = 0x308;
k10temp_get_ccd_support(pdev, data, 8);
@@ -502,6 +503,7 @@ static const struct pci_device_id k10temp_id_table[] = {
{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_19H_M10H_DF_F3) },
{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_19H_M40H_DF_F3) },
{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_19H_M50H_DF_F3) },
+ { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_19H_M60H_DF_F3) },
{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_19H_M70H_DF_F3) },
{ PCI_VDEVICE(HYGON, PCI_DEVICE_ID_AMD_17H_DF_F3) },
{}
--
2.25.1
^ permalink raw reply [flat|nested] 12+ messages in thread* Re: [PATCH v3 RESEND 0/6] Add support for upcoming chips to k10temp and amd_nb
2022-07-19 19:52 [PATCH v3 RESEND 0/6] Add support for upcoming chips to k10temp and amd_nb Mario Limonciello
` (5 preceding siblings ...)
2022-07-19 19:52 ` [PATCH v3 RESEND 6/6] hwmon: (k10temp): Add support for family 19h models 60h-6Fh Mario Limonciello
@ 2022-07-20 14:45 ` Borislav Petkov
2022-07-20 15:22 ` Guenter Roeck
2022-07-21 9:19 ` [tip: x86/misc] hwmon: (k10temp): Add support for new family 17h and 19h models tip-bot2 for Mario Limonciello
2022-07-21 9:19 ` [tip: x86/misc] x86/amd_nb: Add AMD PCI IDs for SMN communication tip-bot2 for Mario Limonciello
8 siblings, 1 reply; 12+ messages in thread
From: Borislav Petkov @ 2022-07-20 14:45 UTC (permalink / raw)
To: Mario Limonciello
Cc: Clemens Ladisch, Thomas Gleixner, Ingo Molnar, dave.hansen,
linux-hwmon, Guenter Roeck, babu.moger, yazen.ghannam,
linux-kernel, x86
On Tue, Jul 19, 2022 at 02:52:50PM -0500, Mario Limonciello wrote:
> This series started as what looked like a correction to previous
> commits, but I missed that the previous commits were for a different
> family with the same chip models. So while fixing up the series I also
> noticed that a few upcoming chips have new PCIe IDs and CCD offsets not
> yet supported, so add them to amd_nb/k10temp.
>
> v2->v3
> * Pick up tags
> * Group "ROOT" PCI IDs with others in patches 2 and 3.
> v1->v2:
> * Correct commit messages
> * Add more missing chips and offsets
> * since so much changed, do not include Bjorn's Ack.
>
> V3 original submission:
> * https://lore.kernel.org/lkml/20220613192956.4911-1-mario.limonciello@amd.com/#t
>
> Mario Limonciello (6):
> x86/amd_nb: Add AMD Family 17h A0-AF IDs
> x86/amd_nb: Add Family 19h model 70h-7Fh IDs
> x86/amd_nb: Add Family 19h model 60h-6Fh IDs
> hwmon: (k10temp): Add support for family 17h models A0h-AFh
> hwmon: (k10temp): Add support for family 19h models 70h-7Fh
> hwmon: (k10temp): Add support for family 19h models 60h-6Fh
Is there any particular reason why those are split into such small
pieces?
I'd expect one patch adding all PCI IDs and a second patch doing the
k10temp changes.
If no particular reason, I'll compact them all 6 into 2.
Thx.
--
Regards/Gruss,
Boris.
https://people.kernel.org/tglx/notes-about-netiquette
^ permalink raw reply [flat|nested] 12+ messages in thread* Re: [PATCH v3 RESEND 0/6] Add support for upcoming chips to k10temp and amd_nb
2022-07-20 14:45 ` [PATCH v3 RESEND 0/6] Add support for upcoming chips to k10temp and amd_nb Borislav Petkov
@ 2022-07-20 15:22 ` Guenter Roeck
2022-07-20 15:30 ` Limonciello, Mario
0 siblings, 1 reply; 12+ messages in thread
From: Guenter Roeck @ 2022-07-20 15:22 UTC (permalink / raw)
To: Borislav Petkov, Mario Limonciello
Cc: Clemens Ladisch, Thomas Gleixner, Ingo Molnar, dave.hansen,
linux-hwmon, babu.moger, yazen.ghannam, linux-kernel, x86
On 7/20/22 07:45, Borislav Petkov wrote:
> On Tue, Jul 19, 2022 at 02:52:50PM -0500, Mario Limonciello wrote:
>> This series started as what looked like a correction to previous
>> commits, but I missed that the previous commits were for a different
>> family with the same chip models. So while fixing up the series I also
>> noticed that a few upcoming chips have new PCIe IDs and CCD offsets not
>> yet supported, so add them to amd_nb/k10temp.
>>
>> v2->v3
>> * Pick up tags
>> * Group "ROOT" PCI IDs with others in patches 2 and 3.
>> v1->v2:
>> * Correct commit messages
>> * Add more missing chips and offsets
>> * since so much changed, do not include Bjorn's Ack.
>>
>> V3 original submission:
>> * https://lore.kernel.org/lkml/20220613192956.4911-1-mario.limonciello@amd.com/#t
>>
>> Mario Limonciello (6):
>> x86/amd_nb: Add AMD Family 17h A0-AF IDs
>> x86/amd_nb: Add Family 19h model 70h-7Fh IDs
>> x86/amd_nb: Add Family 19h model 60h-6Fh IDs
>> hwmon: (k10temp): Add support for family 17h models A0h-AFh
>> hwmon: (k10temp): Add support for family 19h models 70h-7Fh
>> hwmon: (k10temp): Add support for family 19h models 60h-6Fh
>
> Is there any particular reason why those are split into such small
> pieces?
>
> I'd expect one patch adding all PCI IDs and a second patch doing the
> k10temp changes.
>
> If no particular reason, I'll compact them all 6 into 2.
>
Ok with me.
Guenter
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH v3 RESEND 0/6] Add support for upcoming chips to k10temp and amd_nb
2022-07-20 15:22 ` Guenter Roeck
@ 2022-07-20 15:30 ` Limonciello, Mario
0 siblings, 0 replies; 12+ messages in thread
From: Limonciello, Mario @ 2022-07-20 15:30 UTC (permalink / raw)
To: Guenter Roeck, Borislav Petkov
Cc: Clemens Ladisch, Thomas Gleixner, Ingo Molnar, dave.hansen,
linux-hwmon, babu.moger, yazen.ghannam, linux-kernel, x86
On 7/20/2022 10:22, Guenter Roeck wrote:
> On 7/20/22 07:45, Borislav Petkov wrote:
>> On Tue, Jul 19, 2022 at 02:52:50PM -0500, Mario Limonciello wrote:
>>> This series started as what looked like a correction to previous
>>> commits, but I missed that the previous commits were for a different
>>> family with the same chip models. So while fixing up the series I also
>>> noticed that a few upcoming chips have new PCIe IDs and CCD offsets not
>>> yet supported, so add them to amd_nb/k10temp.
>>>
>>> v2->v3
>>> * Pick up tags
>>> * Group "ROOT" PCI IDs with others in patches 2 and 3.
>>> v1->v2:
>>> * Correct commit messages
>>> * Add more missing chips and offsets
>>> * since so much changed, do not include Bjorn's Ack.
>>>
>>> V3 original submission:
>>> *
>>> https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Flore.kernel.org%2Flkml%2F20220613192956.4911-1-mario.limonciello%40amd.com%2F%23t&data=05%7C01%7Cmario.limonciello%40amd.com%7Cccd318a2336a4fff464e08da6a63adf5%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637939273635072576%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C3000%7C%7C%7C&sdata=WHsUYbBtu0ka4S2jiji%2BKaFycbTAHz%2B1RoANXo4maf0%3D&reserved=0
>>>
>>>
>>> Mario Limonciello (6):
>>> x86/amd_nb: Add AMD Family 17h A0-AF IDs
>>> x86/amd_nb: Add Family 19h model 70h-7Fh IDs
>>> x86/amd_nb: Add Family 19h model 60h-6Fh IDs
>>> hwmon: (k10temp): Add support for family 17h models A0h-AFh
>>> hwmon: (k10temp): Add support for family 19h models 70h-7Fh
>>> hwmon: (k10temp): Add support for family 19h models 60h-6Fh
>>
>> Is there any particular reason why those are split into such small
>> pieces?
>>
>> I'd expect one patch adding all PCI IDs and a second patch doing the
>> k10temp changes.
>>
>> If no particular reason, I'll compact them all 6 into 2.
>>
> Ok with me.
>
It was mostly for review purpose so that other AMD guys could comment if
I fumbled the DID or offsets for a product or if someone wanted to test
it independently on a particular product but didn't have the others to test.
At this point that's fine with me too to combine them; thanks.
^ permalink raw reply [flat|nested] 12+ messages in thread
* [tip: x86/misc] hwmon: (k10temp): Add support for new family 17h and 19h models
2022-07-19 19:52 [PATCH v3 RESEND 0/6] Add support for upcoming chips to k10temp and amd_nb Mario Limonciello
` (6 preceding siblings ...)
2022-07-20 14:45 ` [PATCH v3 RESEND 0/6] Add support for upcoming chips to k10temp and amd_nb Borislav Petkov
@ 2022-07-21 9:19 ` tip-bot2 for Mario Limonciello
2022-07-21 9:19 ` [tip: x86/misc] x86/amd_nb: Add AMD PCI IDs for SMN communication tip-bot2 for Mario Limonciello
8 siblings, 0 replies; 12+ messages in thread
From: tip-bot2 for Mario Limonciello @ 2022-07-21 9:19 UTC (permalink / raw)
To: linux-tip-commits
Cc: Mario Limonciello, Borislav Petkov, Guenter Roeck, x86, linux-kernel
The following commit has been merged into the x86/misc branch of tip:
Commit-ID: d906fa730827456711ce29c1f2994a0ccaff49dc
Gitweb: https://git.kernel.org/tip/d906fa730827456711ce29c1f2994a0ccaff49dc
Author: Mario Limonciello <mario.limonciello@amd.com>
AuthorDate: Tue, 19 Jul 2022 14:52:54 -05:00
Committer: Borislav Petkov <bp@suse.de>
CommitterDate: Wed, 20 Jul 2022 17:39:11 +02:00
hwmon: (k10temp): Add support for new family 17h and 19h models
Add the support for CCD offsets used on family 17h models A0h-AFh,
and family 19h models 60h-7Fh.
[ bp: Merge into a single patch. ]
Signed-off-by: Mario Limonciello <mario.limonciello@amd.com>
Signed-off-by: Borislav Petkov <bp@suse.de>
Acked-by: Guenter Roeck <linux@roeck-us.net>
Link: https://lore.kernel.org/r/20220719195256.1516-1-mario.limonciello@amd.com
---
drivers/hwmon/k10temp.c | 12 ++++++++++++
1 file changed, 12 insertions(+)
diff --git a/drivers/hwmon/k10temp.c b/drivers/hwmon/k10temp.c
index 4e239bd..5a9d47a 100644
--- a/drivers/hwmon/k10temp.c
+++ b/drivers/hwmon/k10temp.c
@@ -428,6 +428,10 @@ static int k10temp_probe(struct pci_dev *pdev, const struct pci_device_id *id)
data->ccd_offset = 0x154;
k10temp_get_ccd_support(pdev, data, 8);
break;
+ case 0xa0 ... 0xaf:
+ data->ccd_offset = 0x300;
+ k10temp_get_ccd_support(pdev, data, 8);
+ break;
}
} else if (boot_cpu_data.x86 == 0x19) {
data->temp_adjust_mask = ZEN_CUR_TEMP_RANGE_SEL_MASK;
@@ -445,6 +449,11 @@ static int k10temp_probe(struct pci_dev *pdev, const struct pci_device_id *id)
data->ccd_offset = 0x300;
k10temp_get_ccd_support(pdev, data, 8);
break;
+ case 0x60 ... 0x6f:
+ case 0x70 ... 0x7f:
+ data->ccd_offset = 0x308;
+ k10temp_get_ccd_support(pdev, data, 8);
+ break;
case 0x10 ... 0x1f:
case 0xa0 ... 0xaf:
data->ccd_offset = 0x300;
@@ -489,10 +498,13 @@ static const struct pci_device_id k10temp_id_table[] = {
{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_17H_M30H_DF_F3) },
{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_17H_M60H_DF_F3) },
{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_17H_M70H_DF_F3) },
+ { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_17H_MA0H_DF_F3) },
{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_19H_DF_F3) },
{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_19H_M10H_DF_F3) },
{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_19H_M40H_DF_F3) },
{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_19H_M50H_DF_F3) },
+ { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_19H_M60H_DF_F3) },
+ { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_19H_M70H_DF_F3) },
{ PCI_VDEVICE(HYGON, PCI_DEVICE_ID_AMD_17H_DF_F3) },
{}
};
^ permalink raw reply [flat|nested] 12+ messages in thread* [tip: x86/misc] x86/amd_nb: Add AMD PCI IDs for SMN communication
2022-07-19 19:52 [PATCH v3 RESEND 0/6] Add support for upcoming chips to k10temp and amd_nb Mario Limonciello
` (7 preceding siblings ...)
2022-07-21 9:19 ` [tip: x86/misc] hwmon: (k10temp): Add support for new family 17h and 19h models tip-bot2 for Mario Limonciello
@ 2022-07-21 9:19 ` tip-bot2 for Mario Limonciello
8 siblings, 0 replies; 12+ messages in thread
From: tip-bot2 for Mario Limonciello @ 2022-07-21 9:19 UTC (permalink / raw)
To: linux-tip-commits
Cc: Mario Limonciello, Borislav Petkov, Yazen Ghannam, Bjorn Helgaas,
Guenter Roeck, x86, linux-kernel
The following commit has been merged into the x86/misc branch of tip:
Commit-ID: f8faf3496633b302a6591fda599540a0b53a35bb
Gitweb: https://git.kernel.org/tip/f8faf3496633b302a6591fda599540a0b53a35bb
Author: Mario Limonciello <mario.limonciello@amd.com>
AuthorDate: Tue, 19 Jul 2022 14:52:51 -05:00
Committer: Borislav Petkov <bp@suse.de>
CommitterDate: Wed, 20 Jul 2022 17:35:40 +02:00
x86/amd_nb: Add AMD PCI IDs for SMN communication
Add support for SMN communication on family 17h model A0h and family 19h
models 60h-70h.
[ bp: Merge into a single patch. ]
Signed-off-by: Mario Limonciello <mario.limonciello@amd.com>
Signed-off-by: Borislav Petkov <bp@suse.de>
Reviewed-by: Yazen Ghannam <yazen.ghannam@amd.com>
Acked-by: Bjorn Helgaas <bhelgaas@google.com> # pci_ids.h
Acked-by: Guenter Roeck <linux@roeck-us.net>
Link: https://lore.kernel.org/r/20220719195256.1516-1-mario.limonciello@amd.com
---
arch/x86/kernel/amd_nb.c | 13 +++++++++++++
include/linux/pci_ids.h | 3 +++
2 files changed, 16 insertions(+)
diff --git a/arch/x86/kernel/amd_nb.c b/arch/x86/kernel/amd_nb.c
index 190e0f7..4266b64 100644
--- a/arch/x86/kernel/amd_nb.c
+++ b/arch/x86/kernel/amd_nb.c
@@ -19,17 +19,23 @@
#define PCI_DEVICE_ID_AMD_17H_M10H_ROOT 0x15d0
#define PCI_DEVICE_ID_AMD_17H_M30H_ROOT 0x1480
#define PCI_DEVICE_ID_AMD_17H_M60H_ROOT 0x1630
+#define PCI_DEVICE_ID_AMD_17H_MA0H_ROOT 0x14b5
#define PCI_DEVICE_ID_AMD_19H_M10H_ROOT 0x14a4
+#define PCI_DEVICE_ID_AMD_19H_M60H_ROOT 0x14d8
+#define PCI_DEVICE_ID_AMD_19H_M70H_ROOT 0x14e8
#define PCI_DEVICE_ID_AMD_17H_DF_F4 0x1464
#define PCI_DEVICE_ID_AMD_17H_M10H_DF_F4 0x15ec
#define PCI_DEVICE_ID_AMD_17H_M30H_DF_F4 0x1494
#define PCI_DEVICE_ID_AMD_17H_M60H_DF_F4 0x144c
#define PCI_DEVICE_ID_AMD_17H_M70H_DF_F4 0x1444
+#define PCI_DEVICE_ID_AMD_17H_MA0H_DF_F4 0x1728
#define PCI_DEVICE_ID_AMD_19H_DF_F4 0x1654
#define PCI_DEVICE_ID_AMD_19H_M10H_DF_F4 0x14b1
#define PCI_DEVICE_ID_AMD_19H_M40H_ROOT 0x14b5
#define PCI_DEVICE_ID_AMD_19H_M40H_DF_F4 0x167d
#define PCI_DEVICE_ID_AMD_19H_M50H_DF_F4 0x166e
+#define PCI_DEVICE_ID_AMD_19H_M60H_DF_F4 0x14e4
+#define PCI_DEVICE_ID_AMD_19H_M70H_DF_F4 0x14f4
/* Protect the PCI config register pairs used for SMN. */
static DEFINE_MUTEX(smn_mutex);
@@ -41,8 +47,11 @@ static const struct pci_device_id amd_root_ids[] = {
{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_17H_M10H_ROOT) },
{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_17H_M30H_ROOT) },
{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_17H_M60H_ROOT) },
+ { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_17H_MA0H_ROOT) },
{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_19H_M10H_ROOT) },
{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_19H_M40H_ROOT) },
+ { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_19H_M60H_ROOT) },
+ { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_19H_M70H_ROOT) },
{}
};
@@ -61,12 +70,15 @@ static const struct pci_device_id amd_nb_misc_ids[] = {
{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_17H_M10H_DF_F3) },
{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_17H_M30H_DF_F3) },
{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_17H_M60H_DF_F3) },
+ { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_17H_MA0H_DF_F3) },
{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_CNB17H_F3) },
{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_17H_M70H_DF_F3) },
{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_19H_DF_F3) },
{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_19H_M10H_DF_F3) },
{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_19H_M40H_DF_F3) },
{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_19H_M50H_DF_F3) },
+ { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_19H_M60H_DF_F3) },
+ { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_19H_M70H_DF_F3) },
{}
};
@@ -81,6 +93,7 @@ static const struct pci_device_id amd_nb_link_ids[] = {
{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_17H_M30H_DF_F4) },
{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_17H_M60H_DF_F4) },
{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_17H_M70H_DF_F4) },
+ { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_17H_MA0H_DF_F4) },
{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_19H_DF_F4) },
{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_19H_M10H_DF_F4) },
{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_19H_M40H_DF_F4) },
diff --git a/include/linux/pci_ids.h b/include/linux/pci_ids.h
index 0178823..7fa460c 100644
--- a/include/linux/pci_ids.h
+++ b/include/linux/pci_ids.h
@@ -556,10 +556,13 @@
#define PCI_DEVICE_ID_AMD_17H_M30H_DF_F3 0x1493
#define PCI_DEVICE_ID_AMD_17H_M60H_DF_F3 0x144b
#define PCI_DEVICE_ID_AMD_17H_M70H_DF_F3 0x1443
+#define PCI_DEVICE_ID_AMD_17H_MA0H_DF_F3 0x1727
#define PCI_DEVICE_ID_AMD_19H_DF_F3 0x1653
#define PCI_DEVICE_ID_AMD_19H_M10H_DF_F3 0x14b0
#define PCI_DEVICE_ID_AMD_19H_M40H_DF_F3 0x167c
#define PCI_DEVICE_ID_AMD_19H_M50H_DF_F3 0x166d
+#define PCI_DEVICE_ID_AMD_19H_M60H_DF_F3 0x14e3
+#define PCI_DEVICE_ID_AMD_19H_M70H_DF_F3 0x14f3
#define PCI_DEVICE_ID_AMD_CNB17H_F3 0x1703
#define PCI_DEVICE_ID_AMD_LANCE 0x2000
#define PCI_DEVICE_ID_AMD_LANCE_HOME 0x2001
^ permalink raw reply [flat|nested] 12+ messages in thread