[PATCH v2 3/3] arm64: dts: socfpga: agilex72: add clock manager support

[evon.chiam@altera.com]

From: "Chiam, Evon" <evon.chiam@altera.com>

Add the Agilex72 clock manager node and input reference clocks, and
wire the UART clocks through the clock manager instead of a fixed
clock. Set the SoCDK board-specific input clock frequencies.

Signed-off-by: Chiam, Evon <evon.chiam@altera.com>
---
Changes in v2:
- Subject: use the "arm64: dts: socfpga:" prefix to match the directory.
- Keep the device tree in dts/intel with the existing "intel," compatible
  strings.
- Pass the four external reference clocks to the clock manager node via
  clocks and clock-names.
- Dropped the unused sdm_xspi_clk fixed clock.

 .../boot/dts/intel/socfpga_agilex72.dtsi      | 44 +++++++++++++++++--
 .../boot/dts/intel/socfpga_agilex72_socdk.dts | 12 +++++
 2 files changed, 52 insertions(+), 4 deletions(-)

diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex72.dtsi b/arch/arm64/boot/dts/intel/socfpga_agilex72.dtsi
index c29c2afcaab7..e1553791c472 100644
--- a/arch/arm64/boot/dts/intel/socfpga_agilex72.dtsi
+++ b/arch/arm64/boot/dts/intel/socfpga_agilex72.dtsi
@@ -5,6 +5,7 @@
 /dts-v1/;
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 #include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/clock/altr,agilex72-clkmgr.h>
 
 / {
 	compatible = "intel,socfpga-agilex72";
@@ -64,11 +65,32 @@ cpu3: cpu@300 {
 		};
 	};
 
+	/* Clock tree 4 main sources */
 	clocks {
-		uart_clk: uart-clk {
+		cb_intosc_div2_clk: cb-intosc-div2-clk {
+			#clock-cells = <0>;
 			compatible = "fixed-clock";
+			clock-frequency = <0>;
+		};
+
+		cb_intosc_div10_clk: cb-intosc-div10-clk {
 			#clock-cells = <0>;
-			clock-frequency = <125000000>;
+			compatible = "fixed-factor-clock";
+			clocks = <&cb_intosc_div2_clk>;
+			clock-mult = <1>;
+			clock-div = <5>;
+		};
+
+		f2s_free_clk: f2s-free-clk {
+			#clock-cells = <0>;
+			compatible = "fixed-clock";
+			clock-frequency = <0>;
+		};
+
+		osc1: osc1 {
+			#clock-cells = <0>;
+			compatible = "fixed-clock";
+			clock-frequency = <0>;
 		};
 	};
 
@@ -133,13 +155,27 @@ ocram: sram@0 {
 			#size-cells = <1>;
 		};
 
+		clkmgr: clock-controller@915c000 {
+			compatible = "altr,agilex72-clkmgr";
+			reg = <0x915c000 0x1000>,
+			      <0x915e000 0x1000>,
+			      <0x915f000 0x1000>,
+			      <0x9160000 0x1000>;
+			reg-names = "clkmgr", "gppll0", "gppll1", "gppll2";
+			clocks = <&osc1>, <&cb_intosc_div2_clk>,
+				 <&cb_intosc_div10_clk>, <&f2s_free_clk>;
+			clock-names = "osc1", "cb-intosc-div2-clk",
+				      "cb-intosc-div10-clk", "f2s-free-clk";
+			#clock-cells = <1>;
+		};
+
 		uart0: serial@9038000 {
 			compatible = "snps,dw-apb-uart";
 			reg = <0x9038000 0x100>;
 			interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
 			reg-shift = <2>;
 			reg-io-width = <4>;
-			clocks = <&uart_clk>;
+			clocks = <&clkmgr AGILEX72_LSP_SP_CLK>;
 			status = "disabled";
 		};
 
@@ -149,7 +185,7 @@ uart1: serial@9039000 {
 			interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
 			reg-shift = <2>;
 			reg-io-width = <4>;
-			clocks = <&uart_clk>;
+			clocks = <&clkmgr AGILEX72_LSP_SP_CLK>;
 			status = "disabled";
 		};
 	};
diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex72_socdk.dts b/arch/arm64/boot/dts/intel/socfpga_agilex72_socdk.dts
index 998f19f492b3..dfac1f18d16d 100644
--- a/arch/arm64/boot/dts/intel/socfpga_agilex72_socdk.dts
+++ b/arch/arm64/boot/dts/intel/socfpga_agilex72_socdk.dts
@@ -22,6 +22,18 @@ memory@80000000 {
 	};
 };
 
+&cb_intosc_div2_clk {
+	clock-frequency = <500000000>;
+};
+
+&osc1 {
+	clock-frequency = <100000000>;
+};
+
+&f2s_free_clk {
+	clock-frequency = <100000000>;
+};
+
 &uart0 {
 	status = "okay";
 };
-- 
2.43.7