Re: [PATCH msm-next] drm/msm/a8xx: report the GMEM size of the active slices

[Akhil P Oommen <akhilpo@oss.qualcomm.com>]

On 9/30/2026 4:47 PM, Rahul Pon wrote:
> A8xx GPUs split GMEM evenly between their slices, and parts can have
> slices fused off: a8xx_gpu_get_slice_info() reads the active slice mask
> and folds the slice count into the chip ID. The GMEM size reported to
> userspace (MSM_PARAM_GMEM_SIZE) is still the catalog value for all
> slices.
> 
> On an HP OmniBook 5 (Snapdragon X2 Elite, Mahua), the Adreno X2-85 runs
> 3 of 4 slices (chip ID 0x44070031) and the kernel reports 21 MB of GMEM.

This commit text is incorrect, but the fix is valid. Please use this series
for Mahua GPU support:

https://lore.kernel.org/lkml/20260925-mahua-gpu-v1-0-0fa0bfd8d315@oss.qualcomm.com/

> Mesa sizes its tiles and places its CCU caches at the top of that range,
> past the end of the GMEM that exists, and GPU-rendered output is visibly
> corrupted: noise bands and block garbage, across the whole desktop with
> GNOME Shell. Rendering without GMEM (FD_MESA_DEBUG=sysmem) is clean;
> disabling UBWC, LRZ or compressed scanout is not.
> 
> Qualcomm's downstream driver reports GMEM for the active slices on this
> GPU: gen8_get_gmem_size() in KGSL returns
> gmem_size / GEN8_1_0_NUM_PHYSICAL_SLICES * active slices, 15.75 MB here.
> Do the same when reading the slice mask. The GMEM protection and UCHE
> setup still cover the full range, as in KGSL.
> 
> Fixes: 288a93200892 ("drm/msm/adreno: Introduce A8x GPU Support")
> Assisted-by: LLM
> Signed-off-by: Rahul Pon <theflyingrahul@gmail.com>
> ---
>  drivers/gpu/drm/msm/adreno/a8xx_gpu.c   | 4 ++++
>  drivers/gpu/drm/msm/adreno/adreno_gpu.c | 3 ++-
>  drivers/gpu/drm/msm/adreno/adreno_gpu.h | 2 ++
>  3 files changed, 8 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/msm/adreno/a8xx_gpu.c b/drivers/gpu/drm/msm/adreno/a8xx_gpu.c
> index add93c1fa039..9b95d9b3826a 100644
> --- a/drivers/gpu/drm/msm/adreno/a8xx_gpu.c
> +++ b/drivers/gpu/drm/msm/adreno/a8xx_gpu.c
> @@ -112,6 +112,10 @@ void a8xx_gpu_get_slice_info(struct msm_gpu *gpu)
>  	/* Chip ID depends on the number of slices available. So update it */
>  	adreno_gpu->chip_id |= FIELD_PREP(GENMASK(7, 4), hweight32(slice_mask));
>  
> +	/* GMEM is split evenly between slices: report the active share */
> +	adreno_gpu->gmem = adreno_gpu->info->gmem / info->max_slices *
> +			   hweight32(slice_mask);

Please add '()' to improve readability. And it would be easier on eyes, if you
don't break the line.

Also, reword the commit text to exclude mentioning Mahua. We don't a partial slice SKU
commercialized yet.

With above updates:
Reviewed-by: Akhil P Oommen <akhilpo@oss.qualcomm.com>

Thanks,
-Akhil.

> +
>  	/* Update the gpu-name to reflect the slice config: */
>  	const char *name = devm_kasprintf(dev, GFP_KERNEL,
>  			"%"ADRENO_CHIPID_FMT,
> diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.c b/drivers/gpu/drm/msm/adreno/adreno_gpu.c
> index 5832dc25d6bf..dadfe4c69438 100644
> --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.c
> +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.c
> @@ -379,7 +379,7 @@ int adreno_get_param(struct msm_gpu *gpu, struct msm_context *ctx,
>  		*value = adreno_gpu->info->revn;
>  		return 0;
>  	case MSM_PARAM_GMEM_SIZE:
> -		*value = adreno_gpu->info->gmem;
> +		*value = adreno_gpu->gmem;
>  		return 0;
>  	case MSM_PARAM_GMEM_BASE:
>  		if (adreno_gpu->info->family >= ADRENO_6XX_GEN3)
> @@ -1205,6 +1205,7 @@ int adreno_gpu_init(struct drm_device *drm, struct platform_device *pdev,
>  	adreno_gpu->funcs = funcs;
>  	adreno_gpu->info = config->info;
>  	adreno_gpu->chip_id = config->chip_id;
> +	adreno_gpu->gmem = config->info->gmem;
>  
>  	gpu->allow_relocs = config->info->family < ADRENO_6XX_GEN1;
>  	gpu->pdev = pdev;
> diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.h b/drivers/gpu/drm/msm/adreno/adreno_gpu.h
> index 114a40f79ef3..8e6a88103610 100644
> --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.h
> +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.h
> @@ -204,6 +204,8 @@ struct adreno_gpu {
>  	struct msm_gpu base;
>  	const struct adreno_info *info;
>  	uint32_t chip_id;
> +	/* GMEM size available to userspace, see a8xx_gpu_get_slice_info(): */
> +	uint32_t gmem;
>  	uint16_t speedbin;
>  	const struct adreno_gpu_funcs *funcs;
>  
> 
> base-commit: d33622598496c8994c35ba0a8a913de064dfc1a4