From: Heiko Schocher <hs@nabladev.com>
To: Xu Yilun <yilun.xu@linux.intel.com>
Cc: linux-kernel@vger.kernel.org, linux-fpga@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
Michal Simek <michal.simek@amd.com>,
Moritz Fischer <mdf@kernel.org>, Tom Rix <trix@redhat.com>,
Xu Yilun <yilun.xu@intel.com>
Subject: Re: [PATCH v2] driver: fpga: xilinx-selectmap: add csi and rdwr support
Date: Thu, 23 Jul 2026 06:47:22 +0200 [thread overview]
Message-ID: <d7844d5d-1ce5-2b31-64ca-4ff2798ce221@nabladev.com> (raw)
In-Reply-To: <amGbvtMWHXjpE35D@yilunxu-OptiPlex-7050>
Hello Yilun,
On 23.07.26 06:42, Xu Yilun wrote:
> On Tue, Jul 21, 2026 at 01:42:52PM +0200, Heiko Schocher wrote:
>> Add csi_b and rdwr pin support for the xilinx,selectmap driver.
>>
>> In current driver the pins are configured from DTS and set to
>> GPIOD_OUT_HIGH. This works in case you have one FPGA.
>>
>> Extend this to really implement csi_b and rdwr pin function in
>> driver, so it works with more than one FPGA.
>
> Please help specify in changelog: what do csi_b, rdwr pins do? Why they
> now work with one FPGA but not with 2 FPGAs? How do you select which FPGA
> to reprogram? thanks.
I will try to add this. You find some hint here:
Documentation/devicetree/bindings/fpga/xlnx,fpga-selectmap.yaml
Thanks!
bye,
Heiko
>
> Thanks,
> Yilun
>
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prev parent reply other threads:[~2026-07-23 4:47 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-07-21 11:42 Heiko Schocher
2026-07-22 6:55 ` Michal Simek
2026-07-22 14:45 ` Heiko Schocher
2026-07-23 5:44 ` Michal Simek
2026-07-23 5:57 ` Heiko Schocher
2026-07-23 4:42 ` Xu Yilun
2026-07-23 4:47 ` Heiko Schocher [this message]
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