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From: Alexandre Torgue <alexandre.torgue@st.com>
To: Thomas Gleixner <tglx@linutronix.de>
Cc: Maxime Coquelin <mcoquelin.stm32@gmail.com>,
	Jason Cooper <jason@lakedaemon.net>,
	Marc Zyngier <marc.zyngier@arm.com>,
	Linus Walleij <linus.walleij@linaro.org>,
	Mark Rutland <mark.rutland@arm.com>,
	Rob Herring <robh+dt@kernel.org>, <linux-gpio@vger.kernel.org>,
	<arnd@arndb.de>, <linux-arm-kernel@lists.infradead.org>,
	<linux-kernel@vger.kernel.org>, <devicetree@vger.kernel.org>,
	Daniel Thompson <daniel.thompson@linaro.org>,
	<bruherrera@gmail.com>, <lee.jones@linaro.org>
Subject: Re: [PATCH v3 2/9] drivers: irqchip: Add STM32 external interrupts support
Date: Mon, 5 Sep 2016 09:47:27 +0200	[thread overview]
Message-ID: <d790a3fd-766a-36d3-7a05-40b3198777c6@st.com> (raw)
In-Reply-To: <alpine.DEB.2.20.1609022052470.5647@nanos>

Hi Thomas,

On 09/02/2016 08:57 PM, Thomas Gleixner wrote:
> Alexandre,
>
> On Fri, 2 Sep 2016, Alexandre TORGUE wrote:
>
> This all looks very reasonable. The only complaint I have is your variable
> declaration ordering or the lack thereof.
>
> 1)
>> +	struct irq_domain *domain = irq_desc_get_handler_data(desc);
>> +	struct irq_chip_generic *gc = domain->gc->gc[0];
>> +	struct irq_chip *chip = irq_desc_get_chip(desc);
>> +	unsigned long pending;
>> +	int n;
>
> 2)
>> +	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(data);
>> +	u32 rtsr, ftsr;
>> +	int pin = data->hwirq;
>
> 3)
>> +	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(data);
>> +	int pin = data->hwirq;
>> +	u32 emr;
>
> 4)
>> +	irq_hw_number_t hwirq;
>> +	struct irq_fwspec *fwspec = data;
>> +	struct irq_chip_generic *gc = d->gc->gc[0];
>
> 5)
>> +	int nr_irqs, nr_exti, ret, i;
>> +	unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN;
>> +	struct irq_domain *domain;
>> +	struct irq_chip_generic *gc;
>> +	void *base;
>
> #1 and 3 have the ordering which is preferred in the irq code.
>
> #2, #4 and #5 are three permutations which are way harder to read.
>
>> +	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(data);
>> +	int pin = data->hwirq;
>> +	u32 rtsr, ftsr;
>
>> +	struct irq_chip_generic *gc = d->gc->gc[0];
>> +	struct irq_fwspec *fwspec = data;
>> +	irq_hw_number_t hwirq;
>
>> +	unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN;
>> +	int nr_irqs, nr_exti, ret, i;
>> +	struct irq_chip_generic *gc;
>> +	struct irq_domain *domain;
>> +	void *base;
>
> Can you spot the difference?

Thanks for review and for proposal. It Will be in next version.

Regards

Alex

>
> Thanks,
>
> 	tglx
>

  reply	other threads:[~2016-09-05  7:48 UTC|newest]

Thread overview: 14+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2016-09-02 15:33 [PATCH v3 0/9] Add STM32 EXTI interrupt controller support Alexandre TORGUE
2016-09-02 15:33 ` [PATCH v3 1/9] Documentation: dt-bindings: Document STM32 EXTI controller bindings Alexandre TORGUE
2016-09-02 15:33 ` [PATCH v3 2/9] drivers: irqchip: Add STM32 external interrupts support Alexandre TORGUE
2016-09-02 18:57   ` Thomas Gleixner
2016-09-05  7:47     ` Alexandre Torgue [this message]
2016-09-02 15:33 ` [PATCH v3 3/9] ARM: STM32: Select external interrupts controller Alexandre TORGUE
2016-09-02 15:33 ` [PATCH v3 4/9] ARM: dts: Add EXTI controller node to stm32f429 Alexandre TORGUE
2016-09-02 15:33 ` [PATCH v3 5/9] Documentation: dt-bindings: Add IRQ related properties of STM32 pinctrl Alexandre TORGUE
2016-09-02 15:33 ` [PATCH v3 6/9] pinctrl: Add IRQ support to STM32 gpios Alexandre TORGUE
2016-09-02 19:10   ` Thomas Gleixner
2016-09-05  7:53     ` Alexandre Torgue
2016-09-02 15:33 ` [PATCH v3 7/9] ARM: dts: Add GPIO irq support to STM2F429 Alexandre TORGUE
2016-09-02 15:33 ` [PATCH v3 8/9] ARM: dts: Declare push button as GPIO key on stm32f429 boards Alexandre TORGUE
2016-09-02 15:33 ` [PATCH v3 9/9] ARM: config: Enable GPIO Key driver in stm32_defconfig Alexandre TORGUE

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