From: <Parthiban.Veerasooran@microchip.com>
To: <kuba@kernel.org>
Cc: <andrew+netdev@lunn.ch>, <davem@davemloft.net>,
<edumazet@google.com>, <pabeni@redhat.com>,
<netdev@vger.kernel.org>, <linux-kernel@vger.kernel.org>
Subject: Re: [PATCH net 2/2] microchip: lan865x: fix missing configuration for Rev.B0/B1 as per AN1760
Date: Mon, 18 Aug 2025 04:44:52 +0000 [thread overview]
Message-ID: <d8a5c557-f76c-4bbd-a181-d35736ef4cbb@microchip.com> (raw)
In-Reply-To: <20250815184019.68116359@kernel.org>
Hi Kakub,
Thank you for reviewing the patches.
On 16/08/25 7:10 am, Jakub Kicinski wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>
> On Wed, 13 Aug 2025 16:03:55 +0530 Parthiban Veerasooran wrote:
>> +#define LAN865X_REG_FIXUP 0x00010077
>> +#define LAN865X_FIXUP_VALUE 0x0028
>
> Looks like the application note explains what this register is and what
> is the meaning of the bits in it. Please break this up and name
> properly. "FIXUP_REGISTER" and "FIXUP_VALUE" is about as useful
> as naming it "REGSITER_AT_10077" and "VALUE_28" :/
Yes, sure. I will update the correct details in the next version.
Since this falls under the initial settings, I initially kept this
configuration as a "fixup," similar to what we did in the PHY driver. In
that case, the PHY initial settings didn’t have valid register names or
details, so the "fixup" approach was appropriate.
However, in this case, we do have the register names and details
available in the configuration application note. So, I will update the
configuration accordingly.
Best regards,
Parthiban V
> --
> pw-bot: cr
prev parent reply other threads:[~2025-08-18 4:44 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-08-13 10:33 [PATCH net 0/2] Fixes on the Microchip's LAN865x driver Parthiban Veerasooran
2025-08-13 10:33 ` [PATCH net 1/2] microchip: lan865x: fix missing netif_start_queue() call on device open Parthiban Veerasooran
2025-08-13 10:33 ` [PATCH net 2/2] microchip: lan865x: fix missing configuration for Rev.B0/B1 as per AN1760 Parthiban Veerasooran
2025-08-16 1:40 ` Jakub Kicinski
2025-08-18 4:44 ` Parthiban.Veerasooran [this message]
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