[PATCH 0/3] Add missing UFS symbol 0/1 RX/TX clocks

[PATCH 0/3] Add missing UFS symbol 0/1 RX/TX clocks

[Taniya Das]

Some of the UFS symbol clock infrastructure has been left undescribed.
Add the required muxes in the global clock controller driver.

The UFS testcases have been verified with these clocks.

Signed-off-by: Taniya Das <taniya.das@oss.qualcomm.com>
---
Taniya Das (3):
      dt-bindings: clock: qcom,x1e80100-gcc: Add missing UFS mux clocks
      clk: qcom: gcc-x1e80100: Add missing UFS symbol mux clocks
      arm64: dts: qcom: hamoa: Extend the gcc input clock list

 .../bindings/clock/qcom,x1e80100-gcc.yaml          |   8 +-
 arch/arm64/boot/dts/qcom/hamoa.dtsi                |   3 +
 drivers/clk/qcom/gcc-x1e80100.c                    | 102 ++++++++++++++++++++-
 include/dt-bindings/clock/qcom,x1e80100-gcc.h      |   3 +
 4 files changed, 112 insertions(+), 4 deletions(-)
---
base-commit: cc3aa43b44bdb43dfbac0fcb51c56594a11338a8
change-id: 20251230-ufs_symbol_clk-c669042d65be

Best regards,
-- 
Taniya Das <taniya.das@oss.qualcomm.com>

[PATCH 1/3] dt-bindings: clock: qcom,x1e80100-gcc: Add missing UFS mux clocks

[Taniya Das]

Some of the UFS symbol rx/tx muxes were not initially described.

Add indices for them to allow extending the driver.

Signed-off-by: Taniya Das <taniya.das@oss.qualcomm.com>
---
 Documentation/devicetree/bindings/clock/qcom,x1e80100-gcc.yaml | 8 +++++++-
 include/dt-bindings/clock/qcom,x1e80100-gcc.h                  | 3 +++
 2 files changed, 10 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/clock/qcom,x1e80100-gcc.yaml b/Documentation/devicetree/bindings/clock/qcom,x1e80100-gcc.yaml
index 1b15b507095455c93b1ba39404cafbb6f96be5a9..881a5dd8d06f924a4627db5f8d17ad147a1011dd 100644
--- a/Documentation/devicetree/bindings/clock/qcom,x1e80100-gcc.yaml
+++ b/Documentation/devicetree/bindings/clock/qcom,x1e80100-gcc.yaml
@@ -62,6 +62,9 @@ properties:
       - description: USB4_1 PHY max PIPE clock source
       - description: USB4_2 PHY PCIE PIPE clock source
       - description: USB4_2 PHY max PIPE clock source
+      - description: UFS PHY RX Symbol 0 clock source
+      - description: UFS PHY RX Symbol 1 clock source
+      - description: UFS PHY TX Symbol 0 clock source
 
   power-domains:
     description:
@@ -121,7 +124,10 @@ examples:
                <&usb4_1_phy_pcie_pipe_clk>,
                <&usb4_1_phy_max_pipe_clk>,
                <&usb4_2_phy_pcie_pipe_clk>,
-               <&usb4_2_phy_max_pipe_clk>;
+               <&usb4_2_phy_max_pipe_clk>,
+               <&ufs_phy_rx_symbol_0>,
+               <&ufs_phy_rx_symbol_1>,
+               <&ufs_phy_tx_symbol_0>;
       power-domains = <&rpmhpd RPMHPD_CX>;
       #clock-cells = <1>;
       #reset-cells = <1>;
diff --git a/include/dt-bindings/clock/qcom,x1e80100-gcc.h b/include/dt-bindings/clock/qcom,x1e80100-gcc.h
index 62aa1242559270dd3bd31cd10322ee265468b8e4..d905804e64654dc8d01ab20eb1106cebf6e54b0e 100644
--- a/include/dt-bindings/clock/qcom,x1e80100-gcc.h
+++ b/include/dt-bindings/clock/qcom,x1e80100-gcc.h
@@ -387,6 +387,9 @@
 #define GCC_USB4_2_PHY_RX0_CLK_SRC				377
 #define GCC_USB4_2_PHY_RX1_CLK_SRC				378
 #define GCC_USB4_2_PHY_SYS_CLK_SRC				379
+#define GCC_UFS_PHY_RX_SYMBOL_0_CLK_SRC				380
+#define GCC_UFS_PHY_RX_SYMBOL_1_CLK_SRC				381
+#define GCC_UFS_PHY_TX_SYMBOL_0_CLK_SRC				382
 
 /* GCC power domains */
 #define GCC_PCIE_0_TUNNEL_GDSC					0

-- 
2.34.1

[PATCH 2/3] clk: qcom: gcc-x1e80100: Add missing UFS symbol mux clocks

[Taniya Das]

The UFS symbol RX/TX mux clocks were not defined previously.
Add these mux clocks so that clock rate propagation reaches
the muxes correctly.

Fixes: 161b7c401f4b ("clk: qcom: Add Global Clock controller (GCC) driver for X1E80100")
Signed-off-by: Taniya Das <taniya.das@oss.qualcomm.com>
---
 drivers/clk/qcom/gcc-x1e80100.c | 102 ++++++++++++++++++++++++++++++++++++++--
 1 file changed, 99 insertions(+), 3 deletions(-)

diff --git a/drivers/clk/qcom/gcc-x1e80100.c b/drivers/clk/qcom/gcc-x1e80100.c
index e46e65e631513e315de2f663f3dab73e1eb70604..c8fc9e6b1ac97b13f84753ac7f76e23df071c2e0 100644
--- a/drivers/clk/qcom/gcc-x1e80100.c
+++ b/drivers/clk/qcom/gcc-x1e80100.c
@@ -59,6 +59,9 @@ enum {
 	DT_USB4_1_PHY_GCC_USB4RTR_MAX_PIPE_CLK,
 	DT_USB4_2_PHY_GCC_USB4_PCIE_PIPE_CLK,
 	DT_USB4_2_PHY_GCC_USB4RTR_MAX_PIPE_CLK,
+	DT_UFS_PHY_RX_SYMBOL_0_CLK,
+	DT_UFS_PHY_RX_SYMBOL_1_CLK,
+	DT_UFS_PHY_TX_SYMBOL_0_CLK,
 };
 
 enum {
@@ -103,6 +106,9 @@ enum {
 	P_USB4_1_PHY_GCC_USB4RTR_MAX_PIPE_CLK,
 	P_USB4_2_PHY_GCC_USB4_PCIE_PIPE_CLK,
 	P_USB4_2_PHY_GCC_USB4RTR_MAX_PIPE_CLK,
+	P_UFS_PHY_RX_SYMBOL_0_CLK,
+	P_UFS_PHY_RX_SYMBOL_1_CLK,
+	P_UFS_PHY_TX_SYMBOL_0_CLK,
 };
 
 static struct clk_alpha_pll gcc_gpll0 = {
@@ -482,6 +488,78 @@ static const struct clk_parent_data gcc_parent_data_33[] = {
 	{ .index = DT_USB4_2_PHY_GCC_USB4_PCIE_PIPE_CLK },
 };
 
+static const struct parent_map gcc_parent_map_37[] = {
+	{ P_UFS_PHY_RX_SYMBOL_0_CLK, 0 },
+	{ P_BI_TCXO, 2 },
+};
+
+static const struct clk_parent_data gcc_parent_data_37[] = {
+	{ .index = DT_UFS_PHY_RX_SYMBOL_0_CLK },
+	{ .index = DT_BI_TCXO },
+};
+
+static const struct parent_map gcc_parent_map_38[] = {
+	{ P_UFS_PHY_RX_SYMBOL_1_CLK, 0 },
+	{ P_BI_TCXO, 2 },
+};
+
+static const struct clk_parent_data gcc_parent_data_38[] = {
+	{ .index = DT_UFS_PHY_RX_SYMBOL_1_CLK },
+	{ .index = DT_BI_TCXO },
+};
+
+static const struct parent_map gcc_parent_map_39[] = {
+	{ P_UFS_PHY_TX_SYMBOL_0_CLK, 0 },
+	{ P_BI_TCXO, 2 },
+};
+
+static const struct clk_parent_data gcc_parent_data_39[] = {
+	{ .index = DT_UFS_PHY_TX_SYMBOL_0_CLK },
+	{ .index = DT_BI_TCXO },
+};
+
+static struct clk_regmap_phy_mux gcc_ufs_phy_rx_symbol_0_clk_src = {
+	.reg = 0x77064,
+	.clkr = {
+		.hw.init = &(const struct clk_init_data) {
+			.name = "gcc_ufs_phy_rx_symbol_0_clk_src",
+			.parent_data = &(const struct clk_parent_data) {
+				.index = DT_UFS_PHY_RX_SYMBOL_0_CLK,
+			},
+			.num_parents = 1,
+			.ops = &clk_regmap_phy_mux_ops,
+		},
+	},
+};
+
+static struct clk_regmap_phy_mux gcc_ufs_phy_rx_symbol_1_clk_src = {
+	.reg = 0x770e0,
+	.clkr = {
+		.hw.init = &(const struct clk_init_data) {
+			.name = "gcc_ufs_phy_rx_symbol_1_clk_src",
+			.parent_data = &(const struct clk_parent_data) {
+				.index = DT_UFS_PHY_RX_SYMBOL_1_CLK,
+			},
+			.num_parents = 1,
+			.ops = &clk_regmap_phy_mux_ops,
+		},
+	},
+};
+
+static struct clk_regmap_phy_mux gcc_ufs_phy_tx_symbol_0_clk_src = {
+	.reg = 0x77054,
+	.clkr = {
+		.hw.init = &(const struct clk_init_data) {
+			.name = "gcc_ufs_phy_tx_symbol_0_clk_src",
+			.parent_data = &(const struct clk_parent_data) {
+				.index = DT_UFS_PHY_TX_SYMBOL_0_CLK,
+			},
+			.num_parents = 1,
+			.ops = &clk_regmap_phy_mux_ops,
+		},
+	},
+};
+
 static struct clk_regmap_phy_mux gcc_usb4_0_phy_dp0_clk_src = {
 	.reg = 0x9f06c,
 	.clkr = {
@@ -5148,12 +5226,17 @@ static struct clk_branch gcc_ufs_phy_phy_aux_clk = {
 
 static struct clk_branch gcc_ufs_phy_rx_symbol_0_clk = {
 	.halt_reg = 0x7702c,
-	.halt_check = BRANCH_HALT,
+	.halt_check = BRANCH_HALT_DELAY,
 	.clkr = {
 		.enable_reg = 0x7702c,
 		.enable_mask = BIT(0),
 		.hw.init = &(const struct clk_init_data) {
 			.name = "gcc_ufs_phy_rx_symbol_0_clk",
+			.parent_hws = (const struct clk_hw*[]) {
+				&gcc_ufs_phy_rx_symbol_0_clk_src.clkr.hw,
+			},
+			.num_parents = 1,
+			.flags = CLK_SET_RATE_PARENT,
 			.ops = &clk_branch2_ops,
 		},
 	},
@@ -5161,12 +5244,17 @@ static struct clk_branch gcc_ufs_phy_rx_symbol_0_clk = {
 
 static struct clk_branch gcc_ufs_phy_rx_symbol_1_clk = {
 	.halt_reg = 0x770cc,
-	.halt_check = BRANCH_HALT,
+	.halt_check = BRANCH_HALT_DELAY,
 	.clkr = {
 		.enable_reg = 0x770cc,
 		.enable_mask = BIT(0),
 		.hw.init = &(const struct clk_init_data) {
 			.name = "gcc_ufs_phy_rx_symbol_1_clk",
+			.parent_hws = (const struct clk_hw*[]) {
+				&gcc_ufs_phy_rx_symbol_1_clk_src.clkr.hw,
+			},
+			.num_parents = 1,
+			.flags = CLK_SET_RATE_PARENT,
 			.ops = &clk_branch2_ops,
 		},
 	},
@@ -5174,12 +5262,17 @@ static struct clk_branch gcc_ufs_phy_rx_symbol_1_clk = {
 
 static struct clk_branch gcc_ufs_phy_tx_symbol_0_clk = {
 	.halt_reg = 0x77028,
-	.halt_check = BRANCH_HALT,
+	.halt_check = BRANCH_HALT_DELAY,
 	.clkr = {
 		.enable_reg = 0x77028,
 		.enable_mask = BIT(0),
 		.hw.init = &(const struct clk_init_data) {
 			.name = "gcc_ufs_phy_tx_symbol_0_clk",
+			.parent_hws = (const struct clk_hw*[]) {
+				&gcc_ufs_phy_tx_symbol_0_clk_src.clkr.hw,
+			},
+			.num_parents = 1,
+			.flags = CLK_SET_RATE_PARENT,
 			.ops = &clk_branch2_ops,
 		},
 	},
@@ -7180,6 +7273,9 @@ static struct clk_regmap *gcc_x1e80100_clocks[] = {
 	[GCC_USB4_2_TMU_CLK_SRC] = &gcc_usb4_2_tmu_clk_src.clkr,
 	[GCC_VIDEO_AXI0_CLK] = &gcc_video_axi0_clk.clkr,
 	[GCC_VIDEO_AXI1_CLK] = &gcc_video_axi1_clk.clkr,
+	[GCC_UFS_PHY_RX_SYMBOL_0_CLK_SRC] = &gcc_ufs_phy_rx_symbol_0_clk_src.clkr,
+	[GCC_UFS_PHY_RX_SYMBOL_1_CLK_SRC] = &gcc_ufs_phy_rx_symbol_1_clk_src.clkr,
+	[GCC_UFS_PHY_TX_SYMBOL_0_CLK_SRC] = &gcc_ufs_phy_tx_symbol_0_clk_src.clkr,
 };
 
 static struct gdsc *gcc_x1e80100_gdscs[] = {

-- 
2.34.1

[PATCH 3/3] arm64: dts: qcom: hamoa: Extend the gcc input clock list

[Taniya Das]

The recent dt-bindings were updated for the missing RX/TX symbol clocks
for UFS.

Extend the existing list to make sure the DT contains the expected
amount of 'clocks' entries.

Signed-off-by: Taniya Das <taniya.das@oss.qualcomm.com>
---
 arch/arm64/boot/dts/qcom/hamoa.dtsi | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/hamoa.dtsi b/arch/arm64/boot/dts/qcom/hamoa.dtsi
index bb7c14d473c9c523e1501f9379ee7049c6287e96..21ab6ef61520695d977f9d741ce633cf537171ac 100644
--- a/arch/arm64/boot/dts/qcom/hamoa.dtsi
+++ b/arch/arm64/boot/dts/qcom/hamoa.dtsi
@@ -834,6 +834,9 @@ gcc: clock-controller@100000 {
 				 <0>,
 				 <0>,
 				 <0>,
+				 <0>,
+				 <0>,
+				 <0>,
 				 <0>;
 
 			power-domains = <&rpmhpd RPMHPD_CX>;

-- 
2.34.1

Re: [PATCH 2/3] clk: qcom: gcc-x1e80100: Add missing UFS symbol mux clocks

[Dmitry Baryshkov]

On Tue, Dec 30, 2025 at 11:08:35PM +0530, Taniya Das wrote:
> The UFS symbol RX/TX mux clocks were not defined previously.
> Add these mux clocks so that clock rate propagation reaches
> the muxes correctly.
> 
> Fixes: 161b7c401f4b ("clk: qcom: Add Global Clock controller (GCC) driver for X1E80100")
> Signed-off-by: Taniya Das <taniya.das@oss.qualcomm.com>
> ---
>  drivers/clk/qcom/gcc-x1e80100.c | 102 ++++++++++++++++++++++++++++++++++++++--
>  1 file changed, 99 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/clk/qcom/gcc-x1e80100.c b/drivers/clk/qcom/gcc-x1e80100.c
> index e46e65e631513e315de2f663f3dab73e1eb70604..c8fc9e6b1ac97b13f84753ac7f76e23df071c2e0 100644
> --- a/drivers/clk/qcom/gcc-x1e80100.c
> +++ b/drivers/clk/qcom/gcc-x1e80100.c
> @@ -59,6 +59,9 @@ enum {
>  	DT_USB4_1_PHY_GCC_USB4RTR_MAX_PIPE_CLK,
>  	DT_USB4_2_PHY_GCC_USB4_PCIE_PIPE_CLK,
>  	DT_USB4_2_PHY_GCC_USB4RTR_MAX_PIPE_CLK,
> +	DT_UFS_PHY_RX_SYMBOL_0_CLK,
> +	DT_UFS_PHY_RX_SYMBOL_1_CLK,
> +	DT_UFS_PHY_TX_SYMBOL_0_CLK,
>  };
>  
>  enum {
> @@ -103,6 +106,9 @@ enum {
>  	P_USB4_1_PHY_GCC_USB4RTR_MAX_PIPE_CLK,
>  	P_USB4_2_PHY_GCC_USB4_PCIE_PIPE_CLK,
>  	P_USB4_2_PHY_GCC_USB4RTR_MAX_PIPE_CLK,
> +	P_UFS_PHY_RX_SYMBOL_0_CLK,
> +	P_UFS_PHY_RX_SYMBOL_1_CLK,
> +	P_UFS_PHY_TX_SYMBOL_0_CLK,
>  };
>  
>  static struct clk_alpha_pll gcc_gpll0 = {
> @@ -482,6 +488,78 @@ static const struct clk_parent_data gcc_parent_data_33[] = {
>  	{ .index = DT_USB4_2_PHY_GCC_USB4_PCIE_PIPE_CLK },
>  };
>  
> +static const struct parent_map gcc_parent_map_37[] = {
> +	{ P_UFS_PHY_RX_SYMBOL_0_CLK, 0 },
> +	{ P_BI_TCXO, 2 },
> +};
> +
> +static const struct clk_parent_data gcc_parent_data_37[] = {
> +	{ .index = DT_UFS_PHY_RX_SYMBOL_0_CLK },
> +	{ .index = DT_BI_TCXO },
> +};
> +
> +static const struct parent_map gcc_parent_map_38[] = {
> +	{ P_UFS_PHY_RX_SYMBOL_1_CLK, 0 },
> +	{ P_BI_TCXO, 2 },
> +};
> +
> +static const struct clk_parent_data gcc_parent_data_38[] = {
> +	{ .index = DT_UFS_PHY_RX_SYMBOL_1_CLK },
> +	{ .index = DT_BI_TCXO },
> +};
> +
> +static const struct parent_map gcc_parent_map_39[] = {
> +	{ P_UFS_PHY_TX_SYMBOL_0_CLK, 0 },
> +	{ P_BI_TCXO, 2 },
> +};
> +
> +static const struct clk_parent_data gcc_parent_data_39[] = {
> +	{ .index = DT_UFS_PHY_TX_SYMBOL_0_CLK },
> +	{ .index = DT_BI_TCXO },
> +};

And all of these parent maps and parent data are unused.

> +
> +static struct clk_regmap_phy_mux gcc_ufs_phy_rx_symbol_0_clk_src = {
> +	.reg = 0x77064,
> +	.clkr = {
> +		.hw.init = &(const struct clk_init_data) {
> +			.name = "gcc_ufs_phy_rx_symbol_0_clk_src",
> +			.parent_data = &(const struct clk_parent_data) {
> +				.index = DT_UFS_PHY_RX_SYMBOL_0_CLK,
> +			},
> +			.num_parents = 1,
> +			.ops = &clk_regmap_phy_mux_ops,
> +		},
> +	},
> +};
> +
> +static struct clk_regmap_phy_mux gcc_ufs_phy_rx_symbol_1_clk_src = {
> +	.reg = 0x770e0,
> +	.clkr = {
> +		.hw.init = &(const struct clk_init_data) {
> +			.name = "gcc_ufs_phy_rx_symbol_1_clk_src",
> +			.parent_data = &(const struct clk_parent_data) {
> +				.index = DT_UFS_PHY_RX_SYMBOL_1_CLK,
> +			},
> +			.num_parents = 1,
> +			.ops = &clk_regmap_phy_mux_ops,
> +		},
> +	},
> +};
> +
> +static struct clk_regmap_phy_mux gcc_ufs_phy_tx_symbol_0_clk_src = {
> +	.reg = 0x77054,
> +	.clkr = {
> +		.hw.init = &(const struct clk_init_data) {
> +			.name = "gcc_ufs_phy_tx_symbol_0_clk_src",
> +			.parent_data = &(const struct clk_parent_data) {
> +				.index = DT_UFS_PHY_TX_SYMBOL_0_CLK,
> +			},
> +			.num_parents = 1,
> +			.ops = &clk_regmap_phy_mux_ops,
> +		},
> +	},
> +};
> +
>  static struct clk_regmap_phy_mux gcc_usb4_0_phy_dp0_clk_src = {
>  	.reg = 0x9f06c,
>  	.clkr = {
> @@ -5148,12 +5226,17 @@ static struct clk_branch gcc_ufs_phy_phy_aux_clk = {
>  
>  static struct clk_branch gcc_ufs_phy_rx_symbol_0_clk = {
>  	.halt_reg = 0x7702c,
> -	.halt_check = BRANCH_HALT,
> +	.halt_check = BRANCH_HALT_DELAY,
>  	.clkr = {
>  		.enable_reg = 0x7702c,
>  		.enable_mask = BIT(0),
>  		.hw.init = &(const struct clk_init_data) {
>  			.name = "gcc_ufs_phy_rx_symbol_0_clk",
> +			.parent_hws = (const struct clk_hw*[]) {
> +				&gcc_ufs_phy_rx_symbol_0_clk_src.clkr.hw,
> +			},
> +			.num_parents = 1,
> +			.flags = CLK_SET_RATE_PARENT,
>  			.ops = &clk_branch2_ops,
>  		},
>  	},
> @@ -5161,12 +5244,17 @@ static struct clk_branch gcc_ufs_phy_rx_symbol_0_clk = {
>  
>  static struct clk_branch gcc_ufs_phy_rx_symbol_1_clk = {
>  	.halt_reg = 0x770cc,
> -	.halt_check = BRANCH_HALT,
> +	.halt_check = BRANCH_HALT_DELAY,
>  	.clkr = {
>  		.enable_reg = 0x770cc,
>  		.enable_mask = BIT(0),
>  		.hw.init = &(const struct clk_init_data) {
>  			.name = "gcc_ufs_phy_rx_symbol_1_clk",
> +			.parent_hws = (const struct clk_hw*[]) {
> +				&gcc_ufs_phy_rx_symbol_1_clk_src.clkr.hw,
> +			},
> +			.num_parents = 1,
> +			.flags = CLK_SET_RATE_PARENT,
>  			.ops = &clk_branch2_ops,
>  		},
>  	},
> @@ -5174,12 +5262,17 @@ static struct clk_branch gcc_ufs_phy_rx_symbol_1_clk = {
>  
>  static struct clk_branch gcc_ufs_phy_tx_symbol_0_clk = {
>  	.halt_reg = 0x77028,
> -	.halt_check = BRANCH_HALT,
> +	.halt_check = BRANCH_HALT_DELAY,
>  	.clkr = {
>  		.enable_reg = 0x77028,
>  		.enable_mask = BIT(0),
>  		.hw.init = &(const struct clk_init_data) {
>  			.name = "gcc_ufs_phy_tx_symbol_0_clk",
> +			.parent_hws = (const struct clk_hw*[]) {
> +				&gcc_ufs_phy_tx_symbol_0_clk_src.clkr.hw,
> +			},
> +			.num_parents = 1,
> +			.flags = CLK_SET_RATE_PARENT,
>  			.ops = &clk_branch2_ops,
>  		},
>  	},
> @@ -7180,6 +7273,9 @@ static struct clk_regmap *gcc_x1e80100_clocks[] = {
>  	[GCC_USB4_2_TMU_CLK_SRC] = &gcc_usb4_2_tmu_clk_src.clkr,
>  	[GCC_VIDEO_AXI0_CLK] = &gcc_video_axi0_clk.clkr,
>  	[GCC_VIDEO_AXI1_CLK] = &gcc_video_axi1_clk.clkr,
> +	[GCC_UFS_PHY_RX_SYMBOL_0_CLK_SRC] = &gcc_ufs_phy_rx_symbol_0_clk_src.clkr,
> +	[GCC_UFS_PHY_RX_SYMBOL_1_CLK_SRC] = &gcc_ufs_phy_rx_symbol_1_clk_src.clkr,
> +	[GCC_UFS_PHY_TX_SYMBOL_0_CLK_SRC] = &gcc_ufs_phy_tx_symbol_0_clk_src.clkr,
>  };
>  
>  static struct gdsc *gcc_x1e80100_gdscs[] = {
> 
> -- 
> 2.34.1
> 

-- 
With best wishes
Dmitry

Re: [PATCH 3/3] arm64: dts: qcom: hamoa: Extend the gcc input clock list

[Dmitry Baryshkov]

On Tue, Dec 30, 2025 at 11:08:36PM +0530, Taniya Das wrote:
> The recent dt-bindings were updated for the missing RX/TX symbol clocks
> for UFS.
> 
> Extend the existing list to make sure the DT contains the expected
> amount of 'clocks' entries.
> 
> Signed-off-by: Taniya Das <taniya.das@oss.qualcomm.com>
> ---
>  arch/arm64/boot/dts/qcom/hamoa.dtsi | 3 +++
>  1 file changed, 3 insertions(+)
> 

Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>


-- 
With best wishes
Dmitry

Re: [PATCH 3/3] arm64: dts: qcom: hamoa: Extend the gcc input clock list

[Abel Vesa]

On 25-12-30 23:08:36, Taniya Das wrote:
> The recent dt-bindings were updated for the missing RX/TX symbol clocks
> for UFS.
> 
> Extend the existing list to make sure the DT contains the expected
> amount of 'clocks' entries.
> 
> Signed-off-by: Taniya Das <taniya.das@oss.qualcomm.com>

Reviewed-by: Abel Vesa <abel.vesa@oss.qualcomm.com>

Re: [PATCH 2/3] clk: qcom: gcc-x1e80100: Add missing UFS symbol mux clocks

[Abel Vesa]

On 25-12-30 23:08:35, Taniya Das wrote:
> The UFS symbol RX/TX mux clocks were not defined previously.
> Add these mux clocks so that clock rate propagation reaches
> the muxes correctly.
> 
> Fixes: 161b7c401f4b ("clk: qcom: Add Global Clock controller (GCC) driver for X1E80100")
> Signed-off-by: Taniya Das <taniya.das@oss.qualcomm.com>

Reviewed-by: Abel Vesa <abel.vesa@oss.qualcomm.com>

Re: [PATCH 2/3] clk: qcom: gcc-x1e80100: Add missing UFS symbol mux clocks

[Taniya Das]

On 12/30/2025 11:39 PM, Dmitry Baryshkov wrote:
>>  };
>>  
>> +static const struct parent_map gcc_parent_map_37[] = {
>> +	{ P_UFS_PHY_RX_SYMBOL_0_CLK, 0 },
>> +	{ P_BI_TCXO, 2 },
>> +};
>> +
>> +static const struct clk_parent_data gcc_parent_data_37[] = {
>> +	{ .index = DT_UFS_PHY_RX_SYMBOL_0_CLK },
>> +	{ .index = DT_BI_TCXO },
>> +};
>> +
>> +static const struct parent_map gcc_parent_map_38[] = {
>> +	{ P_UFS_PHY_RX_SYMBOL_1_CLK, 0 },
>> +	{ P_BI_TCXO, 2 },
>> +};
>> +
>> +static const struct clk_parent_data gcc_parent_data_38[] = {
>> +	{ .index = DT_UFS_PHY_RX_SYMBOL_1_CLK },
>> +	{ .index = DT_BI_TCXO },
>> +};
>> +
>> +static const struct parent_map gcc_parent_map_39[] = {
>> +	{ P_UFS_PHY_TX_SYMBOL_0_CLK, 0 },
>> +	{ P_BI_TCXO, 2 },
>> +};
>> +
>> +static const struct clk_parent_data gcc_parent_data_39[] = {
>> +	{ .index = DT_UFS_PHY_TX_SYMBOL_0_CLK },
>> +	{ .index = DT_BI_TCXO },
>> +};
> And all of these parent maps and parent data are unused.

Sure, I will remove them in the next patch.

-- 
Thanks,
Taniya Das

Re: [PATCH 1/3] dt-bindings: clock: qcom,x1e80100-gcc: Add missing UFS mux clocks

[Krzysztof Kozlowski]

On Tue, Dec 30, 2025 at 11:08:34PM +0530, Taniya Das wrote:
> Some of the UFS symbol rx/tx muxes were not initially described.
> 
> Add indices for them to allow extending the driver.

Please drop this. We do not add bindings to allow extending driver, so
above is not the correct reason to do anything here.

> 
> Signed-off-by: Taniya Das <taniya.das@oss.qualcomm.com>

Best regards,
Krzysztof

Re: [PATCH 1/3] dt-bindings: clock: qcom,x1e80100-gcc: Add missing UFS mux clocks

[Taniya Das]

On 1/2/2026 5:44 PM, Krzysztof Kozlowski wrote:
> On Tue, Dec 30, 2025 at 11:08:34PM +0530, Taniya Das wrote:
>> Some of the UFS symbol rx/tx muxes were not initially described.
>>
>> Add indices for them to allow extending the driver.
> 
> Please drop this. We do not add bindings to allow extending driver, so
> above is not the correct reason to do anything here.
> 

Sure will remove this.

>>
>> Signed-off-by: Taniya Das <taniya.das@oss.qualcomm.com>
> 
> Best regards,
> Krzysztof
> 

-- 
Thanks,
Taniya Das