Re: [PATCH 4/4] platform/x86/amd/hsmp: Add pwr_current_active_freq_limit_source_raw

[Carlos Bilbao <carlos.bilbao.osdev@gmail.com>]

On 10/7/26 05:59, Erwan Velu wrote:

> From: Erwan Velu <e.velu@criteo.com>
>
> pwr_current_active_freq_limit_source reports the active frequency limit
> sources as a list of names, one per line, which metrics exporters have
> to parse and map back to a value.
>
> Add pwr_current_active_freq_limit_source_raw, reporting the same source
> bitmask as a single hexadecimal value. Exporters only need a plain
> integer conversion, and its interpretation can be centralized in the
> monitoring stack, e.g. with Grafana value mappings, instead of being
> decoded on each server.
>
> The bit assignment is defined by the HSMP specification and is stable:
> new limit sources are only appended, existing bits never change meaning.
> A given value therefore has a single interpretation, whatever the
> platform or kernel version it comes from.
>
> Assisted-by: claude-opus-5-5
> Signed-off-by: Erwan Velu <e.velu@criteo.com>


Acked-by: Carlos Bilbao <carlos.bilbao@kernel.org>


> ---
>   Documentation/arch/x86/amd_hsmp.rst   |  4 ++++
>   drivers/platform/x86/amd/hsmp/sysfs.c | 18 ++++++++++++++++++
>   2 files changed, 22 insertions(+)
>
> diff --git a/Documentation/arch/x86/amd_hsmp.rst b/Documentation/arch/x86/amd_hsmp.rst
> index 954e938eea3d..66dbf506db05 100644
> --- a/Documentation/arch/x86/amd_hsmp.rst
> +++ b/Documentation/arch/x86/amd_hsmp.rst
> @@ -109,6 +109,10 @@ Following sysfs files are available at /sys/devices/amd_hsmp/socket%d/.
>     in MHz.
>   * pwr_current_active_freq_limit_source: Source of current active frequency
>     limit.
> +* pwr_current_active_freq_limit_source_raw: Source of current active
> +  frequency limit, as a hexadecimal bitmask. Bits 0 to 7 are, in order:
> +  cHTC-Active, PROCHOT, TDC limit, PPT Limit, OPN Max, Reliability Limit,
> +  APML Agent, HSMP Agent.
>   
>   ACPI device object format
>   =========================
> diff --git a/drivers/platform/x86/amd/hsmp/sysfs.c b/drivers/platform/x86/amd/hsmp/sysfs.c
> index e9e91b640b2a..fa1cf8dc3b6f 100644
> --- a/drivers/platform/x86/amd/hsmp/sysfs.c
> +++ b/drivers/platform/x86/amd/hsmp/sysfs.c
> @@ -274,6 +274,21 @@ static ssize_t hsmp_freq_limit_source_show(struct device *dev, struct device_att
>   	return len;
>   }
>   
> +static ssize_t hsmp_freq_limit_source_raw_show(struct device *dev,
> +					       struct device_attribute *attr, char *buf)
> +{
> +	struct hsmp_sys_attr *hattr = to_hsmp_sys_attr(attr);
> +	struct hsmp_socket *sock = dev_get_drvdata(dev);
> +	u32 data;
> +	int ret;
> +
> +	ret = hsmp_msg_get_nargs(sock->sock_ind, hattr->msg_id, &data, 1);
> +	if (ret)
> +		return ret;
> +
> +	return sysfs_emit(buf, "0x%04lx\n", FIELD_GET(FREQ_SRC_IND_MASK, data));
> +}
> +
>   static const struct bin_attribute  hsmp_metric_tbl_attr = {
>   	.attr = { .name = HSMP_METRICS_TABLE_NAME, .mode = 0444},
>   	.read = hsmp_metric_tbl_acpi_read,
> @@ -307,6 +322,8 @@ HSMP_DEV_ATTR(pwr_current_active_freq_limit, HSMP_GET_SOCKET_FREQ_LIMIT,
>   	      hsmp_freq_limit_show, 0444);
>   HSMP_DEV_ATTR(pwr_current_active_freq_limit_source, HSMP_GET_SOCKET_FREQ_LIMIT,
>   	      hsmp_freq_limit_source_show, 0444);
> +HSMP_DEV_ATTR(pwr_current_active_freq_limit_source_raw, HSMP_GET_SOCKET_FREQ_LIMIT,
> +	      hsmp_freq_limit_source_raw_show, 0444);
>   
>   static struct attribute *hsmp_dev_attr_list[] = {
>   	&hattr_c0_residency_input.dattr.attr,
> @@ -323,6 +340,7 @@ static struct attribute *hsmp_dev_attr_list[] = {
>   	&hattr_clk_fmin.dattr.attr,
>   	&hattr_pwr_current_active_freq_limit.dattr.attr,
>   	&hattr_pwr_current_active_freq_limit_source.dattr.attr,
> +	&hattr_pwr_current_active_freq_limit_source_raw.dattr.attr,
>   	NULL
>   };
>