* [PATCH v2 0/5] Add bootph-all property for J7 boards
@ 2024-07-05 6:26 Manorit Chawdhry
2024-07-05 6:26 ` [PATCH v2 1/5] arm64: dts: ti: k3-j721s2*: Add bootph-* properties Manorit Chawdhry
` (5 more replies)
0 siblings, 6 replies; 9+ messages in thread
From: Manorit Chawdhry @ 2024-07-05 6:26 UTC (permalink / raw)
To: Nishanth Menon, Vignesh Raghavendra, Tero Kristo, Rob Herring,
Krzysztof Kozlowski, Conor Dooley
Cc: linux-arm-kernel, devicetree, linux-kernel, Neha Malcom Francis,
Aniket Limaye, Udit Kumar, Beleswar Padhi, Manorit Chawdhry
The idea of this series is to add bootph-all and bootph-pre-ram property
in all the leaf nodes wherever required and cleanup any other places where
bootph-all/bootph-pre-ram exist in the parent nodes as well.
Signed-off-by: Manorit Chawdhry <m-chawdhry@ti.com>
---
Changes in v2:
* Aniket
- Change wkup_vtm0 bootph-all to bootph-pre-ram
- Add bootph-all explicitly to dmsc/sms nodes as otherwise the boards
don't boot
- Cleanup more nodes along with some testing with u-boot.
- Fix build errors
- Link to v1: https://lore.kernel.org/r/20240507-b4-upstream-bootph-all-v1-0-c6d52651856f@ti.com
---
Manorit Chawdhry (5):
arm64: dts: ti: k3-j721s2*: Add bootph-* properties
arm64: dts: ti: k3-j784s4*: Remove bootph properties from parent nodes
arm64: dts: ti: k3-am68*: Add bootph-* properties
arm64: dts: ti: k3-j721e*: Add bootph-* properties
arm64: dts: ti: k3-j7200*: Add bootph-* properties
arch/arm64/boot/dts/ti/k3-am68-sk-base-board.dts | 10 ++++++++++
arch/arm64/boot/dts/ti/k3-am68-sk-som.dtsi | 2 ++
.../boot/dts/ti/k3-j7200-common-proc-board.dts | 23 ++++++++++++++++++++++
arch/arm64/boot/dts/ti/k3-j7200-main.dtsi | 2 ++
arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi | 11 +++++++++++
arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi | 7 +++++++
.../boot/dts/ti/k3-j721e-common-proc-board.dts | 20 +++++++++++++++++++
arch/arm64/boot/dts/ti/k3-j721e-main.dtsi | 2 ++
arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi | 10 ++++++++++
arch/arm64/boot/dts/ti/k3-j721e-sk.dts | 18 +++++++++++++++++
arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi | 5 +++++
.../boot/dts/ti/k3-j721s2-common-proc-board.dts | 14 +++++++++++++
arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi | 2 ++
arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi | 12 +++++++++++
arch/arm64/boot/dts/ti/k3-j721s2-som-p0.dtsi | 2 ++
arch/arm64/boot/dts/ti/k3-j784s4-evm.dts | 9 +--------
arch/arm64/boot/dts/ti/k3-j784s4-mcu-wakeup.dtsi | 7 ++++---
17 files changed, 145 insertions(+), 11 deletions(-)
---
base-commit: 0b58e108042b0ed28a71cd7edf5175999955b233
change-id: 20240430-b4-upstream-bootph-all-8d47b72bc0fd
Best regards,
--
Manorit Chawdhry <m-chawdhry@ti.com>
^ permalink raw reply [flat|nested] 9+ messages in thread
* [PATCH v2 1/5] arm64: dts: ti: k3-j721s2*: Add bootph-* properties
2024-07-05 6:26 [PATCH v2 0/5] Add bootph-all property for J7 boards Manorit Chawdhry
@ 2024-07-05 6:26 ` Manorit Chawdhry
2024-07-09 7:32 ` Vignesh Raghavendra
2024-07-05 6:26 ` [PATCH v2 2/5] arm64: dts: ti: k3-j784s4*: Remove bootph properties from parent nodes Manorit Chawdhry
` (4 subsequent siblings)
5 siblings, 1 reply; 9+ messages in thread
From: Manorit Chawdhry @ 2024-07-05 6:26 UTC (permalink / raw)
To: Nishanth Menon, Vignesh Raghavendra, Tero Kristo, Rob Herring,
Krzysztof Kozlowski, Conor Dooley
Cc: linux-arm-kernel, devicetree, linux-kernel, Neha Malcom Francis,
Aniket Limaye, Udit Kumar, Beleswar Padhi, Manorit Chawdhry
Adds bootph-* properties to the leaf nodes to enable U-boot to
utilise them.
Signed-off-by: Manorit Chawdhry <m-chawdhry@ti.com>
---
arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts | 14 ++++++++++++++
arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi | 2 ++
arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi | 12 ++++++++++++
arch/arm64/boot/dts/ti/k3-j721s2-som-p0.dtsi | 2 ++
4 files changed, 30 insertions(+)
diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts
index c5a0b7cbb14f..6ce14f9e087b 100644
--- a/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts
+++ b/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts
@@ -138,6 +138,7 @@ J721S2_IOPAD(0x044, PIN_OUTPUT, 14) /* (Y26) MCASP0_AXR1.UART8_RTSn */
J721S2_IOPAD(0x0d0, PIN_INPUT, 11) /* (AF26) SPI0_CS1.UART8_RXD */
J721S2_IOPAD(0x0d4, PIN_OUTPUT, 11) /* (AH27) SPI0_CLK.UART8_TXD */
>;
+ bootph-all;
};
main_i2c3_pins_default: main-i2c3-default-pins {
@@ -165,6 +166,7 @@ J721S2_IOPAD(0x0f4, PIN_INPUT, 0) /* (R24) MMC1_DAT2 */
J721S2_IOPAD(0x0f0, PIN_INPUT, 0) /* (R22) MMC1_DAT3 */
J721S2_IOPAD(0x0e8, PIN_INPUT, 8) /* (AE25) TIMER_IO0.MMC1_SDCD */
>;
+ bootph-all;
};
vdd_sd_dv_pins_default: vdd-sd-dv-default-pins {
@@ -177,6 +179,7 @@ main_usbss0_pins_default: main-usbss0-default-pins {
pinctrl-single,pins = <
J721S2_IOPAD(0x0ec, PIN_OUTPUT, 6) /* (AG25) TIMER_IO1.USB0_DRVVBUS */
>;
+ bootph-all;
};
main_mcan3_pins_default: main-mcan3-default-pins {
@@ -200,6 +203,7 @@ wkup_uart0_pins_default: wkup-uart0-default-pins {
J721S2_WKUP_IOPAD(0x048, PIN_INPUT, 0) /* (D28) WKUP_UART0_RXD */
J721S2_WKUP_IOPAD(0x04c, PIN_OUTPUT, 0) /* (D27) WKUP_UART0_TXD */
>;
+ bootph-all;
};
mcu_uart0_pins_default: mcu-uart0-default-pins {
@@ -209,6 +213,7 @@ J721S2_WKUP_IOPAD(0x094, PIN_OUTPUT, 0) /* (D25) WKUP_GPIO0_15.MCU_UART0_RTSn */
J721S2_WKUP_IOPAD(0x08c, PIN_INPUT, 0) /* (C24) WKUP_GPIO0_13.MCU_UART0_RXD */
J721S2_WKUP_IOPAD(0x088, PIN_OUTPUT, 0) /* (C25) WKUP_GPIO0_12.MCU_UART0_TXD */
>;
+ bootph-all;
};
mcu_cpsw_pins_default: mcu-cpsw-default-pins {
@@ -301,6 +306,7 @@ J721S2_WKUP_IOPAD(0x020, PIN_INPUT, 0) /* (A20) MCU_OSPI1_D3 */
J721S2_WKUP_IOPAD(0x010, PIN_INPUT, 0) /* (B19) MCU_OSPI1_DQS */
J721S2_WKUP_IOPAD(0x00c, PIN_INPUT, 0) /* (B20) MCU_OSPI1_LBCLKO */
>;
+ bootph-all;
};
};
@@ -316,12 +322,14 @@ &wkup_uart0 {
status = "reserved";
pinctrl-names = "default";
pinctrl-0 = <&wkup_uart0_pins_default>;
+ bootph-all;
};
&mcu_uart0 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&mcu_uart0_pins_default>;
+ bootph-all;
};
&main_uart8 {
@@ -330,6 +338,7 @@ &main_uart8 {
pinctrl-0 = <&main_uart8_pins_default>;
/* Shared with TFA on this platform */
power-domains = <&k3_pds 357 TI_SCI_PD_SHARED>;
+ bootph-all;
};
&main_i2c0 {
@@ -385,6 +394,7 @@ &main_sdhci0 {
non-removable;
ti,driver-strength-ohm = <50>;
disable-wp;
+ bootph-all;
};
&main_sdhci1 {
@@ -395,6 +405,7 @@ &main_sdhci1 {
disable-wp;
vmmc-supply = <&vdd_mmc1>;
vqmmc-supply = <&vdd_sd_dv>;
+ bootph-all;
};
&mcu_cpsw {
@@ -446,11 +457,13 @@ &usbss0 {
pinctrl-names = "default";
ti,vbus-divider;
ti,usb2-only;
+ bootph-all;
};
&usb0 {
dr_mode = "otg";
maximum-speed = "high-speed";
+ bootph-all;
};
&ospi1 {
@@ -469,6 +482,7 @@ flash@0 {
cdns,tchsh-ns = <60>;
cdns,tslch-ns = <60>;
cdns,read-delay = <2>;
+ bootph-all;
};
};
diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi
index 9ed6949b40e9..0ea6817de65c 100644
--- a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi
@@ -816,6 +816,7 @@ secure_proxy_main: mailbox@32c00000 {
<0x00 0x32800000 0x00 0x100000>;
interrupt-names = "rx_011";
interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
+ bootph-all;
};
hwspinlock: spinlock@30e00000 {
@@ -1225,6 +1226,7 @@ usb0: usb@6000000 {
interrupt-names = "host", "peripheral", "otg";
maximum-speed = "super-speed";
dr_mode = "otg";
+ bootph-all;
};
};
diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi
index 8feb42c89e47..497e0dfa8011 100644
--- a/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi
@@ -17,20 +17,24 @@ sms: system-controller@44083000 {
reg-names = "debug_messages";
reg = <0x00 0x44083000 0x00 0x1000>;
+ bootph-all;
k3_pds: power-controller {
compatible = "ti,sci-pm-domain";
#power-domain-cells = <2>;
+ bootph-all;
};
k3_clks: clock-controller {
compatible = "ti,k2g-sci-clk";
#clock-cells = <2>;
+ bootph-all;
};
k3_reset: reset-controller {
compatible = "ti,sci-reset";
#reset-cells = <2>;
+ bootph-all;
};
};
@@ -43,6 +47,7 @@ wkup_conf: bus@43000000 {
chipid: chipid@14 {
compatible = "ti,am654-chipid";
reg = <0x14 0x4>;
+ bootph-all;
};
};
@@ -59,6 +64,7 @@ secure_proxy_sa3: mailbox@43600000 {
* firmware on non-MPU processors
*/
status = "disabled";
+ bootph-pre-ram;
};
mcu_ram: sram@41c00000 {
@@ -170,6 +176,7 @@ mcu_timer0: timer@40400000 {
ti,timer-pwm;
/* Non-MPU Firmware usage */
status = "reserved";
+ bootph-pre-ram;
};
mcu_timer1: timer@40410000 {
@@ -362,6 +369,7 @@ wkup_i2c0: i2c@42120000 {
clock-names = "fck";
power-domains = <&k3_pds 223 TI_SCI_PD_EXCLUSIVE>;
status = "disabled";
+ bootph-all;
};
mcu_i2c0: i2c@40b00000 {
@@ -474,6 +482,7 @@ mcu_ringacc: ringacc@2b800000 {
ti,sci = <&sms>;
ti,sci-dev-id = <272>;
msi-parent = <&main_udmass_inta>;
+ bootph-all;
};
mcu_udmap: dma-controller@285c0000 {
@@ -497,6 +506,7 @@ mcu_udmap: dma-controller@285c0000 {
ti,sci-rm-range-rchan = <0x0a>, /* RX_CHAN */
<0x0b>; /* RX_HCHAN */
ti,sci-rm-range-rflow = <0x00>; /* GP RFLOW */
+ bootph-all;
};
};
@@ -513,6 +523,7 @@ secure_proxy_mcu: mailbox@2a480000 {
* firmware on non-MPU processors
*/
status = "disabled";
+ bootph-pre-ram;
};
mcu_cpsw: ethernet@46000000 {
@@ -667,6 +678,7 @@ wkup_vtm0: temperature-sensor@42040000 {
<0x00 0x42050000 0x0 0x350>;
power-domains = <&k3_pds 180 TI_SCI_PD_SHARED>;
#thermal-sensor-cells = <1>;
+ bootph-pre-ram;
};
mcu_r5fss0: r5fss@41000000 {
diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-som-p0.dtsi b/arch/arm64/boot/dts/ti/k3-j721s2-som-p0.dtsi
index 82aacc01e8fe..dfcc223809e7 100644
--- a/arch/arm64/boot/dts/ti/k3-j721s2-som-p0.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j721s2-som-p0.dtsi
@@ -170,6 +170,7 @@ J721S2_WKUP_IOPAD(0x028, PIN_INPUT, 0) /* (F20) MCU_OSPI0_D7 */
J721S2_WKUP_IOPAD(0x008, PIN_INPUT, 0) /* (E18) MCU_OSPI0_DQS */
J721S2_WKUP_IOPAD(0x004, PIN_INPUT, 0) /* (E20) MCU_OSPI0_LBCLKO */
>;
+ bootph-all;
};
};
@@ -445,6 +446,7 @@ flash@0 {
cdns,tchsh-ns = <60>;
cdns,tslch-ns = <60>;
cdns,read-delay = <4>;
+ bootph-all;
};
};
--
2.45.1
^ permalink raw reply [flat|nested] 9+ messages in thread
* [PATCH v2 2/5] arm64: dts: ti: k3-j784s4*: Remove bootph properties from parent nodes
2024-07-05 6:26 [PATCH v2 0/5] Add bootph-all property for J7 boards Manorit Chawdhry
2024-07-05 6:26 ` [PATCH v2 1/5] arm64: dts: ti: k3-j721s2*: Add bootph-* properties Manorit Chawdhry
@ 2024-07-05 6:26 ` Manorit Chawdhry
2024-07-05 6:26 ` [PATCH v2 3/5] arm64: dts: ti: k3-am68*: Add bootph-* properties Manorit Chawdhry
` (3 subsequent siblings)
5 siblings, 0 replies; 9+ messages in thread
From: Manorit Chawdhry @ 2024-07-05 6:26 UTC (permalink / raw)
To: Nishanth Menon, Vignesh Raghavendra, Tero Kristo, Rob Herring,
Krzysztof Kozlowski, Conor Dooley
Cc: linux-arm-kernel, devicetree, linux-kernel, Neha Malcom Francis,
Aniket Limaye, Udit Kumar, Beleswar Padhi, Manorit Chawdhry
Removes bootph-* properties from parent nodes and aligns the bootph-* to
other u-boot.dtsi
Signed-off-by: Manorit Chawdhry <m-chawdhry@ti.com>
---
arch/arm64/boot/dts/ti/k3-j784s4-evm.dts | 9 +--------
arch/arm64/boot/dts/ti/k3-j784s4-mcu-wakeup.dtsi | 7 ++++---
2 files changed, 5 insertions(+), 11 deletions(-)
diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts b/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts
index 9338d987180d..055e3fbbacff 100644
--- a/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts
+++ b/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts
@@ -461,7 +461,6 @@ J784S4_IOPAD(0x078, PIN_OUTPUT, 1) /* (AH37) MCAN2_RX.AUDIO_EXT_REFCLK1 */
};
&wkup_pmx2 {
- bootph-all;
wkup_uart0_pins_default: wkup-uart0-default-pins {
bootph-all;
pinctrl-single,pins = <
@@ -577,7 +576,6 @@ J784S4_WKUP_IOPAD(0x028, PIN_INPUT, 7)
};
&wkup_pmx0 {
- bootph-all;
mcu_fss0_ospi0_pins_default: mcu-fss0-ospi0-default-pins {
bootph-all;
pinctrl-single,pins = <
@@ -597,7 +595,6 @@ J784S4_WKUP_IOPAD(0x008, PIN_INPUT, 0) /* (C34) MCU_OSPI0_DQS */
};
&wkup_pmx1 {
- bootph-all;
mcu_fss0_ospi0_1_pins_default: mcu-fss0-ospi0-1-default-pins {
bootph-all;
pinctrl-single,pins = <
@@ -668,6 +665,7 @@ bucka12: buck12 {
regulator-max-microvolt = <1100000>;
regulator-boot-on;
regulator-always-on;
+ bootph-pre-ram;
};
bucka3: buck3 {
@@ -769,18 +767,15 @@ &ufs_wrapper {
};
&fss {
- bootph-all;
status = "okay";
};
&ospi0 {
- bootph-all;
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&mcu_fss0_ospi0_pins_default>, <&mcu_fss0_ospi0_1_pins_default>;
flash@0 {
- bootph-all;
compatible = "jedec,spi-nor";
reg = <0x0>;
spi-tx-bus-width = <8>;
@@ -837,13 +832,11 @@ partition@3fc0000 {
};
&ospi1 {
- bootph-all;
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&mcu_fss0_ospi1_pins_default>;
flash@0 {
- bootph-all;
compatible = "jedec,spi-nor";
reg = <0x0>;
spi-tx-bus-width = <1>;
diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-mcu-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-j784s4-mcu-wakeup.dtsi
index f3a6ed1c979d..b2047828331b 100644
--- a/arch/arm64/boot/dts/ti/k3-j784s4-mcu-wakeup.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j784s4-mcu-wakeup.dtsi
@@ -39,7 +39,6 @@ k3_reset: reset-controller {
};
wkup_conf: bus@43000000 {
- bootph-all;
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
@@ -65,6 +64,7 @@ secure_proxy_sa3: mailbox@43600000 {
* firmware on non-MPU processors
*/
status = "disabled";
+ bootph-pre-ram;
};
mcu_ram: sram@41c00000 {
@@ -175,10 +175,10 @@ mcu_timer0: timer@40400000 {
ti,timer-pwm;
/* Non-MPU Firmware usage */
status = "reserved";
+ bootph-all;
};
mcu_timer1: timer@40410000 {
- bootph-all;
compatible = "ti,am654-timer";
reg = <0x00 0x40410000 0x00 0x400>;
interrupts = <GIC_SPI 817 IRQ_TYPE_LEVEL_HIGH>;
@@ -458,7 +458,6 @@ mcu_spi2: spi@40320000 {
};
mcu_navss: bus@28380000 {
- bootph-all;
compatible = "simple-bus";
#address-cells = <2>;
#size-cells = <2>;
@@ -521,6 +520,7 @@ secure_proxy_mcu: mailbox@2a480000 {
* firmware on non-MPU processors
*/
status = "disabled";
+ bootph-pre-ram;
};
mcu_cpsw: ethernet@46000000 {
@@ -632,6 +632,7 @@ wkup_vtm0: temperature-sensor@42040000 {
<0x00 0x42050000 0x00 0x350>;
power-domains = <&k3_pds 243 TI_SCI_PD_SHARED>;
#thermal-sensor-cells = <1>;
+ bootph-pre-ram;
};
tscadc0: tscadc@40200000 {
--
2.45.1
^ permalink raw reply [flat|nested] 9+ messages in thread
* [PATCH v2 3/5] arm64: dts: ti: k3-am68*: Add bootph-* properties
2024-07-05 6:26 [PATCH v2 0/5] Add bootph-all property for J7 boards Manorit Chawdhry
2024-07-05 6:26 ` [PATCH v2 1/5] arm64: dts: ti: k3-j721s2*: Add bootph-* properties Manorit Chawdhry
2024-07-05 6:26 ` [PATCH v2 2/5] arm64: dts: ti: k3-j784s4*: Remove bootph properties from parent nodes Manorit Chawdhry
@ 2024-07-05 6:26 ` Manorit Chawdhry
2024-07-05 6:26 ` [PATCH v2 4/5] arm64: dts: ti: k3-j721e*: " Manorit Chawdhry
` (2 subsequent siblings)
5 siblings, 0 replies; 9+ messages in thread
From: Manorit Chawdhry @ 2024-07-05 6:26 UTC (permalink / raw)
To: Nishanth Menon, Vignesh Raghavendra, Tero Kristo, Rob Herring,
Krzysztof Kozlowski, Conor Dooley
Cc: linux-arm-kernel, devicetree, linux-kernel, Neha Malcom Francis,
Aniket Limaye, Udit Kumar, Beleswar Padhi, Manorit Chawdhry
Adds bootph-* properties to the leaf nodes to enable U-boot to
utilise them.
Signed-off-by: Manorit Chawdhry <m-chawdhry@ti.com>
---
arch/arm64/boot/dts/ti/k3-am68-sk-base-board.dts | 10 ++++++++++
arch/arm64/boot/dts/ti/k3-am68-sk-som.dtsi | 2 ++
2 files changed, 12 insertions(+)
diff --git a/arch/arm64/boot/dts/ti/k3-am68-sk-base-board.dts b/arch/arm64/boot/dts/ti/k3-am68-sk-base-board.dts
index 90dbe31c5b81..38f146f6d8e9 100644
--- a/arch/arm64/boot/dts/ti/k3-am68-sk-base-board.dts
+++ b/arch/arm64/boot/dts/ti/k3-am68-sk-base-board.dts
@@ -184,6 +184,7 @@ main_uart8_pins_default: main-uart8-default-pins {
J721S2_IOPAD(0x0d0, PIN_INPUT, 11) /* (AF26) SPI0_CS1.UART8_RXD */
J721S2_IOPAD(0x0d4, PIN_OUTPUT, 11) /* (AH27) SPI0_CLK.UART8_TXD */
>;
+ bootph-all;
};
main_i2c0_pins_default: main-i2c0-default-pins {
@@ -210,6 +211,7 @@ J721S2_IOPAD(0x0f4, PIN_INPUT, 0) /* (R24) MMC1_DAT2 */
J721S2_IOPAD(0x0f0, PIN_INPUT, 0) /* (R22) MMC1_DAT3 */
J721S2_IOPAD(0x0e8, PIN_INPUT, 8) /* (AE25) TIMER_IO0.MMC1_SDCD */
>;
+ bootph-all;
};
vdd_sd_dv_pins_default: vdd-sd-dv-default-pins {
@@ -222,6 +224,7 @@ main_usbss0_pins_default: main-usbss0-default-pins {
pinctrl-single,pins = <
J721S2_IOPAD(0x0ec, PIN_OUTPUT, 6) /* (AG25) TIMER_IO1.USB0_DRVVBUS */
>;
+ bootph-all;
};
main_mcan6_pins_default: main-mcan6-default-pins {
@@ -312,6 +315,7 @@ J721S2_WKUP_IOPAD(0x074, PIN_OUTPUT, 0) /* (F28) WKUP_GPIO0_7.WKUP_UART0_RTSn */
J721S2_WKUP_IOPAD(0x048, PIN_INPUT, 0) /* (D28) WKUP_UART0_RXD */
J721S2_WKUP_IOPAD(0x04c, PIN_OUTPUT, 0) /* (D27) WKUP_UART0_TXD */
>;
+ bootph-all;
};
mcu_cpsw_pins_default: mcu-cpsw-default-pins {
@@ -412,6 +416,7 @@ &wkup_uart0 {
status = "reserved";
pinctrl-names = "default";
pinctrl-0 = <&wkup_uart0_pins_default>;
+ bootph-all;
};
&wkup_i2c0 {
@@ -494,6 +499,7 @@ &mcu_uart0 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&mcu_uart0_pins_default>;
+ bootph-all;
};
&main_uart8 {
@@ -502,6 +508,7 @@ &main_uart8 {
pinctrl-0 = <&main_uart8_pins_default>;
/* Shared with TFA on this platform */
power-domains = <&k3_pds 357 TI_SCI_PD_SHARED>;
+ bootph-all;
};
&main_i2c0 {
@@ -596,6 +603,7 @@ &main_sdhci1 {
disable-wp;
vmmc-supply = <&vdd_mmc1>;
vqmmc-supply = <&vdd_sd_dv>;
+ bootph-all;
};
&mcu_cpsw {
@@ -728,6 +736,7 @@ &usbss0 {
pinctrl-0 = <&main_usbss0_pins_default>;
pinctrl-names = "default";
ti,vbus-divider;
+ bootph-all;
};
&usb0 {
@@ -735,4 +744,5 @@ &usb0 {
maximum-speed = "super-speed";
phys = <&serdes0_usb_link>;
phy-names = "cdns3,usb3-phy";
+ bootph-all;
};
diff --git a/arch/arm64/boot/dts/ti/k3-am68-sk-som.dtsi b/arch/arm64/boot/dts/ti/k3-am68-sk-som.dtsi
index 5c66e0ec6e82..f2ec7ed0f2ec 100644
--- a/arch/arm64/boot/dts/ti/k3-am68-sk-som.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-am68-sk-som.dtsi
@@ -156,6 +156,7 @@ wkup_i2c0_pins_default: wkup-i2c0-default-pins {
J721S2_WKUP_IOPAD(0x098, PIN_INPUT, 0) /* (H24) WKUP_I2C0_SCL */
J721S2_WKUP_IOPAD(0x09c, PIN_INPUT, 0) /* (H27) WKUP_I2C0_SDA */
>;
+ bootph-all;
};
};
@@ -169,6 +170,7 @@ eeprom@51 {
/* AT24C512C-MAHM-T */
compatible = "atmel,24c512";
reg = <0x51>;
+ bootph-all;
};
};
--
2.45.1
^ permalink raw reply [flat|nested] 9+ messages in thread
* [PATCH v2 4/5] arm64: dts: ti: k3-j721e*: Add bootph-* properties
2024-07-05 6:26 [PATCH v2 0/5] Add bootph-all property for J7 boards Manorit Chawdhry
` (2 preceding siblings ...)
2024-07-05 6:26 ` [PATCH v2 3/5] arm64: dts: ti: k3-am68*: Add bootph-* properties Manorit Chawdhry
@ 2024-07-05 6:26 ` Manorit Chawdhry
2024-07-05 6:26 ` [PATCH v2 5/5] arm64: dts: ti: k3-j7200*: " Manorit Chawdhry
2024-07-05 10:08 ` [PATCH v2 0/5] Add bootph-all property for J7 boards Manorit Chawdhry
5 siblings, 0 replies; 9+ messages in thread
From: Manorit Chawdhry @ 2024-07-05 6:26 UTC (permalink / raw)
To: Nishanth Menon, Vignesh Raghavendra, Tero Kristo, Rob Herring,
Krzysztof Kozlowski, Conor Dooley
Cc: linux-arm-kernel, devicetree, linux-kernel, Neha Malcom Francis,
Aniket Limaye, Udit Kumar, Beleswar Padhi, Manorit Chawdhry
Adds bootph-* properties to the leaf nodes to enable U-boot to
utilise them.
Signed-off-by: Manorit Chawdhry <m-chawdhry@ti.com>
---
.../arm64/boot/dts/ti/k3-j721e-common-proc-board.dts | 20 ++++++++++++++++++++
arch/arm64/boot/dts/ti/k3-j721e-main.dtsi | 2 ++
arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi | 10 ++++++++++
arch/arm64/boot/dts/ti/k3-j721e-sk.dts | 18 ++++++++++++++++++
arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi | 5 +++++
5 files changed, 55 insertions(+)
diff --git a/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts
index 8230d53cd696..ebc9ab3b6790 100644
--- a/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts
+++ b/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts
@@ -193,6 +193,7 @@ J721E_IOPAD(0x1c0, PIN_OUTPUT, 1) /* (AA2) SPI0_CS0.UART0_RTSn */
J721E_IOPAD(0x1e8, PIN_INPUT, 0) /* (AB2) UART0_RXD */
J721E_IOPAD(0x1ec, PIN_OUTPUT, 0) /* (AB3) UART0_TXD */
>;
+ bootph-all;
};
main_uart1_pins_default: main-uart1-default-pins {
@@ -234,6 +235,7 @@ J721E_IOPAD(0x240, PIN_INPUT, 0) /* (R26) MMC1_DAT3 */
J721E_IOPAD(0x258, PIN_INPUT, 0) /* (P23) MMC1_SDCD */
J721E_IOPAD(0x25c, PIN_INPUT, 0) /* (R28) MMC1_SDWP */
>;
+ bootph-all;
};
vdd_sd_dv_alt_pins_default: vdd-sd-dv-alt-default-pins {
@@ -247,6 +249,7 @@ main_usbss0_pins_default: main-usbss0-default-pins {
J721E_IOPAD(0x290, PIN_OUTPUT, 0) /* (U6) USB0_DRVVBUS */
J721E_IOPAD(0x210, PIN_INPUT, 7) /* (W3) MCAN1_RX.GPIO1_3 */
>;
+ bootph-all;
};
main_usbss1_pins_default: main-usbss1-default-pins {
@@ -272,6 +275,7 @@ main_i2c0_pins_default: main-i2c0-default-pins {
J721E_IOPAD(0x220, PIN_INPUT_PULLUP, 0) /* (AC5) I2C0_SCL */
J721E_IOPAD(0x224, PIN_INPUT_PULLUP, 0) /* (AA5) I2C0_SDA */
>;
+ bootph-all;
};
main_i2c1_pins_default: main-i2c1-default-pins {
@@ -342,6 +346,7 @@ wkup_uart0_pins_default: wkup-uart0-default-pins {
J721E_WKUP_IOPAD(0xa0, PIN_INPUT, 0) /* (J29) WKUP_UART0_RXD */
J721E_WKUP_IOPAD(0xa4, PIN_OUTPUT, 0) /* (J28) WKUP_UART0_TXD */
>;
+ bootph-all;
};
mcu_uart0_pins_default: mcu-uart0-default-pins {
@@ -351,6 +356,7 @@ J721E_WKUP_IOPAD(0xec, PIN_OUTPUT, 0) /* (J27) WKUP_GPIO0_15.MCU_UART0_RTSn */
J721E_WKUP_IOPAD(0xe4, PIN_INPUT, 0) /* (H28) WKUP_GPIO0_13.MCU_UART0_RXD */
J721E_WKUP_IOPAD(0xe0, PIN_OUTPUT, 0) /* (G29) WKUP_GPIO0_12.MCU_UART0_TXD */
>;
+ bootph-all;
};
sw11_button_pins_default: sw11-button-default-pins {
@@ -370,6 +376,7 @@ J721E_WKUP_IOPAD(0x4c, PIN_INPUT, 0) /* (C23) MCU_OSPI1_D3 */
J721E_WKUP_IOPAD(0x3c, PIN_INPUT, 0) /* (B23) MCU_OSPI1_DQS */
J721E_WKUP_IOPAD(0x38, PIN_INPUT, 0) /* (A23) MCU_OSPI1_LBCLKO */
>;
+ bootph-all;
};
mcu_cpsw_pins_default: mcu-cpsw-default-pins {
@@ -427,6 +434,7 @@ wkup_gpio_pins_default: wkup-gpio-default-pins {
pinctrl-single,pins = <
J721E_WKUP_IOPAD(0xd0, PIN_INPUT, 7) /* (C14) WKUP_GPIO0_8 */
>;
+ bootph-all;
};
};
@@ -435,12 +443,14 @@ &wkup_uart0 {
status = "reserved";
pinctrl-names = "default";
pinctrl-0 = <&wkup_uart0_pins_default>;
+ bootph-all;
};
&mcu_uart0 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&mcu_uart0_pins_default>;
+ bootph-all;
};
&main_uart0 {
@@ -449,6 +459,7 @@ &main_uart0 {
pinctrl-0 = <&main_uart0_pins_default>;
/* Shared with ATF on this platform */
power-domains = <&k3_pds 146 TI_SCI_PD_SHARED>;
+ bootph-all;
};
&main_uart1 {
@@ -473,6 +484,7 @@ &wkup_gpio0 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&wkup_gpio_pins_default>;
+ bootph-all;
};
&main_gpio0 {
@@ -489,6 +501,7 @@ &main_sdhci0 {
non-removable;
ti,driver-strength-ohm = <50>;
disable-wp;
+ bootph-all;
};
&main_sdhci1 {
@@ -500,10 +513,12 @@ &main_sdhci1 {
pinctrl-0 = <&main_mmc1_pins_default>;
ti,driver-strength-ohm = <50>;
disable-wp;
+ bootph-all;
};
&usb_serdes_mux {
idle-states = <1>, <0>; /* USB0 to SERDES3, USB1 to SERDES1 */
+ bootph-all;
};
&serdes_ln_ctrl {
@@ -513,6 +528,7 @@ &serdes_ln_ctrl {
<J721E_SERDES3_LANE0_USB3_0_SWAP>, <J721E_SERDES3_LANE1_USB3_0>,
<J721E_SERDES4_LANE0_EDP_LANE0>, <J721E_SERDES4_LANE1_EDP_LANE1>,
<J721E_SERDES4_LANE2_EDP_LANE2>, <J721E_SERDES4_LANE3_EDP_LANE3>;
+ bootph-all;
};
&serdes_wiz3 {
@@ -534,6 +550,7 @@ &usbss0 {
pinctrl-names = "default";
pinctrl-0 = <&main_usbss0_pins_default>;
ti,vbus-divider;
+ bootph-all;
};
&usb0 {
@@ -541,6 +558,7 @@ &usb0 {
maximum-speed = "super-speed";
phys = <&serdes3_usb_link>;
phy-names = "cdns3,usb3-phy";
+ bootph-all;
};
&usbss1 {
@@ -569,6 +587,7 @@ flash@0 {
cdns,tchsh-ns = <60>;
cdns,tslch-ns = <60>;
cdns,read-delay = <2>;
+ bootph-all;
partitions {
compatible = "fixed-partitions";
@@ -650,6 +669,7 @@ exp2: gpio@22 {
reg = <0x22>;
gpio-controller;
#gpio-cells = <2>;
+ bootph-all;
p09-hog {
/* P11 - MCASP/TRACE_MUX_S0 */
diff --git a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
index 0da785be80ff..584badcb796d 100644
--- a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
@@ -226,6 +226,7 @@ secure_proxy_main: mailbox@32c00000 {
<0x00 0x32800000 0x00 0x100000>;
interrupt-names = "rx_011";
interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
+ bootph-all;
};
smmu0: iommu@36600000 {
@@ -2854,5 +2855,6 @@ main_esm: esm@700000 {
compatible = "ti,j721e-esm";
reg = <0x0 0x700000 0x0 0x1000>;
ti,esm-pins = <344>, <345>;
+ bootph-all;
};
};
diff --git a/arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi
index 6b6ef6a30614..ff9d8a7c405c 100644
--- a/arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi
@@ -17,20 +17,24 @@ dmsc: system-controller@44083000 {
reg-names = "debug_messages";
reg = <0x00 0x44083000 0x0 0x1000>;
+ bootph-all;
k3_pds: power-controller {
compatible = "ti,sci-pm-domain";
#power-domain-cells = <2>;
+ bootph-all;
};
k3_clks: clock-controller {
compatible = "ti,k2g-sci-clk";
#clock-cells = <2>;
+ bootph-all;
};
k3_reset: reset-controller {
compatible = "ti,sci-reset";
#reset-cells = <2>;
+ bootph-all;
};
};
@@ -61,6 +65,7 @@ wkup_conf: bus@43000000 {
chipid: chipid@14 {
compatible = "ti,am654-chipid";
reg = <0x14 0x4>;
+ bootph-all;
};
};
@@ -115,6 +120,7 @@ mcu_timer0: timer@40400000 {
ti,timer-pwm;
/* Non-MPU Firmware usage */
status = "reserved";
+ bootph-pre-ram;
};
mcu_timer1: timer@40410000 {
@@ -475,6 +481,7 @@ mcu_ringacc: ringacc@2b800000 {
ti,sci = <&dmsc>;
ti,sci-dev-id = <235>;
msi-parent = <&main_udmass_inta>;
+ bootph-all;
};
mcu_udmap: dma-controller@285c0000 {
@@ -499,6 +506,7 @@ mcu_udmap: dma-controller@285c0000 {
ti,sci-rm-range-rchan = <0x0a>, /* RX_CHAN */
<0x0b>; /* RX_HCHAN */
ti,sci-rm-range-rflow = <0x00>; /* GP RFLOW */
+ bootph-all;
};
};
@@ -515,6 +523,7 @@ secure_proxy_mcu: mailbox@2a480000 {
* firmware on non-MPU processors
*/
status = "disabled";
+ bootph-pre-ram;
};
mcu_cpsw: ethernet@46000000 {
@@ -687,6 +696,7 @@ wkup_vtm0: temperature-sensor@42040000 {
<0x00 0x43000300 0x00 0x10>;
power-domains = <&k3_pds 154 TI_SCI_PD_EXCLUSIVE>;
#thermal-sensor-cells = <1>;
+ bootph-pre-ram;
};
mcu_esm: esm@40800000 {
diff --git a/arch/arm64/boot/dts/ti/k3-j721e-sk.dts b/arch/arm64/boot/dts/ti/k3-j721e-sk.dts
index 89fbfb21e5d3..b63d48719090 100644
--- a/arch/arm64/boot/dts/ti/k3-j721e-sk.dts
+++ b/arch/arm64/boot/dts/ti/k3-j721e-sk.dts
@@ -346,6 +346,7 @@ J721E_IOPAD(0x244, PIN_INPUT, 0) /* (R25) MMC1_DAT2 */
J721E_IOPAD(0x240, PIN_INPUT, 0) /* (R26) MMC1_DAT3 */
J721E_IOPAD(0x258, PIN_INPUT, 0) /* (P23) MMC1_SDCD */
>;
+ bootph-all;
};
main_uart0_pins_default: main-uart0-default-pins {
@@ -355,6 +356,7 @@ J721E_IOPAD(0x1f4, PIN_OUTPUT, 0) /* (AB1) UART0_RTSn */
J721E_IOPAD(0x1e8, PIN_INPUT, 0) /* (AB2) UART0_RXD */
J721E_IOPAD(0x1ec, PIN_OUTPUT, 0) /* (AB3) UART0_TXD */
>;
+ bootph-all;
};
main_uart1_pins_default: main-uart1-default-pins {
@@ -390,12 +392,14 @@ main_usbss0_pins_default: main-usbss0-default-pins {
J721E_IOPAD(0x290, PIN_OUTPUT, 0) /* (U6) USB0_DRVVBUS */
J721E_IOPAD(0x210, PIN_INPUT, 7) /* (W3) MCAN1_RX.GPIO1_3 */
>;
+ bootph-all;
};
main_usbss1_pins_default: main-usbss1-default-pins {
pinctrl-single,pins = <
J721E_IOPAD(0x214, PIN_OUTPUT, 4) /* (V4) MCAN1_TX.USB1_DRVVBUS */
>;
+ bootph-all;
};
main_csi_mux_sel_pins_default: main-csi-mux-sel-default-pins {
@@ -594,6 +598,7 @@ J721E_WKUP_IOPAD(0x24, PIN_INPUT, 0) /* (B22) MCU_OSPI0_D6 */
J721E_WKUP_IOPAD(0x28, PIN_INPUT, 0) /* (G21) MCU_OSPI0_D7 */
J721E_WKUP_IOPAD(0x8, PIN_INPUT, 0) /* (D21) MCU_OSPI0_DQS */
>;
+ bootph-all;
};
vdd_mmc1_en_pins_default: vdd-mmc1-en-default-pins {
@@ -622,6 +627,7 @@ J721E_WKUP_IOPAD(0xf4, PIN_OUTPUT, 2)/* (D25) MCU_I3C0_SDA.MCU_UART0_RTSn */
J721E_WKUP_IOPAD(0xe4, PIN_INPUT, 0) /* (H28) WKUP_GPIO0_13.MCU_UART0_RXD */
J721E_WKUP_IOPAD(0xe0, PIN_OUTPUT, 0)/* (G29) WKUP_GPIO0_12.MCU_UART0_TXD */
>;
+ bootph-pre-ram;
};
wkup_i2c0_pins_default: wkup-i2c0-default-pins {
@@ -629,6 +635,7 @@ wkup_i2c0_pins_default: wkup-i2c0-default-pins {
J721E_WKUP_IOPAD(0xf8, PIN_INPUT_PULLUP, 0) /* (J25) WKUP_I2C0_SCL */
J721E_WKUP_IOPAD(0xfc, PIN_INPUT_PULLUP, 0) /* (H24) WKUP_I2C0_SDA */
>;
+ bootph-all;
};
mcu_mcan0_pins_default: mcu-mcan0-default-pins {
@@ -657,6 +664,7 @@ &wkup_uart0 {
status = "reserved";
pinctrl-names = "default";
pinctrl-0 = <&wkup_uart0_pins_default>;
+ bootph-all;
};
&wkup_i2c0 {
@@ -821,6 +829,7 @@ &mcu_uart0 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&mcu_uart0_pins_default>;
+ bootph-all;
};
&main_uart0 {
@@ -829,6 +838,7 @@ &main_uart0 {
pinctrl-0 = <&main_uart0_pins_default>;
/* Shared with ATF on this platform */
power-domains = <&k3_pds 146 TI_SCI_PD_SHARED>;
+ bootph-all;
};
&main_uart1 {
@@ -846,6 +856,7 @@ &main_sdhci1 {
pinctrl-0 = <&main_mmc1_pins_default>;
ti,driver-strength-ohm = <50>;
disable-wp;
+ bootph-all;
};
&ospi0 {
@@ -864,6 +875,7 @@ flash@0 {
cdns,tchsh-ns = <60>;
cdns,tslch-ns = <60>;
cdns,read-delay = <4>;
+ bootph-all;
partitions {
compatible = "fixed-partitions";
@@ -1003,6 +1015,7 @@ &wkup_gpio0 {
&usb_serdes_mux {
idle-states = <1>, <1>; /* USB0 to SERDES3, USB1 to SERDES2 */
+ bootph-all;
};
&serdes_ln_ctrl {
@@ -1012,6 +1025,7 @@ &serdes_ln_ctrl {
<J721E_SERDES3_LANE0_USB3_0_SWAP>, <J721E_SERDES3_LANE1_USB3_0>,
<J721E_SERDES4_LANE0_EDP_LANE0>, <J721E_SERDES4_LANE1_EDP_LANE1>,
<J721E_SERDES4_LANE2_EDP_LANE2>, <J721E_SERDES4_LANE3_EDP_LANE3>;
+ bootph-all;
};
&serdes_wiz3 {
@@ -1051,6 +1065,7 @@ &usbss0 {
pinctrl-names = "default";
pinctrl-0 = <&main_usbss0_pins_default>;
ti,vbus-divider;
+ bootph-all;
};
&usb0 {
@@ -1058,6 +1073,7 @@ &usb0 {
maximum-speed = "super-speed";
phys = <&serdes3_usb_link>;
phy-names = "cdns3,usb3-phy";
+ bootph-all;
};
&serdes2 {
@@ -1074,6 +1090,7 @@ &usbss1 {
pinctrl-names = "default";
pinctrl-0 = <&main_usbss1_pins_default>;
ti,vbus-divider;
+ bootph-all;
};
&usb1 {
@@ -1081,6 +1098,7 @@ &usb1 {
maximum-speed = "super-speed";
phys = <&serdes2_usb_link>;
phy-names = "cdns3,usb3-phy";
+ bootph-all;
};
&mcu_cpsw {
diff --git a/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi
index 5ba947771b84..86bfc5e21eed 100644
--- a/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi
@@ -151,6 +151,7 @@ wkup_i2c0_pins_default: wkup-i2c0-default-pins {
J721E_WKUP_IOPAD(0xf8, PIN_INPUT_PULLUP, 0) /* (J25) WKUP_I2C0_SCL */
J721E_WKUP_IOPAD(0xfc, PIN_INPUT_PULLUP, 0) /* (H24) WKUP_I2C0_SDA */
>;
+ bootph-all;
};
pmic_irq_pins_default: pmic-irq-default-pins {
@@ -173,6 +174,7 @@ J721E_WKUP_IOPAD(0x0024, PIN_INPUT, 0) /* MCU_OSPI0_D6 */
J721E_WKUP_IOPAD(0x0028, PIN_INPUT, 0) /* MCU_OSPI0_D7 */
J721E_WKUP_IOPAD(0x002c, PIN_OUTPUT, 0) /* MCU_OSPI0_CSn0 */
>;
+ bootph-all;
};
mcu_fss0_hpb0_pins_default: mcu-fss0-hpb0-default-pins {
@@ -192,6 +194,7 @@ J721E_WKUP_IOPAD(0x20, PIN_INPUT, 1) /* MCU_HYPERBUS0_DQ5 */
J721E_WKUP_IOPAD(0x24, PIN_INPUT, 1) /* MCU_HYPERBUS0_DQ6 */
J721E_WKUP_IOPAD(0x28, PIN_INPUT, 1) /* MCU_HYPERBUS0_DQ7 */
>;
+ bootph-all;
};
};
@@ -378,6 +381,7 @@ flash@0 {
cdns,tchsh-ns = <60>;
cdns,tslch-ns = <60>;
cdns,read-delay = <0>;
+ bootph-all;
partitions {
compatible = "fixed-partitions";
@@ -440,6 +444,7 @@ &hbmc {
flash@0,0 {
compatible = "cypress,hyperflash", "cfi-flash";
reg = <0x00 0x00 0x4000000>;
+ bootph-all;
partitions {
compatible = "fixed-partitions";
--
2.45.1
^ permalink raw reply [flat|nested] 9+ messages in thread
* [PATCH v2 5/5] arm64: dts: ti: k3-j7200*: Add bootph-* properties
2024-07-05 6:26 [PATCH v2 0/5] Add bootph-all property for J7 boards Manorit Chawdhry
` (3 preceding siblings ...)
2024-07-05 6:26 ` [PATCH v2 4/5] arm64: dts: ti: k3-j721e*: " Manorit Chawdhry
@ 2024-07-05 6:26 ` Manorit Chawdhry
2024-07-05 10:08 ` [PATCH v2 0/5] Add bootph-all property for J7 boards Manorit Chawdhry
5 siblings, 0 replies; 9+ messages in thread
From: Manorit Chawdhry @ 2024-07-05 6:26 UTC (permalink / raw)
To: Nishanth Menon, Vignesh Raghavendra, Tero Kristo, Rob Herring,
Krzysztof Kozlowski, Conor Dooley
Cc: linux-arm-kernel, devicetree, linux-kernel, Neha Malcom Francis,
Aniket Limaye, Udit Kumar, Beleswar Padhi, Manorit Chawdhry
Adds bootph-* properties to the leaf nodes to enable U-boot to
utilise them.
Signed-off-by: Manorit Chawdhry <m-chawdhry@ti.com>
---
.../boot/dts/ti/k3-j7200-common-proc-board.dts | 23 ++++++++++++++++++++++
arch/arm64/boot/dts/ti/k3-j7200-main.dtsi | 2 ++
arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi | 11 +++++++++++
arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi | 7 +++++++
4 files changed, 43 insertions(+)
diff --git a/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts
index 6593c5da82c0..f7b96e8d6462 100644
--- a/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts
+++ b/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts
@@ -129,6 +129,7 @@ J721E_WKUP_IOPAD(0x94, PIN_OUTPUT, 0) /* (E21) MCU_UART0_RTSn */
J721E_WKUP_IOPAD(0x8c, PIN_INPUT, 0) /* (D20) MCU_UART0_RXD */
J721E_WKUP_IOPAD(0x88, PIN_OUTPUT, 0) /* (D19) MCU_UART0_TXD */
>;
+ bootph-all;
};
wkup_uart0_pins_default: wkup-uart0-default-pins {
@@ -136,6 +137,7 @@ wkup_uart0_pins_default: wkup-uart0-default-pins {
J721E_WKUP_IOPAD(0x48, PIN_INPUT, 0) /* (B14) WKUP_UART0_RXD */
J721E_WKUP_IOPAD(0x4c, PIN_OUTPUT, 0) /* (A14) WKUP_UART0_TXD */
>;
+ bootph-all;
};
mcu_cpsw_pins_default: mcu-cpsw-default-pins {
@@ -153,12 +155,14 @@ J721E_WKUP_IOPAD(0x002c, PIN_INPUT, 0) /* MCU_RGMII1_RD0 */
J721E_WKUP_IOPAD(0x0018, PIN_OUTPUT, 0) /* MCU_RGMII1_TXC */
J721E_WKUP_IOPAD(0x001c, PIN_INPUT, 0) /* MCU_RGMII1_RXC */
>;
+ bootph-all;
};
wkup_gpio_pins_default: wkup-gpio-default-pins {
pinctrl-single,pins = <
J721E_WKUP_IOPAD(0x70, PIN_INPUT, 7) /* (C14) WKUP_GPIO0_6 */
>;
+ bootph-all;
};
mcu_mdio_pins_default: mcu-mdio1-default-pins {
@@ -204,6 +208,7 @@ J721E_IOPAD(0xb4, PIN_OUTPUT, 0) /* (T17) UART0_TXD */
J721E_IOPAD(0xc0, PIN_INPUT, 2) /* (W3) SPI0_CS0.UART0_CTSn */
J721E_IOPAD(0xc4, PIN_OUTPUT, 2) /* (U5) SPI0_CS1.UART0_RTSn */
>;
+ bootph-all;
};
main_uart1_pins_default: main-uart1-default-pins {
@@ -238,6 +243,7 @@ J721E_IOPAD(0xf0, PIN_INPUT, 0) /* (N20) MMC1_DAT2 */
J721E_IOPAD(0xec, PIN_INPUT, 0) /* (N19) MMC1_DAT3 */
J721E_IOPAD(0xe4, PIN_INPUT, 8) /* (V1) TIMER_IO0.MMC1_SDCD */
>;
+ bootph-all;
};
vdd_sd_dv_pins_default: vdd-sd-dv-default-pins {
@@ -259,6 +265,7 @@ main_usbss0_pins_default: main-usbss0-default-pins {
pinctrl-single,pins = <
J721E_IOPAD(0x04, PIN_OUTPUT, 0) /* (T4) USB0_DRVVBUS */
>;
+ bootph-all;
};
};
@@ -267,12 +274,14 @@ &wkup_uart0 {
status = "reserved";
pinctrl-names = "default";
pinctrl-0 = <&wkup_uart0_pins_default>;
+ bootph-all;
};
&mcu_uart0 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&mcu_uart0_pins_default>;
+ bootph-all;
};
&main_uart0 {
@@ -281,6 +290,7 @@ &main_uart0 {
power-domains = <&k3_pds 146 TI_SCI_PD_SHARED>;
pinctrl-names = "default";
pinctrl-0 = <&main_uart0_pins_default>;
+ bootph-all;
};
&main_uart1 {
@@ -293,6 +303,7 @@ &main_uart1 {
&main_uart2 {
/* MAIN UART 2 is used by R5F firmware */
status = "reserved";
+ bootph-all; /* Doubtful if required or not */
};
&main_uart3 {
@@ -310,11 +321,13 @@ &wkup_gpio0 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&wkup_gpio_pins_default>;
+ bootph-all;
};
&mcu_cpsw {
pinctrl-names = "default";
pinctrl-0 = <&mcu_cpsw_pins_default>, <&mcu_mdio_pins_default>;
+ bootph-all;
};
&davinci_mdio {
@@ -341,6 +354,7 @@ exp1: gpio@20 {
reg = <0x20>;
gpio-controller;
#gpio-cells = <2>;
+ bootph-all;
};
exp2: gpio@22 {
@@ -348,6 +362,7 @@ exp2: gpio@22 {
reg = <0x22>;
gpio-controller;
#gpio-cells = <2>;
+ bootph-all;
};
};
@@ -381,6 +396,7 @@ &main_sdhci0 {
non-removable;
ti,driver-strength-ohm = <50>;
disable-wp;
+ bootph-all;
};
&main_sdhci1 {
@@ -392,15 +408,18 @@ &main_sdhci1 {
vqmmc-supply = <&vdd_sd_dv>;
ti,driver-strength-ohm = <50>;
disable-wp;
+ bootph-all;
};
&serdes_ln_ctrl {
idle-states = <J7200_SERDES0_LANE0_PCIE1_LANE0>, <J7200_SERDES0_LANE1_PCIE1_LANE1>,
<J7200_SERDES0_LANE2_QSGMII_LANE1>, <J7200_SERDES0_LANE3_IP4_UNUSED>;
+ bootph-all;
};
&usb_serdes_mux {
idle-states = <1>; /* USB0 to SERDES lane 3 */
+ bootph-all;
};
&usbss0 {
@@ -408,11 +427,13 @@ &usbss0 {
pinctrl-0 = <&main_usbss0_pins_default>;
ti,vbus-divider;
ti,usb2-only;
+ bootph-all;
};
&usb0 {
dr_mode = "otg";
maximum-speed = "high-speed";
+ bootph-all;
};
&tscadc0 {
@@ -432,6 +453,7 @@ serdes0_pcie_link: phy@0 {
#phy-cells = <0>;
cdns,phy-type = <PHY_TYPE_PCIE>;
resets = <&serdes_wiz0 1>, <&serdes_wiz0 2>;
+ bootph-all;
};
serdes0_qsgmii_link: phy@1 {
@@ -440,6 +462,7 @@ serdes0_qsgmii_link: phy@1 {
#phy-cells = <0>;
cdns,phy-type = <PHY_TYPE_QSGMII>;
resets = <&serdes_wiz0 3>;
+ bootph-all;
};
};
diff --git a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi
index 9386bf3ef9f6..b95656942412 100644
--- a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi
@@ -136,6 +136,7 @@ secure_proxy_main: mailbox@32c00000 {
<0x00 0x32800000 0x00 0x100000>;
interrupt-names = "rx_011";
interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
+ bootph-all;
};
hwspinlock: spinlock@30e00000 {
@@ -1528,5 +1529,6 @@ main_esm: esm@700000 {
compatible = "ti,j721e-esm";
reg = <0x0 0x700000 0x0 0x1000>;
ti,esm-pins = <656>, <657>;
+ bootph-all;
};
};
diff --git a/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi
index 5097d192c2b2..fba8fa1557b1 100644
--- a/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi
@@ -17,20 +17,24 @@ dmsc: system-controller@44083000 {
reg-names = "debug_messages";
reg = <0x00 0x44083000 0x00 0x1000>;
+ bootph-all;
k3_pds: power-controller {
compatible = "ti,sci-pm-domain";
#power-domain-cells = <2>;
+ bootph-all;
};
k3_clks: clock-controller {
compatible = "ti,k2g-sci-clk";
#clock-cells = <2>;
+ bootph-all;
};
k3_reset: reset-controller {
compatible = "ti,sci-reset";
#reset-cells = <2>;
+ bootph-all;
};
};
@@ -45,6 +49,7 @@ mcu_timer0: timer@40400000 {
assigned-clock-parents = <&k3_clks 35 2>;
power-domains = <&k3_pds 35 TI_SCI_PD_EXCLUSIVE>;
ti,timer-pwm;
+ bootph-pre-ram;
};
mcu_timer1: timer@40410000 {
@@ -191,6 +196,7 @@ wkup_conf: bus@43000000 {
chipid: chipid@14 {
compatible = "ti,am654-chipid";
reg = <0x14 0x4>;
+ bootph-all;
};
};
@@ -349,6 +355,7 @@ mcu_ringacc: ringacc@2b800000 {
ti,sci = <&dmsc>;
ti,sci-dev-id = <235>;
msi-parent = <&main_udmass_inta>;
+ bootph-all;
};
mcu_udmap: dma-controller@285c0000 {
@@ -373,6 +380,7 @@ mcu_udmap: dma-controller@285c0000 {
ti,sci-rm-range-rchan = <0x0a>, /* RX_CHAN */
<0x0b>; /* RX_HCHAN */
ti,sci-rm-range-rflow = <0x00>; /* GP RFLOW */
+ bootph-all;
};
};
@@ -389,6 +397,7 @@ secure_proxy_mcu: mailbox@2a480000 {
* firmware on non-MPU processors
*/
status = "disabled";
+ bootph-pre-ram;
};
mcu_cpsw: ethernet@46000000 {
@@ -534,6 +543,7 @@ hbmc_mux: mux-controller@47000004 {
reg = <0x00 0x47000004 0x00 0x4>;
#mux-control-cells = <1>;
mux-reg-masks = <0x0 0x2>; /* HBMC select */
+ bootph-pre-ram;
};
hbmc: hyperbus@47034000 {
@@ -652,6 +662,7 @@ wkup_vtm0: temperature-sensor@42040000 {
<0x00 0x42050000 0x00 0x350>;
power-domains = <&k3_pds 154 TI_SCI_PD_EXCLUSIVE>;
#thermal-sensor-cells = <1>;
+ bootph-pre-ram;
};
mcu_esm: esm@40800000 {
diff --git a/arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi b/arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi
index 21fe194a5766..d78f86889bf9 100644
--- a/arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi
@@ -121,6 +121,7 @@ J721E_WKUP_IOPAD(0x20, PIN_INPUT, 1) /* (B8) MCU_OSPI0_D5.MCU_HYPERBUS0_DQ5 */
J721E_WKUP_IOPAD(0x24, PIN_INPUT, 1) /* (A8) MCU_OSPI0_D6.MCU_HYPERBUS0_DQ6 */
J721E_WKUP_IOPAD(0x28, PIN_INPUT, 1) /* (A7) MCU_OSPI0_D7.MCU_HYPERBUS0_DQ7 */
>;
+ bootph-all;
};
mcu_fss0_ospi0_pins_default: mcu-fss0-ospi0-default-pins {
@@ -137,6 +138,7 @@ J721E_WKUP_IOPAD(0x0024, PIN_INPUT, 0) /* MCU_OSPI0_D6 */
J721E_WKUP_IOPAD(0x0028, PIN_INPUT, 0) /* MCU_OSPI0_D7 */
J721E_WKUP_IOPAD(0x0008, PIN_INPUT, 0) /* MCU_OSPI0_DQS */
>;
+ bootph-all;
};
};
@@ -146,6 +148,7 @@ wkup_i2c0_pins_default: wkup-i2c0-default-pins {
J721E_WKUP_IOPAD(0x98, PIN_INPUT_PULLUP, 0) /* (F20) WKUP_I2C0_SCL */
J721E_WKUP_IOPAD(0x9c, PIN_INPUT_PULLUP, 0) /* (H21) WKUP_I2C0_SDA */
>;
+ bootph-all;
};
};
@@ -163,6 +166,7 @@ main_i2c0_pins_default: main-i2c0-default-pins {
J721E_IOPAD(0xd4, PIN_INPUT_PULLUP, 0) /* (V3) I2C0_SCL */
J721E_IOPAD(0xd8, PIN_INPUT_PULLUP, 0) /* (W2) I2C0_SDA */
>;
+ bootph-all;
};
main_mcan0_pins_default: main-mcan0-default-pins {
@@ -186,6 +190,7 @@ &hbmc {
flash@0,0 {
compatible = "cypress,hyperflash", "cfi-flash";
reg = <0x00 0x00 0x4000000>;
+ bootph-all;
partitions {
compatible = "fixed-partitions";
@@ -330,6 +335,7 @@ bucka1: buck1 {
regulator-max-microvolt = <1800000>;
regulator-boot-on;
regulator-always-on;
+ bootph-all;
};
bucka2: buck2 {
@@ -464,6 +470,7 @@ flash@0 {
cdns,tchsh-ns = <60>;
cdns,tslch-ns = <60>;
cdns,read-delay = <4>;
+ bootph-all;
partitions {
compatible = "fixed-partitions";
--
2.45.1
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH v2 0/5] Add bootph-all property for J7 boards
2024-07-05 6:26 [PATCH v2 0/5] Add bootph-all property for J7 boards Manorit Chawdhry
` (4 preceding siblings ...)
2024-07-05 6:26 ` [PATCH v2 5/5] arm64: dts: ti: k3-j7200*: " Manorit Chawdhry
@ 2024-07-05 10:08 ` Manorit Chawdhry
5 siblings, 0 replies; 9+ messages in thread
From: Manorit Chawdhry @ 2024-07-05 10:08 UTC (permalink / raw)
To: Nishanth Menon, Vignesh Raghavendra, Tero Kristo, Rob Herring,
Krzysztof Kozlowski, Conor Dooley
Cc: linux-arm-kernel, devicetree, linux-kernel, Neha Malcom Francis,
Aniket Limaye, Udit Kumar, Beleswar Padhi
Hi all,
On 11:56-20240705, Manorit Chawdhry wrote:
> The idea of this series is to add bootph-all and bootph-pre-ram property
> in all the leaf nodes wherever required and cleanup any other places where
> bootph-all/bootph-pre-ram exist in the parent nodes as well.
>
> Signed-off-by: Manorit Chawdhry <m-chawdhry@ti.com>
> ---
> Changes in v2:
>
> * Aniket
> - Change wkup_vtm0 bootph-all to bootph-pre-ram
> - Add bootph-all explicitly to dmsc/sms nodes as otherwise the boards
> don't boot
>
> - Cleanup more nodes along with some testing with u-boot.
Here is the u-boot patch with the cleanup that I have tried [0] and here
is the corresponding boot log for that [1].
[0]: https://github.com/manorit2001/u-boot/tree/b4/upstream/j7/remove-bootph
[1]: https://gist.github.com/manorit2001/da42b634fabb662a48728927cdcb1acc
Regards,
Manorit
> - Fix build errors
> - Link to v1: https://lore.kernel.org/r/20240507-b4-upstream-bootph-all-v1-0-c6d52651856f@ti.com
>
> ---
> Manorit Chawdhry (5):
> arm64: dts: ti: k3-j721s2*: Add bootph-* properties
> arm64: dts: ti: k3-j784s4*: Remove bootph properties from parent nodes
> arm64: dts: ti: k3-am68*: Add bootph-* properties
> arm64: dts: ti: k3-j721e*: Add bootph-* properties
> arm64: dts: ti: k3-j7200*: Add bootph-* properties
>
> arch/arm64/boot/dts/ti/k3-am68-sk-base-board.dts | 10 ++++++++++
> arch/arm64/boot/dts/ti/k3-am68-sk-som.dtsi | 2 ++
> .../boot/dts/ti/k3-j7200-common-proc-board.dts | 23 ++++++++++++++++++++++
> arch/arm64/boot/dts/ti/k3-j7200-main.dtsi | 2 ++
> arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi | 11 +++++++++++
> arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi | 7 +++++++
> .../boot/dts/ti/k3-j721e-common-proc-board.dts | 20 +++++++++++++++++++
> arch/arm64/boot/dts/ti/k3-j721e-main.dtsi | 2 ++
> arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi | 10 ++++++++++
> arch/arm64/boot/dts/ti/k3-j721e-sk.dts | 18 +++++++++++++++++
> arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi | 5 +++++
> .../boot/dts/ti/k3-j721s2-common-proc-board.dts | 14 +++++++++++++
> arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi | 2 ++
> arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi | 12 +++++++++++
> arch/arm64/boot/dts/ti/k3-j721s2-som-p0.dtsi | 2 ++
> arch/arm64/boot/dts/ti/k3-j784s4-evm.dts | 9 +--------
> arch/arm64/boot/dts/ti/k3-j784s4-mcu-wakeup.dtsi | 7 ++++---
> 17 files changed, 145 insertions(+), 11 deletions(-)
> ---
> base-commit: 0b58e108042b0ed28a71cd7edf5175999955b233
> change-id: 20240430-b4-upstream-bootph-all-8d47b72bc0fd
>
> Best regards,
> --
> Manorit Chawdhry <m-chawdhry@ti.com>
>
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH v2 1/5] arm64: dts: ti: k3-j721s2*: Add bootph-* properties
2024-07-05 6:26 ` [PATCH v2 1/5] arm64: dts: ti: k3-j721s2*: Add bootph-* properties Manorit Chawdhry
@ 2024-07-09 7:32 ` Vignesh Raghavendra
2024-07-09 8:48 ` Manorit Chawdhry
0 siblings, 1 reply; 9+ messages in thread
From: Vignesh Raghavendra @ 2024-07-09 7:32 UTC (permalink / raw)
To: Manorit Chawdhry, Nishanth Menon, Tero Kristo, Rob Herring,
Krzysztof Kozlowski, Conor Dooley
Cc: linux-arm-kernel, devicetree, linux-kernel, Neha Malcom Francis,
Aniket Limaye, Udit Kumar, Beleswar Padhi
On 05/07/24 11:56, Manorit Chawdhry wrote:
> diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi
> index 8feb42c89e47..497e0dfa8011 100644
> --- a/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi
> +++ b/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi
> @@ -17,20 +17,24 @@ sms: system-controller@44083000 {
>
> reg-names = "debug_messages";
> reg = <0x00 0x44083000 0x00 0x1000>;
> + bootph-all;
Since [0] in U-Boot, bootph-* is automatically propagated to supernodes.
Please fix throughout the series
>
> k3_pds: power-controller {
> compatible = "ti,sci-pm-domain";
> #power-domain-cells = <2>;
> + bootph-all;
> };
>
> k3_clks: clock-controller {
> compatible = "ti,k2g-sci-clk";
> #clock-cells = <2>;
> + bootph-all;
> };
>
> k3_reset: reset-controller {
> compatible = "ti,sci-reset";
> #reset-cells = <2>;
> + bootph-all;
> };
> };
[0]
--
Regards
Vignesh
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH v2 1/5] arm64: dts: ti: k3-j721s2*: Add bootph-* properties
2024-07-09 7:32 ` Vignesh Raghavendra
@ 2024-07-09 8:48 ` Manorit Chawdhry
0 siblings, 0 replies; 9+ messages in thread
From: Manorit Chawdhry @ 2024-07-09 8:48 UTC (permalink / raw)
To: Vignesh Raghavendra
Cc: Nishanth Menon, Tero Kristo, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, linux-arm-kernel, devicetree, linux-kernel,
Neha Malcom Francis, Aniket Limaye, Udit Kumar, Beleswar Padhi
Hi Vignesh,
On 13:02-20240709, Vignesh Raghavendra wrote:
>
>
> On 05/07/24 11:56, Manorit Chawdhry wrote:
> > diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi
> > index 8feb42c89e47..497e0dfa8011 100644
> > --- a/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi
> > +++ b/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi
> > @@ -17,20 +17,24 @@ sms: system-controller@44083000 {
> >
> > reg-names = "debug_messages";
> > reg = <0x00 0x44083000 0x00 0x1000>;
> > + bootph-all;
>
> Since [0] in U-Boot, bootph-* is automatically propagated to supernodes.
> Please fix throughout the series
In v1, Aniket posted a review comment and that corresponded to all the
devices hence added that [0]. As you mentioned offline, this node might
be getting called in U-boot proper prior to re-location and somehow the
property is not getting passed on at that stage. Might need some furthur
debugging as to why it's failing. Will see what can be done about it.
Thanks.
[0]: https://lore.kernel.org/all/3e478ecc-33b8-4aa6-b984-67877864e900@ti.com/
Regards,
Manorit
>
> >
> > k3_pds: power-controller {
> > compatible = "ti,sci-pm-domain";
> > #power-domain-cells = <2>;
> > + bootph-all;
> > };
> >
> > k3_clks: clock-controller {
> > compatible = "ti,k2g-sci-clk";
> > #clock-cells = <2>;
> > + bootph-all;
> > };
> >
> > k3_reset: reset-controller {
> > compatible = "ti,sci-reset";
> > #reset-cells = <2>;
> > + bootph-all;
> > };
> > };
>
>
> [0]
>
> --
> Regards
> Vignesh
^ permalink raw reply [flat|nested] 9+ messages in thread
end of thread, other threads:[~2024-07-09 8:49 UTC | newest]
Thread overview: 9+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2024-07-05 6:26 [PATCH v2 0/5] Add bootph-all property for J7 boards Manorit Chawdhry
2024-07-05 6:26 ` [PATCH v2 1/5] arm64: dts: ti: k3-j721s2*: Add bootph-* properties Manorit Chawdhry
2024-07-09 7:32 ` Vignesh Raghavendra
2024-07-09 8:48 ` Manorit Chawdhry
2024-07-05 6:26 ` [PATCH v2 2/5] arm64: dts: ti: k3-j784s4*: Remove bootph properties from parent nodes Manorit Chawdhry
2024-07-05 6:26 ` [PATCH v2 3/5] arm64: dts: ti: k3-am68*: Add bootph-* properties Manorit Chawdhry
2024-07-05 6:26 ` [PATCH v2 4/5] arm64: dts: ti: k3-j721e*: " Manorit Chawdhry
2024-07-05 6:26 ` [PATCH v2 5/5] arm64: dts: ti: k3-j7200*: " Manorit Chawdhry
2024-07-05 10:08 ` [PATCH v2 0/5] Add bootph-all property for J7 boards Manorit Chawdhry
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