* Purpose of PCI address in ranges property
@ 2017-03-19 14:14 valmiki
2017-03-19 21:45 ` Arnd Bergmann
0 siblings, 1 reply; 4+ messages in thread
From: valmiki @ 2017-03-19 14:14 UTC (permalink / raw)
To: linux-kernel, linux-pci; +Cc: helgaas, marc.zyngier, arnd
Hi,
When ranges property is being parsed using
of_pci_get_host_bridge_resources, the pci address is being used for
calculating the offset for pci_add_resource_offset.
What is this offset for ?
So the cpu address is being used for programming memory base and limit
registers ?
Thanks & Regards,
Valmiki
^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: Purpose of PCI address in ranges property
2017-03-19 14:14 Purpose of PCI address in ranges property valmiki
@ 2017-03-19 21:45 ` Arnd Bergmann
2017-03-23 2:59 ` valmiki
0 siblings, 1 reply; 4+ messages in thread
From: Arnd Bergmann @ 2017-03-19 21:45 UTC (permalink / raw)
To: valmiki; +Cc: Linux Kernel Mailing List, linux-pci, Bjorn Helgaas, Marc Zyngier
On Sun, Mar 19, 2017 at 3:14 PM, valmiki <valmikibow@gmail.com> wrote:
> Hi,
>
> When ranges property is being parsed using of_pci_get_host_bridge_resources,
> the pci address is being used for
> calculating the offset for pci_add_resource_offset.
>
> What is this offset for ?
>
> So the cpu address is being used for programming memory base and limit
> registers ?
Linux IORESOURCE_MEM resources are defined in terms of CPU addresses,
while PCI config space BAR registers are programmed with bus addresses.
These are often the same, but on some machines they are not, which results
in an offset that has to be used when accessing the BARs.
Arnd
^ permalink raw reply [flat|nested] 4+ messages in thread* Re: Purpose of PCI address in ranges property
2017-03-19 21:45 ` Arnd Bergmann
@ 2017-03-23 2:59 ` valmiki
2017-03-23 14:11 ` Arnd Bergmann
0 siblings, 1 reply; 4+ messages in thread
From: valmiki @ 2017-03-23 2:59 UTC (permalink / raw)
To: Arnd Bergmann
Cc: Linux Kernel Mailing List, linux-pci, Bjorn Helgaas, Marc Zyngier
On 3/20/2017 3:15 AM, Arnd Bergmann wrote:
> On Sun, Mar 19, 2017 at 3:14 PM, valmiki <valmikibow@gmail.com> wrote:
>> Hi,
>>
>> When ranges property is being parsed using of_pci_get_host_bridge_resources,
>> the pci address is being used for
>> calculating the offset for pci_add_resource_offset.
>>
>> What is this offset for ?
>>
>> So the cpu address is being used for programming memory base and limit
>> registers ?
>
> Linux IORESOURCE_MEM resources are defined in terms of CPU addresses,
> while PCI config space BAR registers are programmed with bus addresses.
> These are often the same, but on some machines they are not, which results
> in an offset that has to be used when accessing the BARs.
>
Thanks Arnd. So mem base and limit registers of RP are programmed with
CPU addresses,
and EP BARs are programmed with PCI bus addresses ?
So when will this offset be used, only when RP assigns BAR's to RP ?
Regards,
Valmiki
^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: Purpose of PCI address in ranges property
2017-03-23 2:59 ` valmiki
@ 2017-03-23 14:11 ` Arnd Bergmann
0 siblings, 0 replies; 4+ messages in thread
From: Arnd Bergmann @ 2017-03-23 14:11 UTC (permalink / raw)
To: valmiki; +Cc: Linux Kernel Mailing List, linux-pci, Bjorn Helgaas, Marc Zyngier
On Thu, Mar 23, 2017 at 3:59 AM, valmiki <valmikibow@gmail.com> wrote:
> On 3/20/2017 3:15 AM, Arnd Bergmann wrote:
>>
>> On Sun, Mar 19, 2017 at 3:14 PM, valmiki <valmikibow@gmail.com> wrote:
>>>
>>> Hi,
>>>
>>> When ranges property is being parsed using
>>> of_pci_get_host_bridge_resources,
>>> the pci address is being used for
>>> calculating the offset for pci_add_resource_offset.
>>>
>>> What is this offset for ?
>>>
>>> So the cpu address is being used for programming memory base and limit
>>> registers ?
>>
>>
>> Linux IORESOURCE_MEM resources are defined in terms of CPU addresses,
>> while PCI config space BAR registers are programmed with bus addresses.
>> These are often the same, but on some machines they are not, which results
>> in an offset that has to be used when accessing the BARs.
>>
> Thanks Arnd. So mem base and limit registers of RP are programmed with CPU
> addresses,
> and EP BARs are programmed with PCI bus addresses ?
> So when will this offset be used, only when RP assigns BAR's to RP ?
I think depending on your platform, we either assign the BARs or we
read the ones that the firmware has assigned, and either way the
offset has to be applied in or way or the other.
Arnd
^ permalink raw reply [flat|nested] 4+ messages in thread
end of thread, other threads:[~2017-03-23 14:11 UTC | newest]
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2017-03-19 14:14 Purpose of PCI address in ranges property valmiki
2017-03-19 21:45 ` Arnd Bergmann
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2017-03-23 14:11 ` Arnd Bergmann
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