From: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
To: Pratyush Brahma <quic_pbrahma@quicinc.com>,
Bjorn Andersson <andersson@kernel.org>,
Konrad Dybcio <konradybcio@kernel.org>,
Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>
Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org
Subject: Re: [PATCH] arm64: dts: qcom: qcs8300: add the pcie smmu node
Date: Sat, 12 Apr 2025 02:01:54 +0200 [thread overview]
Message-ID: <dc535643-235d-46e9-b241-7d7b0e75e6ac@oss.qualcomm.com> (raw)
In-Reply-To: <20250206-qcs8300-pcie-smmu-v1-1-8eee0e3585bc@quicinc.com>
On 2/6/25 2:43 PM, Pratyush Brahma wrote:
> Add the PCIe SMMU node to enable address translations
> for pcie.
>
> Signed-off-by: Pratyush Brahma <quic_pbrahma@quicinc.com>
> ---
> arch/arm64/boot/dts/qcom/qcs8300.dtsi | 75 +++++++++++++++++++++++++++++++++++
> 1 file changed, 75 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/qcs8300.dtsi b/arch/arm64/boot/dts/qcom/qcs8300.dtsi
> index 4a057f7c0d9fae0ebd1b3cf3468746b382bc886b..fe88244771583de9fed7b7e88c69a14872d4ffc8 100644
> --- a/arch/arm64/boot/dts/qcom/qcs8300.dtsi
> +++ b/arch/arm64/boot/dts/qcom/qcs8300.dtsi
> @@ -3199,6 +3199,81 @@ apps_smmu: iommu@15000000 {
> <GIC_SPI 895 IRQ_TYPE_LEVEL_HIGH>;
> };
>
> + pcie_smmu: iommu@15200000 {
> + compatible = "qcom,qcs8300-smmu-500", "qcom,smmu-500", "arm,mmu-500";
> + reg = <0x0 0x15200000 0x0 0x80000>;
> + #iommu-cells = <2>;
> + #global-interrupts = <2>;
> + dma-coherent;
> +
> + interrupts = <GIC_SPI 920 IRQ_TYPE_LEVEL_HIGH>,
This IRQ is not routed
> + <GIC_SPI 921 IRQ_TYPE_LEVEL_HIGH>,
We want 922 here instead and this is the only global interrupt we care about
(set #global-interrupts to 1)
> + <GIC_SPI 925 IRQ_TYPE_LEVEL_HIGH>,
This is a PMU irq which is apparently left unsupported on DT systems..
https://lore.kernel.org/all/b51de3ac-5dbe-a1f1-1897-febb52f3cb34@arm.com/
please remove
> + <GIC_SPI 926 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 927 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 928 IRQ_TYPE_LEVEL_HIGH>,
+929> + <GIC_SPI 950 IRQ_TYPE_LEVEL_HIGH>,
-950> + <GIC_SPI 951 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 952 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 953 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 954 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 955 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 956 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 957 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 958 IRQ_TYPE_LEVEL_HIGH>,
+959
> + <GIC_SPI 885 IRQ_TYPE_LEVEL_HIGH>,
-885
> + <GIC_SPI 886 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 887 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 888 IRQ_TYPE_LEVEL_HIGH>,
+889
> + <GIC_SPI 820 IRQ_TYPE_LEVEL_HIGH>,
-820
+821
> + <GIC_SPI 822 IRQ_TYPE_LEVEL_HIGH>,
-822
+823
> + <GIC_SPI 823 IRQ_TYPE_LEVEL_HIGH>,
-823
+824
> + <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 446 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 447 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 452 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 840 IRQ_TYPE_LEVEL_HIGH>,
-840
> + <GIC_SPI 841 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 842 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 843 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 844 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 845 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 846 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 847 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 848 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 849 IRQ_TYPE_LEVEL_HIGH>,
+850
> + <GIC_SPI 802 IRQ_TYPE_LEVEL_HIGH>,
-802
> + <GIC_SPI 803 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 804 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 805 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 806 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 807 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 808 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 809 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 810 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 811 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 812 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 813 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 814 IRQ_TYPE_LEVEL_HIGH>,
+815
> + <GIC_SPI 836 IRQ_TYPE_LEVEL_HIGH>,
-836
> + <GIC_SPI 837 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 838 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 839 IRQ_TYPE_LEVEL_HIGH>,
+840
> + <GIC_SPI 854 IRQ_TYPE_LEVEL_HIGH>,
-854
> + <GIC_SPI 855 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 856 IRQ_TYPE_LEVEL_HIGH>,
+857
> + <GIC_SPI 790 IRQ_TYPE_LEVEL_HIGH>,
-790
> + <GIC_SPI 791 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 792 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 793 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 794 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 795 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 796 IRQ_TYPE_LEVEL_HIGH>,
+797
> + <GIC_SPI 639 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>,
-79
> + <GIC_SPI 640 IRQ_TYPE_LEVEL_HIGH>;
> + };
Konrad
prev parent reply other threads:[~2025-04-12 0:02 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-02-06 13:43 Pratyush Brahma
2025-03-11 22:05 ` Pratyush Brahma
2025-03-12 6:53 ` Dmitry Baryshkov
2025-03-12 7:11 ` Pratyush Brahma
2025-03-12 8:44 ` Dmitry Baryshkov
2025-03-12 10:19 ` Pratyush Brahma
2025-03-14 22:00 ` Konrad Dybcio
2025-03-28 8:51 ` Pratyush Brahma
2025-04-03 18:46 ` Pratyush Brahma
2025-04-03 20:48 ` Konrad Dybcio
2025-04-12 0:01 ` Konrad Dybcio [this message]
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