[PATCH v2 0/2] Bring dclk_vop2 in line with other VPs on RK3588

[PATCH v2 0/2] Bring dclk_vop2 in line with other VPs on RK3588

[Heiko Stuebner]

The dclk for VP2 behaves differently and its use can currently break
other peripherals, so fix that and additionally allow it to drive
the same outputs.

I've kept Quentin's Tested-by from v1, as the overall change is the same
but did not transfer his Reviewed-by, as the series-structure changed.


changes in v2:
- split the actual fix for breakage and change of reparent handling
  into two separate patches

Heiko Stuebner (2):
  clk: rockchip: rk3588: Don't change PLL rates when setting
    dclk_vop2_src
  clk: rockchip: rk3588: Allow VP2 the same sourcing options as other
    VPs

 drivers/clk/rockchip/clk-rk3588.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

-- 
2.47.3

[PATCH v2 1/2] clk: rockchip: rk3588: Don't change PLL rates when setting dclk_vop2_src

[Heiko Stuebner]

From: Heiko Stuebner <heiko.stuebner@cherry.de>

dclk_vop2_src currently has the CLK_SET_RATE_PARENT flag set, which is
very different from dclk_vop0_src or dclk_vop1_src, which don't have it.

With this flag in dclk_vop2_src, actually setting the clock then results
in a lot of other peripherals breaking, because setting the rate results
in the PLL source getting changed:

[   14.898718] clk_core_set_rate_nolock: setting rate for dclk_vop2 to 152840000
[   15.155017] clk_change_rate: setting rate for pll_gpll to 1680000000
[ clk adjusting every gpll user ]

This includes possibly the other vops, i2s, spdif and even the uarts.
Among other possible things, this breaks the uart console on a board
I use. Sometimes it recovers later on, but there will be a big block
of garbled output for a while at least.

Shared PLLs should not be changed by individual users, so drop this flag
from dclk_vop2_src.

Fixes: f1c506d152ff ("clk: rockchip: add clock controller for the RK3588")
Cc: stable@vger.kernel.org
Tested-by: Quentin Schulz <quentin.schulz@cherry.de> # RK3588 Tiger w/ DP
Signed-off-by: Heiko Stuebner <heiko.stuebner@cherry.de>
---
 drivers/clk/rockchip/clk-rk3588.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/clk/rockchip/clk-rk3588.c b/drivers/clk/rockchip/clk-rk3588.c
index 1694223f4f84..bea2deed0e23 100644
--- a/drivers/clk/rockchip/clk-rk3588.c
+++ b/drivers/clk/rockchip/clk-rk3588.c
@@ -2094,7 +2094,7 @@ static struct rockchip_clk_branch rk3588_early_clk_branches[] __initdata = {
 	COMPOSITE(DCLK_VOP1_SRC, "dclk_vop1_src", gpll_cpll_v0pll_aupll_p, 0,
 			RK3588_CLKSEL_CON(111), 14, 2, MFLAGS, 9, 5, DFLAGS,
 			RK3588_CLKGATE_CON(52), 11, GFLAGS),
-	COMPOSITE(DCLK_VOP2_SRC, "dclk_vop2_src", gpll_cpll_v0pll_aupll_p, CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
+	COMPOSITE(DCLK_VOP2_SRC, "dclk_vop2_src", gpll_cpll_v0pll_aupll_p, CLK_SET_RATE_NO_REPARENT,
 			RK3588_CLKSEL_CON(112), 5, 2, MFLAGS, 0, 5, DFLAGS,
 			RK3588_CLKGATE_CON(52), 12, GFLAGS),
 	COMPOSITE_NODIV(DCLK_VOP0, "dclk_vop0", dclk_vop0_p,
-- 
2.47.3

[PATCH v2 2/2] clk: rockchip: rk3588: Allow VP2 the same sourcing options as other VPs

[Heiko Stuebner]

From: Heiko Stuebner <heiko.stuebner@cherry.de>

Right now dclk_vop2_src is not allowed to change its parent, while
the other two dclks are allowed to do this.

All three VPs can drive non-static outputs (HDMI, DP, eDP) and even the
eDP can also support full DP connections (though no DP+).

Therefore remove the CLK_SET_RATE_NO_REPARENT flag, to allow VP2 the same
flexibility in aquiring its clock rate.

Tested-by: Quentin Schulz <quentin.schulz@cherry.de> # RK3588 Tiger w/ DP
Signed-off-by: Heiko Stuebner <heiko.stuebner@cherry.de>
---
 drivers/clk/rockchip/clk-rk3588.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/clk/rockchip/clk-rk3588.c b/drivers/clk/rockchip/clk-rk3588.c
index bea2deed0e23..cf83242d1726 100644
--- a/drivers/clk/rockchip/clk-rk3588.c
+++ b/drivers/clk/rockchip/clk-rk3588.c
@@ -2094,7 +2094,7 @@ static struct rockchip_clk_branch rk3588_early_clk_branches[] __initdata = {
 	COMPOSITE(DCLK_VOP1_SRC, "dclk_vop1_src", gpll_cpll_v0pll_aupll_p, 0,
 			RK3588_CLKSEL_CON(111), 14, 2, MFLAGS, 9, 5, DFLAGS,
 			RK3588_CLKGATE_CON(52), 11, GFLAGS),
-	COMPOSITE(DCLK_VOP2_SRC, "dclk_vop2_src", gpll_cpll_v0pll_aupll_p, CLK_SET_RATE_NO_REPARENT,
+	COMPOSITE(DCLK_VOP2_SRC, "dclk_vop2_src", gpll_cpll_v0pll_aupll_p, 0,
 			RK3588_CLKSEL_CON(112), 5, 2, MFLAGS, 0, 5, DFLAGS,
 			RK3588_CLKGATE_CON(52), 12, GFLAGS),
 	COMPOSITE_NODIV(DCLK_VOP0, "dclk_vop0", dclk_vop0_p,
-- 
2.47.3

Re: [PATCH v2 0/2] Bring dclk_vop2 in line with other VPs on RK3588

[Chris Morgan]

On Wed, Mar 04, 2026 at 01:14:24PM +0100, Heiko Stuebner wrote:
> The dclk for VP2 behaves differently and its use can currently break
> other peripherals, so fix that and additionally allow it to drive
> the same outputs.
> 
> I've kept Quentin's Tested-by from v1, as the overall change is the same
> but did not transfer his Reviewed-by, as the series-structure changed.
> 
> 
> changes in v2:
> - split the actual fix for breakage and change of reparent handling
>   into two separate patches
> 
> Heiko Stuebner (2):
>   clk: rockchip: rk3588: Don't change PLL rates when setting
>     dclk_vop2_src
>   clk: rockchip: rk3588: Allow VP2 the same sourcing options as other
>     VPs
> 
>  drivers/clk/rockchip/clk-rk3588.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> -- 
> 2.47.3
> 

Tested-by: Chris Morgan <macromorgan@hotmail.com>

Re: [PATCH v2 1/2] clk: rockchip: rk3588: Don't change PLL rates when setting dclk_vop2_src

[Quentin Schulz]

Hi Heiko,

On 3/4/26 1:14 PM, Heiko Stuebner wrote:
> From: Heiko Stuebner <heiko.stuebner@cherry.de>
> 
> dclk_vop2_src currently has the CLK_SET_RATE_PARENT flag set, which is
> very different from dclk_vop0_src or dclk_vop1_src, which don't have it.
> 
> With this flag in dclk_vop2_src, actually setting the clock then results
> in a lot of other peripherals breaking, because setting the rate results
> in the PLL source getting changed:
> 
> [   14.898718] clk_core_set_rate_nolock: setting rate for dclk_vop2 to 152840000
> [   15.155017] clk_change_rate: setting rate for pll_gpll to 1680000000
> [ clk adjusting every gpll user ]
> 
> This includes possibly the other vops, i2s, spdif and even the uarts.
> Among other possible things, this breaks the uart console on a board
> I use. Sometimes it recovers later on, but there will be a big block
> of garbled output for a while at least.
> 
> Shared PLLs should not be changed by individual users, so drop this flag
> from dclk_vop2_src.
> 
> Fixes: f1c506d152ff ("clk: rockchip: add clock controller for the RK3588")
> Cc: stable@vger.kernel.org
> Tested-by: Quentin Schulz <quentin.schulz@cherry.de> # RK3588 Tiger w/ DP

Reviewed-by: Quentin Schulz <quentin.schulz@cherry.de>

Thanks!
Quentin

Re: [PATCH v2 2/2] clk: rockchip: rk3588: Allow VP2 the same sourcing options as other VPs

[Quentin Schulz]

Hi Heiko,

On 3/4/26 1:14 PM, Heiko Stuebner wrote:
> From: Heiko Stuebner <heiko.stuebner@cherry.de>
> 
> Right now dclk_vop2_src is not allowed to change its parent, while
> the other two dclks are allowed to do this.

nitpick: the src dclk of the other 2 VOPs (there are other clocks named 
dclk and the dclk_vopX actually all (except dclk_vop3) have 
set_rate_parent and set_rate_no_reparent).

> 
> All three VPs can drive non-static outputs (HDMI, DP, eDP) and even the
> eDP can also support full DP connections (though no DP+).
> 
> Therefore remove the CLK_SET_RATE_NO_REPARENT flag, to allow VP2 the same
> flexibility in aquiring its clock rate.
> 

nitpick: s/aquiring/acquiring/

> Tested-by: Quentin Schulz <quentin.schulz@cherry.de> # RK3588 Tiger w/ DP

Reviewed-by: Quentin Schulz <quentin.schuz@cherry.de>

Thanks!
Quentin

Re: [PATCH v2 1/2] clk: rockchip: rk3588: Don't change PLL rates when setting dclk_vop2_src

[Quentin Schulz]

Hi Heiko,

On 3/4/26 1:14 PM, Heiko Stuebner wrote:
> From: Heiko Stuebner <heiko.stuebner@cherry.de>
> 
> dclk_vop2_src currently has the CLK_SET_RATE_PARENT flag set, which is
> very different from dclk_vop0_src or dclk_vop1_src, which don't have it.
> 
> With this flag in dclk_vop2_src, actually setting the clock then results
> in a lot of other peripherals breaking, because setting the rate results
> in the PLL source getting changed:
> 
> [   14.898718] clk_core_set_rate_nolock: setting rate for dclk_vop2 to 152840000
> [   15.155017] clk_change_rate: setting rate for pll_gpll to 1680000000
> [ clk adjusting every gpll user ]
> 
> This includes possibly the other vops, i2s, spdif and even the uarts.
> Among other possible things, this breaks the uart console on a board
> I use. Sometimes it recovers later on, but there will be a big block
> of garbled output for a while at least.
> 
> Shared PLLs should not be changed by individual users, so drop this flag
> from dclk_vop2_src.
> 
> Fixes: f1c506d152ff ("clk: rockchip: add clock controller for the RK3588")
> Cc: stable@vger.kernel.org
> Tested-by: Quentin Schulz <quentin.schulz@cherry.de> # RK3588 Tiger w/ DP

Reviewed-by: Quentin Schulz <quentin.schulz@cherry.de>

Thanks!
Quentin

Re: [PATCH v2 2/2] clk: rockchip: rk3588: Allow VP2 the same sourcing options as other VPs

[Quentin Schulz]

Hi Heiko,

On 3/4/26 1:14 PM, Heiko Stuebner wrote:
 > From: Heiko Stuebner <heiko.stuebner@cherry.de>
 >
 > Right now dclk_vop2_src is not allowed to change its parent, while
 > the other two dclks are allowed to do this.

nitpick: the src dclk of the other 2 VOPs (there are other clocks named 
dclk and the dclk_vopX actually all (except dclk_vop3) have 
set_rate_parent and set_rate_no_reparent).

 >
 > All three VPs can drive non-static outputs (HDMI, DP, eDP) and even the
 > eDP can also support full DP connections (though no DP+).
 >
 > Therefore remove the CLK_SET_RATE_NO_REPARENT flag, to allow VP2 the same
 > flexibility in aquiring its clock rate.
 >

nitpick: s/aquiring/acquiring/

Reviewed-by: Quentin Schulz <quentin.schuz@cherry.de>

Thanks!
Quentin

Re: [PATCH v2 0/2] Bring dclk_vop2 in line with other VPs on RK3588

[Heiko Stuebner]

On Wed, 04 Mar 2026 13:14:24 +0100, Heiko Stuebner wrote:
> The dclk for VP2 behaves differently and its use can currently break
> other peripherals, so fix that and additionally allow it to drive
> the same outputs.
> 
> I've kept Quentin's Tested-by from v1, as the overall change is the same
> but did not transfer his Reviewed-by, as the series-structure changed.
> 
> [...]

Applied, thanks!

[1/2] clk: rockchip: rk3588: Don't change PLL rates when setting dclk_vop2_src
      commit: 13b10571cc353448275365ede1a5396d20dfe839
[2/2] clk: rockchip: rk3588: Allow VP2 the same sourcing options as other VPs
      commit: 778dd30867ad783b6903b0aa24a0ab5e97c2dff6

Best regards,
-- 
Heiko Stuebner <heiko@sntech.de>