From: Florian Fainelli <florian.fainelli@broadcom.com>
To: Willow Cunningham <willow.e.cunningham@gmail.com>
Cc: willow.e.cunningham@maine.edu, Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>,
Stefan Wahren <wahrenst@gmx.net>,
Andrea della Porta <andrea.porta@suse.com>,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH] arm64: dts: broadcom: Fix L2 linesize for Raspberry Pi 5
Date: Thu, 10 Oct 2024 16:07:21 -0700 [thread overview]
Message-ID: <dfc1ab0b-0d5f-4205-b8b0-96784d58d31b@broadcom.com> (raw)
In-Reply-To: <20241010150409.262087-1-willow.e.cunningham@maine.edu>
On 10/10/24 08:04, Willow Cunningham wrote:
> From: Willow Cunningham <willow.e.cunningham@gmail.com>
>
> Fixes: faa3381267d0 ("arm64: dts: broadcom: Add minimal support for
> Raspberry Pi 5")
>
> Set the cache-line-size parameter of the L2 cache for each core to the
> correct value of 64 bytes.
>
> Previously, the L2 cache line size was incorrectly set to 128 bytes
> for the Broadcom BCM2712. This causes validation tests for the
> Performance Application Programming Interface (PAPI) tool to fail as
> they depend on sysfs accurately reporting cache line sizes.
>
> The correct value of 64 bytes is stated in the official documentation of
> the ARM Cortex A-72, which is linked in the comments of
> arm64/boot/dts/broadcom/bcm2712.dtsi as the source for cache-line-size.
>
> Signed-off-by: Willow Cunningham <willow.e.cunningham@maine.edu>
Applied, thanks!
--
Florian
prev parent reply other threads:[~2024-10-10 23:07 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-10-10 15:04 Willow Cunningham
2024-10-10 16:30 ` Conor Dooley
2024-10-10 16:36 ` Florian Fainelli
2024-10-10 23:07 ` Florian Fainelli [this message]
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