* [PATCH v2 0/2] Add Coresight support for RB5 board @ 2021-09-24 10:06 Tao Zhang 2021-09-24 10:06 ` [PATCH v2 1/2] coresight: etm4x: Add ETM PID for Kryo-5XX Tao Zhang 2021-09-24 10:06 ` [PATCH v2 2/2] arm64: dts: qcom: sm8250: Add Coresight support Tao Zhang 0 siblings, 2 replies; 9+ messages in thread From: Tao Zhang @ 2021-09-24 10:06 UTC (permalink / raw) To: Mathieu Poirier, Suzuki K Poulose, Alexander Shishkin Cc: Tao Zhang, Mike Leach, Leo Yan, Greg Kroah-Hartman, coresight, linux-arm-kernel, linux-kernel, Tingwei Zhang, Mao Jinlong, Yuanfang Zhang This series adds Coresight support for SM8250 Soc on RB5 board. It is composed of two elements. a) Add ETM PID for Kryo-5XX. b) Add coresight support to DTS for RB5. Changes since V2: - Add the comment "Cortex-A77" for Kryo-5XX ETM PID. - Correct the errors in the patch "Add Coresight support for RB5 board" v1 version, and the adsp-related configuration should not be deleted. Changes since V1: - Add ETM PID for Kryo-5XX. - Add coresight supoort to device tree for RB5. ETM verification and use of Coresight components need Coresight support in device tree. Since the ETR sink needs SMMU support, and SMMU has not been enabled on RB5. ETR is not added to this patch, and it will be added once SMMU is enabled on RB5. ETF sink has been added to the device tree for RB5. This series applies to coresight/next https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git Tao Zhang (2): coresight: etm4x: Add ETM PID for Kryo-5XX arm64: dts: qcom: sm8250: Add Coresight support arch/arm64/boot/dts/qcom/qrb5165-rb5.dts | 442 +++++++++++++++++- .../coresight/coresight-etm4x-core.c | 1 + 2 files changed, 439 insertions(+), 4 deletions(-) -- The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project ^ permalink raw reply [flat|nested] 9+ messages in thread
* [PATCH v2 1/2] coresight: etm4x: Add ETM PID for Kryo-5XX 2021-09-24 10:06 [PATCH v2 0/2] Add Coresight support for RB5 board Tao Zhang @ 2021-09-24 10:06 ` Tao Zhang 2021-09-24 13:17 ` Suzuki K Poulose 2021-09-24 10:06 ` [PATCH v2 2/2] arm64: dts: qcom: sm8250: Add Coresight support Tao Zhang 1 sibling, 1 reply; 9+ messages in thread From: Tao Zhang @ 2021-09-24 10:06 UTC (permalink / raw) To: Mathieu Poirier, Suzuki K Poulose, Alexander Shishkin Cc: Tao Zhang, Mike Leach, Leo Yan, Greg Kroah-Hartman, coresight, linux-arm-kernel, linux-kernel, Tingwei Zhang, Mao Jinlong, Yuanfang Zhang Add ETM PID for Kryo-5XX to the list of supported ETMs. Otherwise, Kryo-5XX ETMs will not be initialized successfully. e.g. This change can be verified on qrb5165-rb5 board. ETM4-ETM7 nodes will not be visible without this change. Signed-off-by: Tao Zhang <quic_taozha@quicinc.com> --- drivers/hwtracing/coresight/coresight-etm4x-core.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c b/drivers/hwtracing/coresight/coresight-etm4x-core.c index da27cd4..52ca918 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x-core.c +++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c @@ -2065,6 +2065,7 @@ static const struct amba_id etm4_ids[] = { CS_AMBA_UCI_ID(0x000bb803, uci_id_etm4),/* Qualcomm Kryo 385 Cortex-A75 */ CS_AMBA_UCI_ID(0x000bb805, uci_id_etm4),/* Qualcomm Kryo 4XX Cortex-A55 */ CS_AMBA_UCI_ID(0x000bb804, uci_id_etm4),/* Qualcomm Kryo 4XX Cortex-A76 */ + CS_AMBA_UCI_ID(0x000bbd0d, uci_id_etm4),/* Qualcomm Kryo 5XX Cortex-A77 */ CS_AMBA_UCI_ID(0x000cc0af, uci_id_etm4),/* Marvell ThunderX2 */ CS_AMBA_UCI_ID(0x000b6d01, uci_id_etm4),/* HiSilicon-Hip08 */ CS_AMBA_UCI_ID(0x000b6d02, uci_id_etm4),/* HiSilicon-Hip09 */ -- The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project ^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH v2 1/2] coresight: etm4x: Add ETM PID for Kryo-5XX 2021-09-24 10:06 ` [PATCH v2 1/2] coresight: etm4x: Add ETM PID for Kryo-5XX Tao Zhang @ 2021-09-24 13:17 ` Suzuki K Poulose 0 siblings, 0 replies; 9+ messages in thread From: Suzuki K Poulose @ 2021-09-24 13:17 UTC (permalink / raw) To: Tao Zhang, Mathieu Poirier, Alexander Shishkin Cc: Mike Leach, Leo Yan, Greg Kroah-Hartman, coresight, linux-arm-kernel, linux-kernel, Tingwei Zhang, Mao Jinlong, Yuanfang Zhang On 24/09/2021 11:06, Tao Zhang wrote: > Add ETM PID for Kryo-5XX to the list of supported ETMs. > Otherwise, Kryo-5XX ETMs will not be initialized successfully. > e.g. > This change can be verified on qrb5165-rb5 board. ETM4-ETM7 nodes > will not be visible without this change. > > Signed-off-by: Tao Zhang <quic_taozha@quicinc.com> I have queued this one. Suzuki ^ permalink raw reply [flat|nested] 9+ messages in thread
* [PATCH v2 2/2] arm64: dts: qcom: sm8250: Add Coresight support 2021-09-24 10:06 [PATCH v2 0/2] Add Coresight support for RB5 board Tao Zhang 2021-09-24 10:06 ` [PATCH v2 1/2] coresight: etm4x: Add ETM PID for Kryo-5XX Tao Zhang @ 2021-09-24 10:06 ` Tao Zhang 2021-09-24 13:11 ` Suzuki K Poulose 2022-08-11 9:25 ` Anshuman Khandual 1 sibling, 2 replies; 9+ messages in thread From: Tao Zhang @ 2021-09-24 10:06 UTC (permalink / raw) To: Mathieu Poirier, Suzuki K Poulose, Alexander Shishkin Cc: Tao Zhang, Mike Leach, Leo Yan, Greg Kroah-Hartman, coresight, linux-arm-kernel, linux-kernel, Tingwei Zhang, Mao Jinlong, Yuanfang Zhang Add the basic coresight components found on Qualcomm SM8250 Soc. The basic coresight components include ETF, ETMs,STM and the related funnels. Signed-off-by: Tao Zhang <quic_taozha@quicinc.com> --- arch/arm64/boot/dts/qcom/qrb5165-rb5.dts | 439 +++++++++++++++++++++++++++++++ 1 file changed, 439 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts b/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts index 5f41de2..1e1579a 100644 --- a/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts +++ b/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts @@ -223,6 +223,445 @@ regulator-max-microvolt = <1800000>; regulator-always-on; }; + + stm@6002000 { + compatible = "arm,coresight-stm", "arm,primecell"; + reg = <0 0x06002000 0 0x1000>, + <0 0x16280000 0 0x180000>; + reg-names = "stm-base", "stm-stimulus-base"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + out-ports { + port { + stm_out: endpoint { + remote-endpoint = + <&funnel0_in7>; + }; + }; + }; + }; + + funnel@6041000 { + compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; + reg = <0 0x06041000 0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + out-ports { + port { + funnel0_out: endpoint { + remote-endpoint = + <&merge_funnel_in0>; + }; + }; + }; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@7 { + reg = <7>; + funnel0_in7: endpoint { + remote-endpoint = <&stm_out>; + }; + }; + }; + }; + + funnel@6042000 { + compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; + reg = <0 0x06042000 0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + out-ports { + port { + funnel2_out: endpoint { + remote-endpoint = + <&merge_funnel_in2>; + }; + }; + }; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@4 { + reg = <4>; + funnel2_in5: endpoint { + remote-endpoint = + <&apss_merge_funnel_out>; + }; + }; + }; + }; + + funnel@6b04000 { + compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; + arm,primecell-periphid = <0x000bb908>; + + reg = <0 0x6b04000 0 0x1000>; + reg-names = "funnel-base"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + out-ports { + port { + merge_funnel_out: endpoint { + remote-endpoint = + <&etf_in>; + }; + }; + }; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@7 { + reg = <7>; + swao_funnel_in7: endpoint { + slave-mode; + remote-endpoint= + <&merg_funnel_out>; + }; + }; + }; + + }; + + funnel@6045000 { + compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; + reg = <0 0x06045000 0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + out-ports { + port { + merg_funnel_out: endpoint { + remote-endpoint = <&swao_funnel_in7>; + }; + }; + }; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + merge_funnel_in0: endpoint { + remote-endpoint = + <&funnel0_out>; + }; + }; + + port@1 { + reg = <1>; + merge_funnel_in2: endpoint { + remote-endpoint = + <&funnel2_out>; + }; + }; + }; + }; + + etf@6b05000 { + compatible = "arm,coresight-tmc", "arm,primecell"; + reg = <0 0x06b05000 0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + in-ports { + port { + etf_in: endpoint { + remote-endpoint = + <&merge_funnel_out>; + }; + }; + }; + }; + + etm@7040000 { + compatible = "arm,coresight-etm4x", "arm,primecell"; + reg = <0 0x07040000 0 0x1000>; + + cpu = <&CPU0>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + arm,coresight-loses-context-with-cpu; + + out-ports { + port { + etm0_out: endpoint { + remote-endpoint = + <&apss_funnel_in0>; + }; + }; + }; + }; + + etm@7140000 { + compatible = "arm,coresight-etm4x", "arm,primecell"; + reg = <0 0x07140000 0 0x1000>; + + cpu = <&CPU1>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + arm,coresight-loses-context-with-cpu; + + out-ports { + port { + etm1_out: endpoint { + remote-endpoint = + <&apss_funnel_in1>; + }; + }; + }; + }; + + etm@7240000 { + compatible = "arm,coresight-etm4x", "arm,primecell"; + reg = <0 0x07240000 0 0x1000>; + + cpu = <&CPU2>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + arm,coresight-loses-context-with-cpu; + + out-ports { + port { + etm2_out: endpoint { + remote-endpoint = + <&apss_funnel_in2>; + }; + }; + }; + }; + + etm@7340000 { + compatible = "arm,coresight-etm4x", "arm,primecell"; + reg = <0 0x07340000 0 0x1000>; + + cpu = <&CPU3>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + arm,coresight-loses-context-with-cpu; + + out-ports { + port { + etm3_out: endpoint { + remote-endpoint = + <&apss_funnel_in3>; + }; + }; + }; + }; + + etm@7440000 { + compatible = "arm,coresight-etm4x", "arm,primecell"; + reg = <0 0x07440000 0 0x1000>; + + cpu = <&CPU4>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + arm,coresight-loses-context-with-cpu; + + out-ports { + port { + etm4_out: endpoint { + remote-endpoint = + <&apss_funnel_in4>; + }; + }; + }; + }; + + etm@7540000 { + compatible = "arm,coresight-etm4x", "arm,primecell"; + reg = <0 0x07540000 0 0x1000>; + + cpu = <&CPU5>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + arm,coresight-loses-context-with-cpu; + + out-ports { + port { + etm5_out: endpoint { + remote-endpoint = + <&apss_funnel_in5>; + }; + }; + }; + }; + + etm@7640000 { + compatible = "arm,coresight-etm4x", "arm,primecell"; + reg = <0 0x07640000 0 0x1000>; + + cpu = <&CPU6>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + arm,coresight-loses-context-with-cpu; + + out-ports { + port { + etm6_out: endpoint { + remote-endpoint = + <&apss_funnel_in6>; + }; + }; + }; + }; + + etm@7740000 { + compatible = "arm,coresight-etm4x", "arm,primecell"; + reg = <0 0x07740000 0 0x1000>; + + cpu = <&CPU7>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + arm,coresight-loses-context-with-cpu; + + out-ports { + port { + etm7_out: endpoint { + remote-endpoint = + <&apss_funnel_in7>; + }; + }; + }; + }; + + funnel@7800000 { + compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; + reg = <0 0x07800000 0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + out-ports { + port { + apss_funnel_out: endpoint { + remote-endpoint = + <&apss_merge_funnel_in>; + }; + }; + }; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + apss_funnel_in0: endpoint { + remote-endpoint = + <&etm0_out>; + }; + }; + + port@1 { + reg = <1>; + apss_funnel_in1: endpoint { + remote-endpoint = + <&etm1_out>; + }; + }; + + port@2 { + reg = <2>; + apss_funnel_in2: endpoint { + remote-endpoint = + <&etm2_out>; + }; + }; + + port@3 { + reg = <3>; + apss_funnel_in3: endpoint { + remote-endpoint = + <&etm3_out>; + }; + }; + + port@4 { + reg = <4>; + apss_funnel_in4: endpoint { + remote-endpoint = + <&etm4_out>; + }; + }; + + port@5 { + reg = <5>; + apss_funnel_in5: endpoint { + remote-endpoint = + <&etm5_out>; + }; + }; + + port@6 { + reg = <6>; + apss_funnel_in6: endpoint { + remote-endpoint = + <&etm6_out>; + }; + }; + + port@7 { + reg = <7>; + apss_funnel_in7: endpoint { + remote-endpoint = + <&etm7_out>; + }; + }; + }; + }; + + funnel@7810000 { + compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; + reg = <0 0x07810000 0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + out-ports { + port { + apss_merge_funnel_out: endpoint { + remote-endpoint = + <&funnel2_in5>; + }; + }; + }; + + in-ports { + port { + apss_merge_funnel_in: endpoint { + remote-endpoint = + <&apss_funnel_out>; + }; + }; + }; + }; }; &adsp { -- The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project ^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH v2 2/2] arm64: dts: qcom: sm8250: Add Coresight support 2021-09-24 10:06 ` [PATCH v2 2/2] arm64: dts: qcom: sm8250: Add Coresight support Tao Zhang @ 2021-09-24 13:11 ` Suzuki K Poulose 2021-09-27 2:42 ` Tao Zhang 2022-08-11 9:25 ` Anshuman Khandual 1 sibling, 1 reply; 9+ messages in thread From: Suzuki K Poulose @ 2021-09-24 13:11 UTC (permalink / raw) To: Tao Zhang, Mathieu Poirier, Alexander Shishkin Cc: Mike Leach, Leo Yan, Greg Kroah-Hartman, coresight, linux-arm-kernel, linux-kernel, Tingwei Zhang, Mao Jinlong, Yuanfang Zhang Hi Tao On 24/09/2021 11:06, Tao Zhang wrote: > Add the basic coresight components found on Qualcomm SM8250 Soc. The > basic coresight components include ETF, ETMs,STM and the related > funnels. > > Signed-off-by: Tao Zhang <quic_taozha@quicinc.com> Acked-by: Suzuki K Poulose <suzuki.poulose@arm.com> PS: This patch must go via the Qcom DT maintainers. I would recommend sending this to the following people, so that it can be queued. $ scripts/get_maintainer.pl arch/arm64/boot/dts/qcom/qrb5165-rb5.dts Andy Gross <agross@kernel.org> (maintainer:ARM/QUALCOMM SUPPORT) Bjorn Andersson <bjorn.andersson@linaro.org> (maintainer:ARM/QUALCOMM SUPPORT) Rob Herring <robh+dt@kernel.org> (maintainer:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS) linux-arm-msm@vger.kernel.org (open list:ARM/QUALCOMM SUPPORT) devicetree@vger.kernel.org (open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS) linux-kernel@vger.kernel.org (open list) Kind regards Suzuki ^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH v2 2/2] arm64: dts: qcom: sm8250: Add Coresight support 2021-09-24 13:11 ` Suzuki K Poulose @ 2021-09-27 2:42 ` Tao Zhang 0 siblings, 0 replies; 9+ messages in thread From: Tao Zhang @ 2021-09-27 2:42 UTC (permalink / raw) To: Suzuki K Poulose Cc: Mathieu Poirier, Alexander Shishkin, Mike Leach, Leo Yan, Greg Kroah-Hartman, coresight, linux-arm-kernel, linux-kernel, Tingwei Zhang, Mao Jinlong, Yuanfang Zhang On Fri, Sep 24, 2021 at 02:11:00PM +0100, Suzuki K Poulose wrote: > Hi Tao > > On 24/09/2021 11:06, Tao Zhang wrote: > >Add the basic coresight components found on Qualcomm SM8250 Soc. The > >basic coresight components include ETF, ETMs,STM and the related > >funnels. > > > >Signed-off-by: Tao Zhang <quic_taozha@quicinc.com> > > Acked-by: Suzuki K Poulose <suzuki.poulose@arm.com> > > PS: This patch must go via the Qcom DT maintainers. I would > recommend sending this to the following people, so that it > can be queued. > > $ scripts/get_maintainer.pl arch/arm64/boot/dts/qcom/qrb5165-rb5.dts > > Andy Gross <agross@kernel.org> (maintainer:ARM/QUALCOMM SUPPORT) > Bjorn Andersson <bjorn.andersson@linaro.org> (maintainer:ARM/QUALCOMM > SUPPORT) > Rob Herring <robh+dt@kernel.org> (maintainer:OPEN FIRMWARE AND FLATTENED > DEVICE TREE BINDINGS) > linux-arm-msm@vger.kernel.org (open list:ARM/QUALCOMM SUPPORT) > devicetree@vger.kernel.org (open list:OPEN FIRMWARE AND FLATTENED DEVICE > TREE BINDINGS) > linux-kernel@vger.kernel.org (open list) > > Kind regards > Suzuki Hi Suzuki, Sure, I will add these maintainers and resubmit the patch for review separately. Thanks for your review. Best, Tao ^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH v2 2/2] arm64: dts: qcom: sm8250: Add Coresight support 2021-09-24 10:06 ` [PATCH v2 2/2] arm64: dts: qcom: sm8250: Add Coresight support Tao Zhang 2021-09-24 13:11 ` Suzuki K Poulose @ 2022-08-11 9:25 ` Anshuman Khandual 1 sibling, 0 replies; 9+ messages in thread From: Anshuman Khandual @ 2022-08-11 9:25 UTC (permalink / raw) To: Tao Zhang, Mathieu Poirier, Suzuki K Poulose, Alexander Shishkin, Andy Gross, Bjorn Andersson, Rob Herring, linux-arm-msm, devicetree Cc: Mike Leach, Leo Yan, Greg Kroah-Hartman, coresight, linux-arm-kernel, linux-kernel, Tingwei Zhang, Mao Jinlong, Yuanfang Zhang On 9/24/21 15:36, Tao Zhang wrote: > Add the basic coresight components found on Qualcomm SM8250 Soc. The > basic coresight components include ETF, ETMs,STM and the related > funnels. Hello, Seems like this patch never merged mainline, what happened ? This change is required to enable coresight devices on RB5 platform. - Anshuman > > Signed-off-by: Tao Zhang <quic_taozha@quicinc.com> > --- > arch/arm64/boot/dts/qcom/qrb5165-rb5.dts | 439 +++++++++++++++++++++++++++++++ > 1 file changed, 439 insertions(+) > > diff --git a/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts b/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts > index 5f41de2..1e1579a 100644 > --- a/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts > +++ b/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts > @@ -223,6 +223,445 @@ > regulator-max-microvolt = <1800000>; > regulator-always-on; > }; > + > + stm@6002000 { > + compatible = "arm,coresight-stm", "arm,primecell"; > + reg = <0 0x06002000 0 0x1000>, > + <0 0x16280000 0 0x180000>; > + reg-names = "stm-base", "stm-stimulus-base"; > + > + clocks = <&aoss_qmp>; > + clock-names = "apb_pclk"; > + > + out-ports { > + port { > + stm_out: endpoint { > + remote-endpoint = > + <&funnel0_in7>; > + }; > + }; > + }; > + }; > + > + funnel@6041000 { > + compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; > + reg = <0 0x06041000 0 0x1000>; > + > + clocks = <&aoss_qmp>; > + clock-names = "apb_pclk"; > + > + out-ports { > + port { > + funnel0_out: endpoint { > + remote-endpoint = > + <&merge_funnel_in0>; > + }; > + }; > + }; > + > + in-ports { > + #address-cells = <1>; > + #size-cells = <0>; > + > + port@7 { > + reg = <7>; > + funnel0_in7: endpoint { > + remote-endpoint = <&stm_out>; > + }; > + }; > + }; > + }; > + > + funnel@6042000 { > + compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; > + reg = <0 0x06042000 0 0x1000>; > + > + clocks = <&aoss_qmp>; > + clock-names = "apb_pclk"; > + > + out-ports { > + port { > + funnel2_out: endpoint { > + remote-endpoint = > + <&merge_funnel_in2>; > + }; > + }; > + }; > + > + in-ports { > + #address-cells = <1>; > + #size-cells = <0>; > + > + port@4 { > + reg = <4>; > + funnel2_in5: endpoint { > + remote-endpoint = > + <&apss_merge_funnel_out>; > + }; > + }; > + }; > + }; > + > + funnel@6b04000 { > + compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; > + arm,primecell-periphid = <0x000bb908>; > + > + reg = <0 0x6b04000 0 0x1000>; > + reg-names = "funnel-base"; > + > + clocks = <&aoss_qmp>; > + clock-names = "apb_pclk"; > + > + out-ports { > + port { > + merge_funnel_out: endpoint { > + remote-endpoint = > + <&etf_in>; > + }; > + }; > + }; > + > + in-ports { > + #address-cells = <1>; > + #size-cells = <0>; > + > + port@7 { > + reg = <7>; > + swao_funnel_in7: endpoint { > + slave-mode; > + remote-endpoint= > + <&merg_funnel_out>; > + }; > + }; > + }; > + > + }; > + > + funnel@6045000 { > + compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; > + reg = <0 0x06045000 0 0x1000>; > + > + clocks = <&aoss_qmp>; > + clock-names = "apb_pclk"; > + > + out-ports { > + port { > + merg_funnel_out: endpoint { > + remote-endpoint = <&swao_funnel_in7>; > + }; > + }; > + }; > + > + in-ports { > + #address-cells = <1>; > + #size-cells = <0>; > + > + port@0 { > + reg = <0>; > + merge_funnel_in0: endpoint { > + remote-endpoint = > + <&funnel0_out>; > + }; > + }; > + > + port@1 { > + reg = <1>; > + merge_funnel_in2: endpoint { > + remote-endpoint = > + <&funnel2_out>; > + }; > + }; > + }; > + }; > + > + etf@6b05000 { > + compatible = "arm,coresight-tmc", "arm,primecell"; > + reg = <0 0x06b05000 0 0x1000>; > + > + clocks = <&aoss_qmp>; > + clock-names = "apb_pclk"; > + > + in-ports { > + port { > + etf_in: endpoint { > + remote-endpoint = > + <&merge_funnel_out>; > + }; > + }; > + }; > + }; > + > + etm@7040000 { > + compatible = "arm,coresight-etm4x", "arm,primecell"; > + reg = <0 0x07040000 0 0x1000>; > + > + cpu = <&CPU0>; > + > + clocks = <&aoss_qmp>; > + clock-names = "apb_pclk"; > + arm,coresight-loses-context-with-cpu; > + > + out-ports { > + port { > + etm0_out: endpoint { > + remote-endpoint = > + <&apss_funnel_in0>; > + }; > + }; > + }; > + }; > + > + etm@7140000 { > + compatible = "arm,coresight-etm4x", "arm,primecell"; > + reg = <0 0x07140000 0 0x1000>; > + > + cpu = <&CPU1>; > + > + clocks = <&aoss_qmp>; > + clock-names = "apb_pclk"; > + arm,coresight-loses-context-with-cpu; > + > + out-ports { > + port { > + etm1_out: endpoint { > + remote-endpoint = > + <&apss_funnel_in1>; > + }; > + }; > + }; > + }; > + > + etm@7240000 { > + compatible = "arm,coresight-etm4x", "arm,primecell"; > + reg = <0 0x07240000 0 0x1000>; > + > + cpu = <&CPU2>; > + > + clocks = <&aoss_qmp>; > + clock-names = "apb_pclk"; > + arm,coresight-loses-context-with-cpu; > + > + out-ports { > + port { > + etm2_out: endpoint { > + remote-endpoint = > + <&apss_funnel_in2>; > + }; > + }; > + }; > + }; > + > + etm@7340000 { > + compatible = "arm,coresight-etm4x", "arm,primecell"; > + reg = <0 0x07340000 0 0x1000>; > + > + cpu = <&CPU3>; > + > + clocks = <&aoss_qmp>; > + clock-names = "apb_pclk"; > + arm,coresight-loses-context-with-cpu; > + > + out-ports { > + port { > + etm3_out: endpoint { > + remote-endpoint = > + <&apss_funnel_in3>; > + }; > + }; > + }; > + }; > + > + etm@7440000 { > + compatible = "arm,coresight-etm4x", "arm,primecell"; > + reg = <0 0x07440000 0 0x1000>; > + > + cpu = <&CPU4>; > + > + clocks = <&aoss_qmp>; > + clock-names = "apb_pclk"; > + arm,coresight-loses-context-with-cpu; > + > + out-ports { > + port { > + etm4_out: endpoint { > + remote-endpoint = > + <&apss_funnel_in4>; > + }; > + }; > + }; > + }; > + > + etm@7540000 { > + compatible = "arm,coresight-etm4x", "arm,primecell"; > + reg = <0 0x07540000 0 0x1000>; > + > + cpu = <&CPU5>; > + > + clocks = <&aoss_qmp>; > + clock-names = "apb_pclk"; > + arm,coresight-loses-context-with-cpu; > + > + out-ports { > + port { > + etm5_out: endpoint { > + remote-endpoint = > + <&apss_funnel_in5>; > + }; > + }; > + }; > + }; > + > + etm@7640000 { > + compatible = "arm,coresight-etm4x", "arm,primecell"; > + reg = <0 0x07640000 0 0x1000>; > + > + cpu = <&CPU6>; > + > + clocks = <&aoss_qmp>; > + clock-names = "apb_pclk"; > + arm,coresight-loses-context-with-cpu; > + > + out-ports { > + port { > + etm6_out: endpoint { > + remote-endpoint = > + <&apss_funnel_in6>; > + }; > + }; > + }; > + }; > + > + etm@7740000 { > + compatible = "arm,coresight-etm4x", "arm,primecell"; > + reg = <0 0x07740000 0 0x1000>; > + > + cpu = <&CPU7>; > + > + clocks = <&aoss_qmp>; > + clock-names = "apb_pclk"; > + arm,coresight-loses-context-with-cpu; > + > + out-ports { > + port { > + etm7_out: endpoint { > + remote-endpoint = > + <&apss_funnel_in7>; > + }; > + }; > + }; > + }; > + > + funnel@7800000 { > + compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; > + reg = <0 0x07800000 0 0x1000>; > + > + clocks = <&aoss_qmp>; > + clock-names = "apb_pclk"; > + > + out-ports { > + port { > + apss_funnel_out: endpoint { > + remote-endpoint = > + <&apss_merge_funnel_in>; > + }; > + }; > + }; > + > + in-ports { > + #address-cells = <1>; > + #size-cells = <0>; > + > + port@0 { > + reg = <0>; > + apss_funnel_in0: endpoint { > + remote-endpoint = > + <&etm0_out>; > + }; > + }; > + > + port@1 { > + reg = <1>; > + apss_funnel_in1: endpoint { > + remote-endpoint = > + <&etm1_out>; > + }; > + }; > + > + port@2 { > + reg = <2>; > + apss_funnel_in2: endpoint { > + remote-endpoint = > + <&etm2_out>; > + }; > + }; > + > + port@3 { > + reg = <3>; > + apss_funnel_in3: endpoint { > + remote-endpoint = > + <&etm3_out>; > + }; > + }; > + > + port@4 { > + reg = <4>; > + apss_funnel_in4: endpoint { > + remote-endpoint = > + <&etm4_out>; > + }; > + }; > + > + port@5 { > + reg = <5>; > + apss_funnel_in5: endpoint { > + remote-endpoint = > + <&etm5_out>; > + }; > + }; > + > + port@6 { > + reg = <6>; > + apss_funnel_in6: endpoint { > + remote-endpoint = > + <&etm6_out>; > + }; > + }; > + > + port@7 { > + reg = <7>; > + apss_funnel_in7: endpoint { > + remote-endpoint = > + <&etm7_out>; > + }; > + }; > + }; > + }; > + > + funnel@7810000 { > + compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; > + reg = <0 0x07810000 0 0x1000>; > + > + clocks = <&aoss_qmp>; > + clock-names = "apb_pclk"; > + > + out-ports { > + port { > + apss_merge_funnel_out: endpoint { > + remote-endpoint = > + <&funnel2_in5>; > + }; > + }; > + }; > + > + in-ports { > + port { > + apss_merge_funnel_in: endpoint { > + remote-endpoint = > + <&apss_funnel_out>; > + }; > + }; > + }; > + }; > }; > > &adsp { ^ permalink raw reply [flat|nested] 9+ messages in thread
* [PATCH v2 0/2] Add Coresight support for RB5 board @ 2021-09-13 6:40 Tao Zhang 2021-09-13 6:40 ` [PATCH v2 1/2] coresight: etm4x: Add ETM PID for Kryo-5XX Tao Zhang 0 siblings, 1 reply; 9+ messages in thread From: Tao Zhang @ 2021-09-13 6:40 UTC (permalink / raw) To: Mathieu Poirier, Suzuki K Poulose, Alexander Shishkin Cc: Tao Zhang, Mike Leach, Leo Yan, Greg Kroah-Hartman, coresight, linux-arm-kernel, linux-kernel, Tingwei Zhang, Mao Jinlong, Yuanfang Zhang This series adds Coresight support for SM8250 Soc on RB5 board. It is composed of two elements. a) Add ETM PID for Kryo-5XX. b) Add coresight support to DTS for RB5. This series applies to coresight/next https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git Tao Zhang (2): coresight: etm4x: Add ETM PID for Kryo-5XX arm64: dts: qcom: sm8250: Add Coresight support arch/arm64/boot/dts/qcom/qrb5165-rb5.dts | 442 +++++++++++++++++- .../coresight/coresight-etm4x-core.c | 1 + 2 files changed, 439 insertions(+), 4 deletions(-) -- The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project ^ permalink raw reply [flat|nested] 9+ messages in thread
* [PATCH v2 1/2] coresight: etm4x: Add ETM PID for Kryo-5XX 2021-09-13 6:40 [PATCH v2 0/2] Add Coresight support for RB5 board Tao Zhang @ 2021-09-13 6:40 ` Tao Zhang 2021-09-21 16:29 ` Suzuki K Poulose 0 siblings, 1 reply; 9+ messages in thread From: Tao Zhang @ 2021-09-13 6:40 UTC (permalink / raw) To: Mathieu Poirier, Suzuki K Poulose, Alexander Shishkin Cc: Tao Zhang, Mike Leach, Leo Yan, Greg Kroah-Hartman, coresight, linux-arm-kernel, linux-kernel, Tingwei Zhang, Mao Jinlong, Yuanfang Zhang Add ETM PID for Kryo-5XX to the list of supported ETMs. Otherwise, Kryo-5XX ETMs will not be initialized successfully. e.g. This change can be verified on qrb5165-rb5 board. ETM4-ETM7 nodes will not be visible without this change. Signed-off-by: Tao Zhang <quic_taozha@quicinc.com> --- drivers/hwtracing/coresight/coresight-etm4x-core.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c b/drivers/hwtracing/coresight/coresight-etm4x-core.c index da27cd4a3c38..52ca918c3bec 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x-core.c +++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c @@ -2065,6 +2065,7 @@ static const struct amba_id etm4_ids[] = { CS_AMBA_UCI_ID(0x000bb803, uci_id_etm4),/* Qualcomm Kryo 385 Cortex-A75 */ CS_AMBA_UCI_ID(0x000bb805, uci_id_etm4),/* Qualcomm Kryo 4XX Cortex-A55 */ CS_AMBA_UCI_ID(0x000bb804, uci_id_etm4),/* Qualcomm Kryo 4XX Cortex-A76 */ + CS_AMBA_UCI_ID(0x000bbd0d, uci_id_etm4),/* Qualcomm Kryo 5XX Cortex-A77 */ CS_AMBA_UCI_ID(0x000cc0af, uci_id_etm4),/* Marvell ThunderX2 */ CS_AMBA_UCI_ID(0x000b6d01, uci_id_etm4),/* HiSilicon-Hip08 */ CS_AMBA_UCI_ID(0x000b6d02, uci_id_etm4),/* HiSilicon-Hip09 */ -- The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project ^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH v2 1/2] coresight: etm4x: Add ETM PID for Kryo-5XX 2021-09-13 6:40 ` [PATCH v2 1/2] coresight: etm4x: Add ETM PID for Kryo-5XX Tao Zhang @ 2021-09-21 16:29 ` Suzuki K Poulose 0 siblings, 0 replies; 9+ messages in thread From: Suzuki K Poulose @ 2021-09-21 16:29 UTC (permalink / raw) To: Tao Zhang, Mathieu Poirier, Alexander Shishkin Cc: Mike Leach, Leo Yan, Greg Kroah-Hartman, coresight, linux-arm-kernel, linux-kernel, Tingwei Zhang, Mao Jinlong, Yuanfang Zhang On 13/09/2021 07:40, Tao Zhang wrote: > Add ETM PID for Kryo-5XX to the list of supported ETMs. > Otherwise, Kryo-5XX ETMs will not be initialized successfully. > e.g. > This change can be verified on qrb5165-rb5 board. ETM4-ETM7 nodes > will not be visible without this change. > > Signed-off-by: Tao Zhang <quic_taozha@quicinc.com> Reviewed-by: Suzuki K Poulose <suzuki.poulose@arm.com> > --- > drivers/hwtracing/coresight/coresight-etm4x-core.c | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c b/drivers/hwtracing/coresight/coresight-etm4x-core.c > index da27cd4a3c38..52ca918c3bec 100644 > --- a/drivers/hwtracing/coresight/coresight-etm4x-core.c > +++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c > @@ -2065,6 +2065,7 @@ static const struct amba_id etm4_ids[] = { > CS_AMBA_UCI_ID(0x000bb803, uci_id_etm4),/* Qualcomm Kryo 385 Cortex-A75 */ > CS_AMBA_UCI_ID(0x000bb805, uci_id_etm4),/* Qualcomm Kryo 4XX Cortex-A55 */ > CS_AMBA_UCI_ID(0x000bb804, uci_id_etm4),/* Qualcomm Kryo 4XX Cortex-A76 */ > + CS_AMBA_UCI_ID(0x000bbd0d, uci_id_etm4),/* Qualcomm Kryo 5XX Cortex-A77 */ > CS_AMBA_UCI_ID(0x000cc0af, uci_id_etm4),/* Marvell ThunderX2 */ > CS_AMBA_UCI_ID(0x000b6d01, uci_id_etm4),/* HiSilicon-Hip08 */ > CS_AMBA_UCI_ID(0x000b6d02, uci_id_etm4),/* HiSilicon-Hip09 */ > ^ permalink raw reply [flat|nested] 9+ messages in thread
end of thread, other threads:[~2022-08-11 9:26 UTC | newest] Thread overview: 9+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2021-09-24 10:06 [PATCH v2 0/2] Add Coresight support for RB5 board Tao Zhang 2021-09-24 10:06 ` [PATCH v2 1/2] coresight: etm4x: Add ETM PID for Kryo-5XX Tao Zhang 2021-09-24 13:17 ` Suzuki K Poulose 2021-09-24 10:06 ` [PATCH v2 2/2] arm64: dts: qcom: sm8250: Add Coresight support Tao Zhang 2021-09-24 13:11 ` Suzuki K Poulose 2021-09-27 2:42 ` Tao Zhang 2022-08-11 9:25 ` Anshuman Khandual -- strict thread matches above, loose matches on Subject: below -- 2021-09-13 6:40 [PATCH v2 0/2] Add Coresight support for RB5 board Tao Zhang 2021-09-13 6:40 ` [PATCH v2 1/2] coresight: etm4x: Add ETM PID for Kryo-5XX Tao Zhang 2021-09-21 16:29 ` Suzuki K Poulose
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