[PATCH 0/2] clk: qcom: nord: fix PHY pipe clock halt check and mux ops

[PATCH 0/2] clk: qcom: nord: fix PHY pipe clock halt check and mux ops

[Taniya Das]

Fix two PHY pipe clock issues in the Nord GCC/NE_GCC drivers: the
PCIe and USB3 pipe clock branches poll BRANCH_HALT_VOTED, which can
spuriously time out since the halt bit doesn't toggle reliably while
the PHY is down. The USB3 pipe clock source muxes use
clk_regmap_mux_closest_ops, which doesn't park on the reference clock
when disabled. Switch the branches to BRANCH_HALT_SKIP and convert
the muxes to clk_regmap_phy_mux_ops, matching existing conventions
elsewhere in the Qualcomm clock drivers.

Signed-off-by: Taniya Das <taniya.das@oss.qualcomm.com>
---
Taniya Das (2):
      clk: qcom: nord: use BRANCH_HALT_SKIP for PHY pipe clocks
      clk: qcom: negcc-nord: use clk_regmap_phy_mux for USB3 pipe clock srcs

 drivers/clk/qcom/gcc-nord.c   |  8 +++----
 drivers/clk/qcom/negcc-nord.c | 53 ++++++++++++-------------------------------
 2 files changed, 18 insertions(+), 43 deletions(-)
---
base-commit: b8809969e1d7a591e0f49dd464a5d04b3cf02ab1
change-id: 20260716-b4-nord-pipe-clk-fixes-e221e57f5600

Best regards,
-- 
Taniya Das <taniya.das@oss.qualcomm.com>

[PATCH 1/2] clk: qcom: nord: use BRANCH_HALT_SKIP for PHY pipe clocks

[Taniya Das]

The PCIe and USB3 pipe clocks on Nord are sourced from their
respective PHYs. The halt bit for these branches does not toggle
reliably when the PHY is powered down or not yet brought up, so
polling for it with BRANCH_HALT_VOTED can spuriously time out.

Switch these pipe clock branches to BRANCH_HALT_SKIP, matching the
convention used for PHY-sourced pipe clocks elsewhere in the Qualcomm
clock drivers.

Fixes: a4f780cd5c7a ("clk: qcom: gcc: Add multiple global clock controller driver for Nord SoC")
Signed-off-by: Taniya Das <taniya.das@oss.qualcomm.com>
---
 drivers/clk/qcom/gcc-nord.c   | 8 ++++----
 drivers/clk/qcom/negcc-nord.c | 4 ++--
 2 files changed, 6 insertions(+), 6 deletions(-)

diff --git a/drivers/clk/qcom/gcc-nord.c b/drivers/clk/qcom/gcc-nord.c
index 7c7c2171ac965f396a000f34dcc15a3ba185a386..970a3e1a5864aad98f3cd3efb08efc429c65e94b 100644
--- a/drivers/clk/qcom/gcc-nord.c
+++ b/drivers/clk/qcom/gcc-nord.c
@@ -701,7 +701,7 @@ static struct clk_branch gcc_pcie_a_phy_rchng_clk = {
 
 static struct clk_branch gcc_pcie_a_pipe_clk = {
 	.halt_reg = 0x49068,
-	.halt_check = BRANCH_HALT_VOTED,
+	.halt_check = BRANCH_HALT_SKIP,
 	.hwcg_reg = 0x49068,
 	.hwcg_bit = 1,
 	.clkr = {
@@ -850,7 +850,7 @@ static struct clk_branch gcc_pcie_b_phy_rchng_clk = {
 
 static struct clk_branch gcc_pcie_b_pipe_clk = {
 	.halt_reg = 0x4a068,
-	.halt_check = BRANCH_HALT_VOTED,
+	.halt_check = BRANCH_HALT_SKIP,
 	.clkr = {
 		.enable_reg = 0x9d008,
 		.enable_mask = BIT(24),
@@ -995,7 +995,7 @@ static struct clk_branch gcc_pcie_c_phy_rchng_clk = {
 
 static struct clk_branch gcc_pcie_c_pipe_clk = {
 	.halt_reg = 0x4b068,
-	.halt_check = BRANCH_HALT_VOTED,
+	.halt_check = BRANCH_HALT_SKIP,
 	.clkr = {
 		.enable_reg = 0x9d010,
 		.enable_mask = BIT(1),
@@ -1140,7 +1140,7 @@ static struct clk_branch gcc_pcie_d_phy_rchng_clk = {
 
 static struct clk_branch gcc_pcie_d_pipe_clk = {
 	.halt_reg = 0x4c068,
-	.halt_check = BRANCH_HALT_VOTED,
+	.halt_check = BRANCH_HALT_SKIP,
 	.clkr = {
 		.enable_reg = 0x9d010,
 		.enable_mask = BIT(10),
diff --git a/drivers/clk/qcom/negcc-nord.c b/drivers/clk/qcom/negcc-nord.c
index 355850a875acb0973fbbc3865f83d6e4df4c62fe..3427a0375373c6843fd6bb02e0e05e51380b15ab 100644
--- a/drivers/clk/qcom/negcc-nord.c
+++ b/drivers/clk/qcom/negcc-nord.c
@@ -1641,7 +1641,7 @@ static struct clk_branch ne_gcc_usb3_prim_phy_com_aux_clk = {
 
 static struct clk_branch ne_gcc_usb3_prim_phy_pipe_clk = {
 	.halt_reg = 0x2a074,
-	.halt_check = BRANCH_HALT_VOTED,
+	.halt_check = BRANCH_HALT_SKIP,
 	.hwcg_reg = 0x2a074,
 	.hwcg_bit = 1,
 	.clkr = {
@@ -1697,7 +1697,7 @@ static struct clk_branch ne_gcc_usb3_sec_phy_com_aux_clk = {
 
 static struct clk_branch ne_gcc_usb3_sec_phy_pipe_clk = {
 	.halt_reg = 0x2c074,
-	.halt_check = BRANCH_HALT_VOTED,
+	.halt_check = BRANCH_HALT_SKIP,
 	.hwcg_reg = 0x2c074,
 	.hwcg_bit = 1,
 	.clkr = {

-- 
2.34.1

Re: [PATCH 1/2] clk: qcom: nord: use BRANCH_HALT_SKIP for PHY pipe clocks

[Konrad Dybcio]

On 7/16/26 12:59 PM, Taniya Das wrote:
> The PCIe and USB3 pipe clocks on Nord are sourced from their
> respective PHYs. The halt bit for these branches does not toggle
> reliably when the PHY is powered down or not yet brought up, so
> polling for it with BRANCH_HALT_VOTED can spuriously time out.
> 
> Switch these pipe clock branches to BRANCH_HALT_SKIP, matching the
> convention used for PHY-sourced pipe clocks elsewhere in the Qualcomm
> clock drivers.
> 
> Fixes: a4f780cd5c7a ("clk: qcom: gcc: Add multiple global clock controller driver for Nord SoC")
> Signed-off-by: Taniya Das <taniya.das@oss.qualcomm.com>
> ---

Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>

Konrad

Re: [PATCH 1/2] clk: qcom: nord: use BRANCH_HALT_SKIP for PHY pipe clocks

[Shawn Guo]

On Thu, Jul 16, 2026 at 04:29:11PM +0530, Taniya Das wrote:
> The PCIe and USB3 pipe clocks on Nord are sourced from their
> respective PHYs. The halt bit for these branches does not toggle
> reliably when the PHY is powered down or not yet brought up, so
> polling for it with BRANCH_HALT_VOTED can spuriously time out.
> 
> Switch these pipe clock branches to BRANCH_HALT_SKIP, matching the
> convention used for PHY-sourced pipe clocks elsewhere in the Qualcomm
> clock drivers.
> 
> Fixes: a4f780cd5c7a ("clk: qcom: gcc: Add multiple global clock controller driver for Nord SoC")
> Signed-off-by: Taniya Das <taniya.das@oss.qualcomm.com>

For USB3,

Tested-by: Shawn Guo <shengchao.guo@oss.qualcomm.com>

[PATCH 2/2] clk: qcom: negcc-nord: use clk_regmap_phy_mux for USB3 pipe clock srcs

[Taniya Das]

ne_gcc_usb3_prim_phy_pipe_clk_src and ne_gcc_usb3_sec_phy_pipe_clk_src
are 2-bit muxes selecting between a PHY-sourced USB3 pipe clock and
BI_TCXO, implemented with clk_regmap_mux_closest_ops. This requires
manual parent switching and does not park the mux on the reference
clock when the clock is disabled.

Convert both to clk_regmap_phy_mux with clk_regmap_phy_mux_ops, which
automatically parks the mux on the XO/ref source on disable and
restores the PHY parent on enable, matching the existing UFS symbol
clock conversions in this driver.

Fixes: a4f780cd5c7a ("clk: qcom: gcc: Add multiple global clock controller driver for Nord SoC")
Signed-off-by: Taniya Das <taniya.das@oss.qualcomm.com>
---
 drivers/clk/qcom/negcc-nord.c | 49 +++++++++++--------------------------------
 1 file changed, 12 insertions(+), 37 deletions(-)

diff --git a/drivers/clk/qcom/negcc-nord.c b/drivers/clk/qcom/negcc-nord.c
index 3427a0375373c6843fd6bb02e0e05e51380b15ab..57b90f11bc06834a68adb3bac9911967ffa60d55 100644
--- a/drivers/clk/qcom/negcc-nord.c
+++ b/drivers/clk/qcom/negcc-nord.c
@@ -16,7 +16,6 @@
 #include "clk-rcg.h"
 #include "clk-regmap.h"
 #include "clk-regmap-divider.h"
-#include "clk-regmap-mux.h"
 #include "clk-regmap-phy-mux.h"
 #include "common.h"
 #include "gdsc.h"
@@ -41,8 +40,6 @@ enum {
 	P_UFS_PHY_RX_SYMBOL_0_CLK,
 	P_UFS_PHY_RX_SYMBOL_1_CLK,
 	P_UFS_PHY_TX_SYMBOL_0_CLK,
-	P_USB3_PHY_SEC_WRAPPER_NE_GCC_USB31_PIPE_CLK,
-	P_USB3_PHY_WRAPPER_NE_GCC_USB31_PIPE_CLK,
 };
 
 static struct clk_alpha_pll ne_gcc_gpll0 = {
@@ -165,26 +162,6 @@ static const struct clk_parent_data ne_gcc_parent_data_5[] = {
 	{ .index = DT_BI_TCXO },
 };
 
-static const struct parent_map ne_gcc_parent_map_6[] = {
-	{ P_USB3_PHY_WRAPPER_NE_GCC_USB31_PIPE_CLK, 0 },
-	{ P_BI_TCXO, 2 },
-};
-
-static const struct clk_parent_data ne_gcc_parent_data_6[] = {
-	{ .index = DT_USB3_PHY_WRAPPER_NE_GCC_USB31_PIPE_CLK },
-	{ .index = DT_BI_TCXO },
-};
-
-static const struct parent_map ne_gcc_parent_map_7[] = {
-	{ P_USB3_PHY_SEC_WRAPPER_NE_GCC_USB31_PIPE_CLK, 0 },
-	{ P_BI_TCXO, 2 },
-};
-
-static const struct clk_parent_data ne_gcc_parent_data_7[] = {
-	{ .index = DT_USB3_PHY_SEC_WRAPPER_NE_GCC_USB31_PIPE_CLK },
-	{ .index = DT_BI_TCXO },
-};
-
 static struct clk_regmap_phy_mux ne_gcc_ufs_phy_rx_symbol_0_clk_src = {
 	.reg = 0x33068,
 	.clkr = {
@@ -227,32 +204,30 @@ static struct clk_regmap_phy_mux ne_gcc_ufs_phy_tx_symbol_0_clk_src = {
 	},
 };
 
-static struct clk_regmap_mux ne_gcc_usb3_prim_phy_pipe_clk_src = {
+static struct clk_regmap_phy_mux ne_gcc_usb3_prim_phy_pipe_clk_src = {
 	.reg = 0x2a078,
-	.shift = 0,
-	.width = 2,
-	.parent_map = ne_gcc_parent_map_6,
 	.clkr = {
 		.hw.init = &(const struct clk_init_data) {
 			.name = "ne_gcc_usb3_prim_phy_pipe_clk_src",
-			.parent_data = ne_gcc_parent_data_6,
-			.num_parents = ARRAY_SIZE(ne_gcc_parent_data_6),
-			.ops = &clk_regmap_mux_closest_ops,
+			.parent_data = &(const struct clk_parent_data){
+				.index = DT_USB3_PHY_WRAPPER_NE_GCC_USB31_PIPE_CLK,
+			},
+			.num_parents = 1,
+			.ops = &clk_regmap_phy_mux_ops,
 		},
 	},
 };
 
-static struct clk_regmap_mux ne_gcc_usb3_sec_phy_pipe_clk_src = {
+static struct clk_regmap_phy_mux ne_gcc_usb3_sec_phy_pipe_clk_src = {
 	.reg = 0x2c078,
-	.shift = 0,
-	.width = 2,
-	.parent_map = ne_gcc_parent_map_7,
 	.clkr = {
 		.hw.init = &(const struct clk_init_data) {
 			.name = "ne_gcc_usb3_sec_phy_pipe_clk_src",
-			.parent_data = ne_gcc_parent_data_7,
-			.num_parents = ARRAY_SIZE(ne_gcc_parent_data_7),
-			.ops = &clk_regmap_mux_closest_ops,
+			.parent_data = &(const struct clk_parent_data){
+				.index = DT_USB3_PHY_SEC_WRAPPER_NE_GCC_USB31_PIPE_CLK,
+			},
+			.num_parents = 1,
+			.ops = &clk_regmap_phy_mux_ops,
 		},
 	},
 };

-- 
2.34.1

Re: [PATCH 2/2] clk: qcom: negcc-nord: use clk_regmap_phy_mux for USB3 pipe clock srcs

[Konrad Dybcio]

On 7/16/26 12:59 PM, Taniya Das wrote:
> ne_gcc_usb3_prim_phy_pipe_clk_src and ne_gcc_usb3_sec_phy_pipe_clk_src
> are 2-bit muxes selecting between a PHY-sourced USB3 pipe clock and
> BI_TCXO, implemented with clk_regmap_mux_closest_ops. This requires
> manual parent switching and does not park the mux on the reference
> clock when the clock is disabled.
> 
> Convert both to clk_regmap_phy_mux with clk_regmap_phy_mux_ops, which
> automatically parks the mux on the XO/ref source on disable and
> restores the PHY parent on enable, matching the existing UFS symbol
> clock conversions in this driver.
> 
> Fixes: a4f780cd5c7a ("clk: qcom: gcc: Add multiple global clock controller driver for Nord SoC")
> Signed-off-by: Taniya Das <taniya.das@oss.qualcomm.com>
> ---

Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>

Konrad

Re: [PATCH 2/2] clk: qcom: negcc-nord: use clk_regmap_phy_mux for USB3 pipe clock srcs

[Shawn Guo]

On Thu, Jul 16, 2026 at 04:29:12PM +0530, Taniya Das wrote:
> ne_gcc_usb3_prim_phy_pipe_clk_src and ne_gcc_usb3_sec_phy_pipe_clk_src
> are 2-bit muxes selecting between a PHY-sourced USB3 pipe clock and
> BI_TCXO, implemented with clk_regmap_mux_closest_ops. This requires
> manual parent switching and does not park the mux on the reference
> clock when the clock is disabled.
> 
> Convert both to clk_regmap_phy_mux with clk_regmap_phy_mux_ops, which
> automatically parks the mux on the XO/ref source on disable and
> restores the PHY parent on enable, matching the existing UFS symbol
> clock conversions in this driver.
> 
> Fixes: a4f780cd5c7a ("clk: qcom: gcc: Add multiple global clock controller driver for Nord SoC")
> Signed-off-by: Taniya Das <taniya.das@oss.qualcomm.com>

Tested-by: Shawn Guo <shengchao.guo@oss.qualcomm.com>

Re: [PATCH 0/2] clk: qcom: nord: fix PHY pipe clock halt check and mux ops

[Bjorn Andersson]

On Thu, 16 Jul 2026 16:29:10 +0530, Taniya Das wrote:
> Fix two PHY pipe clock issues in the Nord GCC/NE_GCC drivers: the
> PCIe and USB3 pipe clock branches poll BRANCH_HALT_VOTED, which can
> spuriously time out since the halt bit doesn't toggle reliably while
> the PHY is down. The USB3 pipe clock source muxes use
> clk_regmap_mux_closest_ops, which doesn't park on the reference clock
> when disabled. Switch the branches to BRANCH_HALT_SKIP and convert
> the muxes to clk_regmap_phy_mux_ops, matching existing conventions
> elsewhere in the Qualcomm clock drivers.
> 
> [...]

Applied, thanks!

[1/2] clk: qcom: nord: use BRANCH_HALT_SKIP for PHY pipe clocks
      commit: 3a8a7d597b07ffe388b47fb524827be52c9f7e0f
[2/2] clk: qcom: negcc-nord: use clk_regmap_phy_mux for USB3 pipe clock srcs
      commit: a5c2859ffe9c8e033e2df1ef62357fa5692008f1

Best regards,
-- 
Bjorn Andersson <andersson@kernel.org>