* [PATCH] gpu: drm: mediatek: correct clk setting AUX_RX_UI_CNT_THR_AUX_FOR_26M
@ 2025-08-18 8:34 payne.lin
2025-11-19 7:24 ` CK Hu (胡俊光)
0 siblings, 1 reply; 6+ messages in thread
From: payne.lin @ 2025-08-18 8:34 UTC (permalink / raw)
To: Chun-Kuang Hu, Philipp Zabel, David Airlie, Simona Vetter,
Matthias Brugger,
AngeloGioacchino Del Regno --cc=dri-devel @ lists . freedesktop
. org
Cc: linux-mediatek, linux-kernel, linux-arm-kernel, Bincai Liu, Payne Lin
From: Bincai Liu <bincai.liu@mediatek.com>
Updated the definition of AUX_RX_UI_CNT_THR_AUX_FOR_26M from 13 to 14.
No other code or logic changes were made; only the macro value was modified.
This change affects the timing configuration for AUX RX at 26MHz.
The formula is xtal_clk / 2 + 1.
Signed-off-by: Bincai Liu <bincai.liu@mediatek.com>
Signed-off-by: Payne Lin <payne.lin@mediatek.com>
---
drivers/gpu/drm/mediatek/mtk_dp_reg.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/mediatek/mtk_dp_reg.h b/drivers/gpu/drm/mediatek/mtk_dp_reg.h
index 8ad7a9cc259e..f8c7b3c0935f 100644
--- a/drivers/gpu/drm/mediatek/mtk_dp_reg.h
+++ b/drivers/gpu/drm/mediatek/mtk_dp_reg.h
@@ -301,7 +301,7 @@
#define AUX_TIMEOUT_THR_AUX_TX_P0_VAL 0x1595
#define MTK_DP_AUX_P0_3614 0x3614
#define AUX_RX_UI_CNT_THR_AUX_TX_P0_MASK GENMASK(6, 0)
-#define AUX_RX_UI_CNT_THR_AUX_FOR_26M 13
+#define AUX_RX_UI_CNT_THR_AUX_FOR_26M 14
#define MTK_DP_AUX_P0_3618 0x3618
#define AUX_RX_FIFO_FULL_AUX_TX_P0_MASK BIT(9)
#define AUX_RX_FIFO_WRITE_POINTER_AUX_TX_P0_MASK GENMASK(3, 0)
--
2.45.2
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH] gpu: drm: mediatek: correct clk setting AUX_RX_UI_CNT_THR_AUX_FOR_26M
2025-08-18 8:34 [PATCH] gpu: drm: mediatek: correct clk setting AUX_RX_UI_CNT_THR_AUX_FOR_26M payne.lin
@ 2025-11-19 7:24 ` CK Hu (胡俊光)
0 siblings, 0 replies; 6+ messages in thread
From: CK Hu (胡俊光) @ 2025-11-19 7:24 UTC (permalink / raw)
To: p.zabel, Payne Lin (林于平),
chunkuang.hu, AngeloGioacchino Del Regno, airlied, matthias.bgg,
simona
Cc: linux-arm-kernel, linux-mediatek,
Bincai Liu (刘彬才),
linux-kernel
On Mon, 2025-08-18 at 16:34 +0800, payne.lin wrote:
> From: Bincai Liu <bincai.liu@mediatek.com>
>
> Updated the definition of AUX_RX_UI_CNT_THR_AUX_FOR_26M from 13 to 14.
> No other code or logic changes were made; only the macro value was modified.
> This change affects the timing configuration for AUX RX at 26MHz.
> The formula is xtal_clk / 2 + 1.
I still don't understand why need this patch.
If it fix a bug, describe what the bug is.
If it provide more stability, describe what's the difference of 13 and 14.
You just show a formula xtal_clk / 2 + 1, but what's the relation with the value 13 and 14?
Regards,
CK
>
> Signed-off-by: Bincai Liu <bincai.liu@mediatek.com>
> Signed-off-by: Payne Lin <payne.lin@mediatek.com>
> ---
> drivers/gpu/drm/mediatek/mtk_dp_reg.h | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/mediatek/mtk_dp_reg.h b/drivers/gpu/drm/mediatek/mtk_dp_reg.h
> index 8ad7a9cc259e..f8c7b3c0935f 100644
> --- a/drivers/gpu/drm/mediatek/mtk_dp_reg.h
> +++ b/drivers/gpu/drm/mediatek/mtk_dp_reg.h
> @@ -301,7 +301,7 @@
> #define AUX_TIMEOUT_THR_AUX_TX_P0_VAL 0x1595
> #define MTK_DP_AUX_P0_3614 0x3614
> #define AUX_RX_UI_CNT_THR_AUX_TX_P0_MASK GENMASK(6, 0)
> -#define AUX_RX_UI_CNT_THR_AUX_FOR_26M 13
> +#define AUX_RX_UI_CNT_THR_AUX_FOR_26M 14
> #define MTK_DP_AUX_P0_3618 0x3618
> #define AUX_RX_FIFO_FULL_AUX_TX_P0_MASK BIT(9)
> #define AUX_RX_FIFO_WRITE_POINTER_AUX_TX_P0_MASK GENMASK(3, 0)
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH] gpu: drm: mediatek: correct clk setting AUX_RX_UI_CNT_THR_AUX_FOR_26M
2025-08-18 8:42 payne.lin
@ 2025-08-19 6:01 ` Fei Shao
0 siblings, 0 replies; 6+ messages in thread
From: Fei Shao @ 2025-08-19 6:01 UTC (permalink / raw)
To: payne.lin
Cc: Chun-Kuang Hu, Philipp Zabel, David Airlie, Simona Vetter,
Matthias Brugger, AngeloGioacchino Del Regno, dri-devel,
linux-mediatek, linux-kernel, linux-arm-kernel,
Project_Global_Chrome_Upstream_Group, sirius.wang, vince-wl.liu,
jh.hsu, Bincai Liu
On Mon, Aug 18, 2025 at 9:37 PM payne.lin <payne.lin@mediatek.com> wrote:
>
Start the patch title with "drm/mediatek: ".
> From: Bincai Liu <bincai.liu@mediatek.com>
>
> Updated the definition of AUX_RX_UI_CNT_THR_AUX_FOR_26M from 13 to 14.
> No other code or logic changes were made; only the macro value was modified.
> This change affects the timing configuration for AUX RX at 26MHz.
> The formula is xtal_clk / 2 + 1.
The datasheet says "It should be set to the ratio of the half cycle
XTAL clock to the 1MHz clock.", which doesn't align with your formula,
so please explain (1) why this is needed and (2) whether it's tested
on any MT8195 or MT8188 based devices, in the commit message.
Also, you'll need a "Fixes:" tag[1] if this fixes a bug.
Regards,
Fei
[1]: https://www.kernel.org/doc/html/latest/process/submitting-patches.html#describe-your-changes
>
> Signed-off-by: Bincai Liu <bincai.liu@mediatek.com>
> Signed-off-by: Payne Lin <payne.lin@mediatek.com>
> ---
> drivers/gpu/drm/mediatek/mtk_dp_reg.h | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/mediatek/mtk_dp_reg.h b/drivers/gpu/drm/mediatek/mtk_dp_reg.h
> index 8ad7a9cc259e..f8c7b3c0935f 100644
> --- a/drivers/gpu/drm/mediatek/mtk_dp_reg.h
> +++ b/drivers/gpu/drm/mediatek/mtk_dp_reg.h
> @@ -301,7 +301,7 @@
> #define AUX_TIMEOUT_THR_AUX_TX_P0_VAL 0x1595
> #define MTK_DP_AUX_P0_3614 0x3614
> #define AUX_RX_UI_CNT_THR_AUX_TX_P0_MASK GENMASK(6, 0)
> -#define AUX_RX_UI_CNT_THR_AUX_FOR_26M 13
> +#define AUX_RX_UI_CNT_THR_AUX_FOR_26M 14
> #define MTK_DP_AUX_P0_3618 0x3618
> #define AUX_RX_FIFO_FULL_AUX_TX_P0_MASK BIT(9)
> #define AUX_RX_FIFO_WRITE_POINTER_AUX_TX_P0_MASK GENMASK(3, 0)
> --
> 2.45.2
>
>
^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH] gpu: drm: mediatek: correct clk setting AUX_RX_UI_CNT_THR_AUX_FOR_26M
@ 2025-08-18 8:42 payne.lin
2025-08-19 6:01 ` Fei Shao
0 siblings, 1 reply; 6+ messages in thread
From: payne.lin @ 2025-08-18 8:42 UTC (permalink / raw)
To: Chun-Kuang Hu, Philipp Zabel, David Airlie, Simona Vetter,
Matthias Brugger, AngeloGioacchino Del Regno
Cc: dri-devel, linux-mediatek, linux-kernel, linux-arm-kernel,
Project_Global_Chrome_Upstream_Group, sirius.wang, vince-wl.liu,
jh.hsu, Bincai Liu, Payne Lin
From: Bincai Liu <bincai.liu@mediatek.com>
Updated the definition of AUX_RX_UI_CNT_THR_AUX_FOR_26M from 13 to 14.
No other code or logic changes were made; only the macro value was modified.
This change affects the timing configuration for AUX RX at 26MHz.
The formula is xtal_clk / 2 + 1.
Signed-off-by: Bincai Liu <bincai.liu@mediatek.com>
Signed-off-by: Payne Lin <payne.lin@mediatek.com>
---
drivers/gpu/drm/mediatek/mtk_dp_reg.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/mediatek/mtk_dp_reg.h b/drivers/gpu/drm/mediatek/mtk_dp_reg.h
index 8ad7a9cc259e..f8c7b3c0935f 100644
--- a/drivers/gpu/drm/mediatek/mtk_dp_reg.h
+++ b/drivers/gpu/drm/mediatek/mtk_dp_reg.h
@@ -301,7 +301,7 @@
#define AUX_TIMEOUT_THR_AUX_TX_P0_VAL 0x1595
#define MTK_DP_AUX_P0_3614 0x3614
#define AUX_RX_UI_CNT_THR_AUX_TX_P0_MASK GENMASK(6, 0)
-#define AUX_RX_UI_CNT_THR_AUX_FOR_26M 13
+#define AUX_RX_UI_CNT_THR_AUX_FOR_26M 14
#define MTK_DP_AUX_P0_3618 0x3618
#define AUX_RX_FIFO_FULL_AUX_TX_P0_MASK BIT(9)
#define AUX_RX_FIFO_WRITE_POINTER_AUX_TX_P0_MASK GENMASK(3, 0)
--
2.45.2
^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH] gpu: drm: mediatek: correct clk setting AUX_RX_UI_CNT_THR_AUX_FOR_26M
@ 2025-08-18 8:40 payne.lin
0 siblings, 0 replies; 6+ messages in thread
From: payne.lin @ 2025-08-18 8:40 UTC (permalink / raw)
To: Chun-Kuang Hu, Philipp Zabel, David Airlie, Simona Vetter,
Matthias Brugger, AngeloGioacchino Del Regno
Cc: dri-devel, linux-mediatek, linux-kernel, linux-arm-kernel,
Bincai Liu, Payne Lin
From: Bincai Liu <bincai.liu@mediatek.com>
Updated the definition of AUX_RX_UI_CNT_THR_AUX_FOR_26M from 13 to 14.
No other code or logic changes were made; only the macro value was modified.
This change affects the timing configuration for AUX RX at 26MHz.
The formula is xtal_clk / 2 + 1.
Signed-off-by: Bincai Liu <bincai.liu@mediatek.com>
Signed-off-by: Payne Lin <payne.lin@mediatek.com>
---
drivers/gpu/drm/mediatek/mtk_dp_reg.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/mediatek/mtk_dp_reg.h b/drivers/gpu/drm/mediatek/mtk_dp_reg.h
index 8ad7a9cc259e..f8c7b3c0935f 100644
--- a/drivers/gpu/drm/mediatek/mtk_dp_reg.h
+++ b/drivers/gpu/drm/mediatek/mtk_dp_reg.h
@@ -301,7 +301,7 @@
#define AUX_TIMEOUT_THR_AUX_TX_P0_VAL 0x1595
#define MTK_DP_AUX_P0_3614 0x3614
#define AUX_RX_UI_CNT_THR_AUX_TX_P0_MASK GENMASK(6, 0)
-#define AUX_RX_UI_CNT_THR_AUX_FOR_26M 13
+#define AUX_RX_UI_CNT_THR_AUX_FOR_26M 14
#define MTK_DP_AUX_P0_3618 0x3618
#define AUX_RX_FIFO_FULL_AUX_TX_P0_MASK BIT(9)
#define AUX_RX_FIFO_WRITE_POINTER_AUX_TX_P0_MASK GENMASK(3, 0)
--
2.45.2
^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH] gpu: drm: mediatek: correct clk setting AUX_RX_UI_CNT_THR_AUX_FOR_26M
@ 2025-08-18 8:37 payne.lin
0 siblings, 0 replies; 6+ messages in thread
From: payne.lin @ 2025-08-18 8:37 UTC (permalink / raw)
To: Chun-Kuang Hu, Philipp Zabel, David Airlie, Simona Vetter,
Matthias Brugger,
AngeloGioacchino Del Regno --cc=dri-devel @ lists . freedesktop
. org
Cc: linux-mediatek, linux-kernel, linux-arm-kernel, Bincai Liu, Payne Lin
From: Bincai Liu <bincai.liu@mediatek.com>
Updated the definition of AUX_RX_UI_CNT_THR_AUX_FOR_26M from 13 to 14.
No other code or logic changes were made; only the macro value was modified.
This change affects the timing configuration for AUX RX at 26MHz.
The formula is xtal_clk / 2 + 1.
Signed-off-by: Bincai Liu <bincai.liu@mediatek.com>
Signed-off-by: Payne Lin <payne.lin@mediatek.com>
---
drivers/gpu/drm/mediatek/mtk_dp_reg.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/mediatek/mtk_dp_reg.h b/drivers/gpu/drm/mediatek/mtk_dp_reg.h
index 8ad7a9cc259e..f8c7b3c0935f 100644
--- a/drivers/gpu/drm/mediatek/mtk_dp_reg.h
+++ b/drivers/gpu/drm/mediatek/mtk_dp_reg.h
@@ -301,7 +301,7 @@
#define AUX_TIMEOUT_THR_AUX_TX_P0_VAL 0x1595
#define MTK_DP_AUX_P0_3614 0x3614
#define AUX_RX_UI_CNT_THR_AUX_TX_P0_MASK GENMASK(6, 0)
-#define AUX_RX_UI_CNT_THR_AUX_FOR_26M 13
+#define AUX_RX_UI_CNT_THR_AUX_FOR_26M 14
#define MTK_DP_AUX_P0_3618 0x3618
#define AUX_RX_FIFO_FULL_AUX_TX_P0_MASK BIT(9)
#define AUX_RX_FIFO_WRITE_POINTER_AUX_TX_P0_MASK GENMASK(3, 0)
--
2.45.2
^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2025-11-19 7:25 UTC | newest]
Thread overview: 6+ messages (download: mbox.gz / follow: Atom feed)
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2025-08-18 8:34 [PATCH] gpu: drm: mediatek: correct clk setting AUX_RX_UI_CNT_THR_AUX_FOR_26M payne.lin
2025-11-19 7:24 ` CK Hu (胡俊光)
2025-08-18 8:37 payne.lin
2025-08-18 8:40 payne.lin
2025-08-18 8:42 payne.lin
2025-08-19 6:01 ` Fei Shao
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