From: Krzysztof Kozlowski <krzk@kernel.org>
To: Abel Vesa <abel.vesa@linaro.org>,
Bjorn Andersson <andersson@kernel.org>,
Konrad Dybcio <konradybcio@kernel.org>,
Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>,
Sibi Sankar <quic_sibis@quicinc.com>,
Rajendra Nayak <quic_rjendra@quicinc.com>
Cc: Johan Hovold <johan@kernel.org>,
linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org
Subject: Re: [PATCH] arm64: dts: qcom: x1e80100: Add HS PHY IRQs to USB1 SS[0-2]
Date: Fri, 9 Aug 2024 12:26:10 +0200 [thread overview]
Message-ID: <e10a2f4a-a02d-427a-92ab-6a3612244766@kernel.org> (raw)
In-Reply-To: <20240809-x1e80100-dts-usb-1-ss0-2-add-hs-phy-irqs-v1-1-9e1bc62fa407@linaro.org>
On 09/08/2024 12:12, Abel Vesa wrote:
> Add missing HS PHY IRQs to all 3 USB1 SS instances.
>
> Fixes: 4af46b7bd66f ("arm64: dts: qcom: x1e80100: Add USB nodes")
> Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
> ---
> arch/arm64/boot/dts/qcom/x1e80100.dtsi | 6 ++++++
> 1 file changed, 6 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/x1e80100.dtsi b/arch/arm64/boot/dts/qcom/x1e80100.dtsi
> index 326283822aee..254643650fa7 100644
> --- a/arch/arm64/boot/dts/qcom/x1e80100.dtsi
> +++ b/arch/arm64/boot/dts/qcom/x1e80100.dtsi
> @@ -3871,10 +3871,12 @@ usb_1_ss2: usb@a0f8800 {
> <200000000>;
>
> interrupts-extended = <&intc GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>,
> + <&intc GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>,
> <&pdc 58 IRQ_TYPE_EDGE_BOTH>,
> <&pdc 57 IRQ_TYPE_EDGE_BOTH>,
> <&pdc 10 IRQ_TYPE_LEVEL_HIGH>;
> interrupt-names = "pwr_event",
> + "hs_phy_irq",
I think current bindings disagree with this. If there is a binding
update, please post a link.
Best regards,
Krzysztof
prev parent reply other threads:[~2024-08-09 10:26 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-08-09 10:12 Abel Vesa
2024-08-09 10:26 ` Krzysztof Kozlowski [this message]
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