From: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
To: Xilin Wu <sophon@radxa.com>,
Bjorn Andersson <andersson@kernel.org>,
Konrad Dybcio <konradybcio@kernel.org>,
Abel Vesa <abelvesa@kernel.org>, Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>
Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org, dragon@radxa.com
Subject: Re: [PATCH] arm64: dts: qcom: sc8280xp: add missing Iris IOMMU SID
Date: Fri, 30 Oct 2026 13:54:58 +0100 [thread overview]
Message-ID: <e1d97fe8-3af1-4429-978e-9f2ce59e87b1@oss.qualcomm.com> (raw)
In-Reply-To: <20261030-sc8280xp-iris-iommu-v1-1-1e3fb8562b3d@radxa.com>
On 10/29/26 5:14 PM, Xilin Wu wrote:
> The Iris VPU on SC8280XP can issue memory transactions using stream ID
> 0x2a07. With only the 0x2a00 SID described in the IOMMU list, those
> transactions are not attached to the Iris IOMMU domain and can trigger a
> non-secure SMMU global fault during video decode.
>
> This was observed while decoding H.264, where the faulting address fell
> inside a DPB buffer mapped for the Iris device.
>
> Add the missing 0x2a07 stream ID so both Iris access paths are mapped by
> the SMMU.
>
> Note that the issue was observed using Gen2 HFI firmware.
>
> Signed-off-by: Xilin Wu <sophon@radxa.com>
> ---
Any chance you're running into this?
https://lore.kernel.org/linux-arm-msm/20260926-vpu_iommu_iova_handling-v5-0-0322ca5dc10c@oss.qualcomm.com/
Konrad
prev parent reply other threads:[~2026-10-30 12:55 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-10-29 16:14 Xilin Wu
2026-10-30 12:54 ` Konrad Dybcio [this message]
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