[PATCH 0/4] Add support for mt6878 pinctrl

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* [PATCH 0/4] Add support for mt6878 pinctrl
@ 2025-09-08 19:17 Igor Belwon
  2025-09-08 19:17 ` [PATCH 1/4] dt-bindings: pinctrl: mediatek: Document MT6878 pin controller bindings Igor Belwon
                   ` (3 more replies)
  0 siblings, 4 replies; 12+ messages in thread
From: Igor Belwon @ 2025-09-08 19:17 UTC (permalink / raw)
  To: Linus Walleij, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
	Matthias Brugger, AngeloGioacchino Del Regno, Sean Wang
  Cc: linux-gpio, devicetree, linux-kernel, linux-arm-kernel,
	linux-mediatek, Igor Belwon

Hi all,

This patchset adds support for the pin controller found in the MediaTek
MT6878 SoC. This SoC has 9 pinctrl groups, and 4 EINT controller
instances.

This SoC also uses the new "eh" bit for controlling i2c driving, support
for which is also added here.

Kind regards,
Igor

Signed-off-by: Igor Belwon <igor.belwon@mentallysanemainliners.org>
---
Igor Belwon (4):
      dt-bindings: pinctrl: mediatek: Document MT6878 pin controller bindings
      pinctrl: mediatek: Add support for eh bit
      pinctrl: mediatek: Add debounce times for MT6878
      pinctrl: mediatek: Add support for MT6878 pinctrl

 .../bindings/pinctrl/mediatek,mt6878-pinctrl.yaml  |  209 ++
 drivers/pinctrl/mediatek/Kconfig                   |   10 +
 drivers/pinctrl/mediatek/Makefile                  |    1 +
 drivers/pinctrl/mediatek/mtk-eint.c                |    5 +
 drivers/pinctrl/mediatek/mtk-eint.h                |    1 +
 drivers/pinctrl/mediatek/pinctrl-mt6878.c          | 1559 ++++++++++++++
 drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.c   |   60 +
 drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.h   |   24 +
 drivers/pinctrl/mediatek/pinctrl-mtk-mt6878.h      | 2248 ++++++++++++++++++++
 drivers/pinctrl/mediatek/pinctrl-paris.c           |   30 +-
 include/dt-bindings/pinctrl/mt6878-pinfunc.h       | 1201 +++++++++++
 11 files changed, 5342 insertions(+), 6 deletions(-)
---
base-commit: 64074b8d93abdc35ae90e38ab5135f0b13ccdf68
change-id: 20250908-mt6878-pinctrl-support-a1d117140efb

Best regards,
-- 
Igor Belwon <igor.belwon@mentallysanemainliners.org>


^ permalink raw reply	[flat|nested] 12+ messages in thread

* [PATCH 1/4] dt-bindings: pinctrl: mediatek: Document MT6878 pin controller bindings
  2025-09-08 19:17 [PATCH 0/4] Add support for mt6878 pinctrl Igor Belwon
@ 2025-09-08 19:17 ` Igor Belwon
  2025-09-09  7:37   ` Krzysztof Kozlowski
  2025-09-08 19:17 ` [PATCH 2/4] pinctrl: mediatek: Add support for eh bit Igor Belwon
                   ` (2 subsequent siblings)
  3 siblings, 1 reply; 12+ messages in thread
From: Igor Belwon @ 2025-09-08 19:17 UTC (permalink / raw)
  To: Linus Walleij, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
	Matthias Brugger, AngeloGioacchino Del Regno, Sean Wang
  Cc: linux-gpio, devicetree, linux-kernel, linux-arm-kernel,
	linux-mediatek, Igor Belwon

Add device-tree bindings for the pin controller and the EINT controller
found in the MediaTek MT6878 SoC.

Signed-off-by: Igor Belwon <igor.belwon@mentallysanemainliners.org>
---
 .../bindings/pinctrl/mediatek,mt6878-pinctrl.yaml  |  209 ++++
 include/dt-bindings/pinctrl/mt6878-pinfunc.h       | 1201 ++++++++++++++++++++
 2 files changed, 1410 insertions(+)

diff --git a/Documentation/devicetree/bindings/pinctrl/mediatek,mt6878-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/mediatek,mt6878-pinctrl.yaml
new file mode 100644
index 0000000000000000000000000000000000000000..ecd24ab23a0c41810828ddb8827ab39c4cd3d2fc
--- /dev/null
+++ b/Documentation/devicetree/bindings/pinctrl/mediatek,mt6878-pinctrl.yaml
@@ -0,0 +1,209 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pinctrl/mediatek,mt6878-pinctrl.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: MediaTek MT6878 Pin Controller
+
+maintainers:
+  - Igor Belwon <igor.belwon@mentallysanemainliners.org>
+
+description:
+  The MediaTek MT6878 Pin controller is used to control SoC pins.
+
+properties:
+  compatible:
+    const: mediatek,mt6878-pinctrl
+
+  reg:
+    items:
+      - description: pin controller base
+      - description: bl group IO
+      - description: bm group IO
+      - description: br group IO
+      - description: bl1 group IO
+      - description: br1 group IO
+      - description: lm group IO
+      - description: lt group IO
+      - description: rm group IO
+      - description: rt group IO
+      - description: EINT controller E block
+      - description: EINT controller S block
+      - description: EINT controller W block
+      - description: EINT controller C block
+
+  reg-names:
+    items:
+      - const: base
+      - const: bl
+      - const: bm
+      - const: br
+      - const: bl1
+      - const: br1
+      - const: lm
+      - const: lt
+      - const: rm
+      - const: rt
+      - const: eint-e
+      - const: eint-s
+      - const: eint-w
+      - const: eint-c
+
+  gpio-controller: true
+
+  '#gpio-cells':
+    description:
+      Number of cells in GPIO specifier. Since the generic GPIO binding is used,
+      the amount of cells must be specified as 2. See the below mentioned gpio
+      binding representation for description of particular cells.
+    const: 2
+
+  gpio-ranges:
+    maxItems: 1
+
+  gpio-line-names: true
+
+  interrupts:
+    description: The interrupt outputs to sysirq
+    maxItems: 1
+
+  interrupt-controller: true
+
+  '#interrupt-cells':
+    const: 2
+
+# PIN CONFIGURATION NODES
+patternProperties:
+  '-pins$':
+    type: object
+    additionalProperties: false
+
+    patternProperties:
+      '^pins':
+        type: object
+        allOf:
+          - $ref: /schemas/pinctrl/pincfg-node.yaml
+          - $ref: /schemas/pinctrl/pinmux-node.yaml
+        description:
+          A pinctrl node should contain at least one subnodes representing the
+          pinctrl groups available on the machine. Each subnode will list the
+          pins it needs, and how they should be configured, with regard to muxer
+          configuration, pullups, drive strength, input enable/disable and input
+          schmitt.
+
+        properties:
+          pinmux:
+            description:
+              Integer array, represents gpio pin number and mux setting.
+              Supported pin number and mux are defined as macros in
+              arch/arm64/boot/dts/mediatek/mt8196-pinfunc.h for this SoC.
+
+          drive-strength:
+            enum: [2, 4, 6, 8, 10, 12, 14, 16]
+
+          drive-strength-microamp:
+            enum: [125, 250, 500, 1000]
+
+          bias-pull-down:
+            oneOf:
+              - type: boolean
+              - enum: [75000, 5000]
+                description: Pull down RSEL type resistance values (in ohms)
+            description:
+              For normal pull down type there is no need to specify a resistance
+              value, hence this can be specified as a boolean property.
+              For RSEL pull down type a resistance value (in ohms) can be added.
+
+          bias-pull-up:
+            oneOf:
+              - type: boolean
+              - enum: [10000, 5000, 4000, 3000]
+                description: Pull up RSEL type resistance values (in ohms)
+            description:
+              For normal pull up type there is no need to specify a resistance
+              value, hence this can be specified as a boolean property.
+              For RSEL pull up type a resistance value (in ohms) can be added.
+
+          bias-disable: true
+
+          output-high: true
+
+          output-low: true
+
+          input-enable: true
+
+          input-disable: true
+
+          input-schmitt-enable: true
+
+          input-schmitt-disable: true
+
+        required:
+          - pinmux
+
+        additionalProperties: false
+
+required:
+  - compatible
+  - reg
+  - interrupts
+  - interrupt-controller
+  - '#interrupt-cells'
+  - gpio-controller
+  - '#gpio-cells'
+  - gpio-ranges
+
+additionalProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/interrupt-controller/arm-gic.h>
+    #include <dt-bindings/pinctrl/mt65xx.h>
+    #define PINMUX_GPIO0__FUNC_GPIO0 (MTK_PIN_NO(0) | 0)
+    #define PINMUX_GPIO99__FUNC_SCL0 (MTK_PIN_NO(99) | 1)
+    #define PINMUX_GPIO100__FUNC_SDA0 (MTK_PIN_NO(100) | 1)
+
+    pio: pinctrl@10005000 {
+        compatible = "mediatek,mt6878-pinctrl";
+        reg = <0x10005000 0x1000>,
+              <0x11d10000 0x1000>,
+              <0x11d30000 0x1000>,
+              <0x11d40000 0x1000>,
+              <0x11d50000 0x1000>,
+              <0x11d60000 0x1000>,
+              <0x11e20000 0x1000>,
+              <0x11e30000 0x1000>,
+              <0x11eb0000 0x1000>,
+              <0x11ec0000 0x1000>,
+              <0x11ce0000 0x1000>,
+              <0x11de0000 0x1000>,
+              <0x11e60000 0x1000>,
+              <0x1c01e000 0x1000>;
+        reg-names = "base", "bl", "bm", "br", "bl1", "br1",
+                    "lm", "lt", "rm", "rt", "eint-e", "eint-s",
+                    "eint-w", "eint-c";
+        gpio-controller;
+        #gpio-cells = <2>;
+        gpio-ranges = <&pio 0 0 220>;
+        interrupt-controller;
+        interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH 0>;
+        #interrupt-cells = <2>;
+
+        gpio-pins {
+            pins {
+                pinmux = <PINMUX_GPIO0__FUNC_GPIO0>;
+                bias-pull-up = <4000>;
+                drive-strength = <6>;
+            };
+        };
+
+        i2c0-pins {
+            pins-bus {
+                pinmux = <PINMUX_GPIO99__FUNC_SCL0>,
+                         <PINMUX_GPIO100__FUNC_SDA0>;
+                bias-pull-down = <75000>;
+                drive-strength-microamp = <1000>;
+            };
+        };
+    };
diff --git a/include/dt-bindings/pinctrl/mt6878-pinfunc.h b/include/dt-bindings/pinctrl/mt6878-pinfunc.h
new file mode 100644
index 0000000000000000000000000000000000000000..4e8e475a74549b513ac7075ac2ef0fe6f7f1d097
--- /dev/null
+++ b/include/dt-bindings/pinctrl/mt6878-pinfunc.h
@@ -0,0 +1,1201 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2023 MediaTek Inc.
+ * Author: Light Hsieh <light.hsieh@mediatek.com>
+ *
+ * Copyright (C) 2025 Igor Belwon <igor.belwon@mentallysanemainliners.org>
+ */
+
+#ifndef __MT6878_PINFUNC_H
+#define __MT6878_PINFUNC_H
+
+#include "mt65xx.h"
+
+#define PINMUX_GPIO0__FUNC_GPIO0 (MTK_PIN_NO(0) | 0)
+#define PINMUX_GPIO0__FUNC_TP_GPIO0_AO (MTK_PIN_NO(0) | 1)
+#define PINMUX_GPIO0__FUNC_SRCLKENA1 (MTK_PIN_NO(0) | 2)
+#define PINMUX_GPIO0__FUNC_DBG_MON_A3 (MTK_PIN_NO(0) | 7)
+
+#define PINMUX_GPIO1__FUNC_GPIO1 (MTK_PIN_NO(1) | 0)
+#define PINMUX_GPIO1__FUNC_TP_GPIO1_AO (MTK_PIN_NO(1) | 1)
+#define PINMUX_GPIO1__FUNC_SRCLKENA1 (MTK_PIN_NO(1) | 2)
+#define PINMUX_GPIO1__FUNC_SRCLKENA2 (MTK_PIN_NO(1) | 3)
+#define PINMUX_GPIO1__FUNC_IDDIG (MTK_PIN_NO(1) | 5)
+#define PINMUX_GPIO1__FUNC_DBG_MON_A4 (MTK_PIN_NO(1) | 7)
+
+#define PINMUX_GPIO2__FUNC_GPIO2 (MTK_PIN_NO(2) | 0)
+#define PINMUX_GPIO2__FUNC_TP_GPIO2_AO (MTK_PIN_NO(2) | 1)
+#define PINMUX_GPIO2__FUNC_SRCLKENAI0 (MTK_PIN_NO(2) | 2)
+#define PINMUX_GPIO2__FUNC_SCP_DMIC_CLK (MTK_PIN_NO(2) | 4)
+#define PINMUX_GPIO2__FUNC_DMIC_CLK (MTK_PIN_NO(2) | 5)
+#define PINMUX_GPIO2__FUNC_DBG_MON_A5 (MTK_PIN_NO(2) | 7)
+
+#define PINMUX_GPIO3__FUNC_GPIO3 (MTK_PIN_NO(3) | 0)
+#define PINMUX_GPIO3__FUNC_TP_GPIO3_AO (MTK_PIN_NO(3) | 1)
+#define PINMUX_GPIO3__FUNC_SRCLKENAI1 (MTK_PIN_NO(3) | 2)
+#define PINMUX_GPIO3__FUNC_SCP_DMIC_DAT (MTK_PIN_NO(3) | 4)
+#define PINMUX_GPIO3__FUNC_DMIC_DAT (MTK_PIN_NO(3) | 5)
+#define PINMUX_GPIO3__FUNC_DBG_MON_A6 (MTK_PIN_NO(3) | 7)
+
+#define PINMUX_GPIO4__FUNC_GPIO4 (MTK_PIN_NO(4) | 0)
+#define PINMUX_GPIO4__FUNC_SPI7_CLK (MTK_PIN_NO(4) | 1)
+#define PINMUX_GPIO4__FUNC_TP_GPIO4_AO (MTK_PIN_NO(4) | 2)
+#define PINMUX_GPIO4__FUNC_ANT_SEL0 (MTK_PIN_NO(4) | 3)
+#define PINMUX_GPIO4__FUNC_DMIC1_CLK (MTK_PIN_NO(4) | 5)
+#define PINMUX_GPIO4__FUNC_MD_INT4 (MTK_PIN_NO(4) | 6)
+#define PINMUX_GPIO4__FUNC_DBG_MON_A7 (MTK_PIN_NO(4) | 7)
+
+#define PINMUX_GPIO5__FUNC_GPIO5 (MTK_PIN_NO(5) | 0)
+#define PINMUX_GPIO5__FUNC_SPI7_CSB (MTK_PIN_NO(5) | 1)
+#define PINMUX_GPIO5__FUNC_TP_GPIO5_AO (MTK_PIN_NO(5) | 2)
+#define PINMUX_GPIO5__FUNC_ANT_SEL1 (MTK_PIN_NO(5) | 3)
+#define PINMUX_GPIO5__FUNC_DMIC1_DAT (MTK_PIN_NO(5) | 5)
+#define PINMUX_GPIO5__FUNC_MD_INT0 (MTK_PIN_NO(5) | 6)
+#define PINMUX_GPIO5__FUNC_DBG_MON_A8 (MTK_PIN_NO(5) | 7)
+
+#define PINMUX_GPIO6__FUNC_GPIO6 (MTK_PIN_NO(6) | 0)
+#define PINMUX_GPIO6__FUNC_SPI7_MO (MTK_PIN_NO(6) | 1)
+#define PINMUX_GPIO6__FUNC_TP_GPIO6_AO (MTK_PIN_NO(6) | 2)
+#define PINMUX_GPIO6__FUNC_ANT_SEL2 (MTK_PIN_NO(6) | 3)
+#define PINMUX_GPIO6__FUNC_MD32_0_GPIO0 (MTK_PIN_NO(6) | 4)
+#define PINMUX_GPIO6__FUNC_MD_INT3 (MTK_PIN_NO(6) | 6)
+#define PINMUX_GPIO6__FUNC_DBG_MON_B0 (MTK_PIN_NO(6) | 7)
+
+#define PINMUX_GPIO7__FUNC_GPIO7 (MTK_PIN_NO(7) | 0)
+#define PINMUX_GPIO7__FUNC_SPI7_MI (MTK_PIN_NO(7) | 1)
+#define PINMUX_GPIO7__FUNC_TP_GPIO7_AO (MTK_PIN_NO(7) | 2)
+#define PINMUX_GPIO7__FUNC_ANT_SEL3 (MTK_PIN_NO(7) | 3)
+#define PINMUX_GPIO7__FUNC_MD32_1_GPIO0 (MTK_PIN_NO(7) | 4)
+
+#define PINMUX_GPIO8__FUNC_GPIO8 (MTK_PIN_NO(8) | 0)
+#define PINMUX_GPIO8__FUNC_SCP_JTAG0_TRSTN_VLP (MTK_PIN_NO(8) | 2)
+#define PINMUX_GPIO8__FUNC_SPM_JTAG_TRSTN_VLP (MTK_PIN_NO(8) | 3)
+#define PINMUX_GPIO8__FUNC_SSPM_JTAG_TRSTN_VLP (MTK_PIN_NO(8) | 4)
+#define PINMUX_GPIO8__FUNC_HFRP_JTAG0_TRSTN (MTK_PIN_NO(8) | 5)
+#define PINMUX_GPIO8__FUNC_IO_JTAG_TRSTN (MTK_PIN_NO(8) | 6)
+#define PINMUX_GPIO8__FUNC_CONN_BGF_MCU_TDI (MTK_PIN_NO(8) | 7)
+
+#define PINMUX_GPIO9__FUNC_GPIO9 (MTK_PIN_NO(9) | 0)
+#define PINMUX_GPIO9__FUNC_SCP_JTAG0_TCK_VLP (MTK_PIN_NO(9) | 2)
+#define PINMUX_GPIO9__FUNC_SPM_JTAG_TCK_VLP (MTK_PIN_NO(9) | 3)
+#define PINMUX_GPIO9__FUNC_SSPM_JTAG_TCK_VLP (MTK_PIN_NO(9) | 4)
+#define PINMUX_GPIO9__FUNC_HFRP_JTAG0_TCK (MTK_PIN_NO(9) | 5)
+#define PINMUX_GPIO9__FUNC_IO_JTAG_TCK (MTK_PIN_NO(9) | 6)
+#define PINMUX_GPIO9__FUNC_CONN_BGF_MCU_TRST_B (MTK_PIN_NO(9) | 7)
+
+#define PINMUX_GPIO10__FUNC_GPIO10 (MTK_PIN_NO(10) | 0)
+#define PINMUX_GPIO10__FUNC_SCP_JTAG0_TMS_VLP (MTK_PIN_NO(10) | 2)
+#define PINMUX_GPIO10__FUNC_SPM_JTAG_TMS_VLP (MTK_PIN_NO(10) | 3)
+#define PINMUX_GPIO10__FUNC_SSPM_JTAG_TMS_VLP (MTK_PIN_NO(10) | 4)
+#define PINMUX_GPIO10__FUNC_HFRP_JTAG0_TMS (MTK_PIN_NO(10) | 5)
+#define PINMUX_GPIO10__FUNC_IO_JTAG_TMS (MTK_PIN_NO(10) | 6)
+#define PINMUX_GPIO10__FUNC_CONN_BGF_MCU_TCK (MTK_PIN_NO(10) | 7)
+
+#define PINMUX_GPIO11__FUNC_GPIO11 (MTK_PIN_NO(11) | 0)
+#define PINMUX_GPIO11__FUNC_SCP_JTAG0_TDI_VLP (MTK_PIN_NO(11) | 2)
+#define PINMUX_GPIO11__FUNC_SPM_JTAG_TDI_VLP (MTK_PIN_NO(11) | 3)
+#define PINMUX_GPIO11__FUNC_SSPM_JTAG_TDI_VLP (MTK_PIN_NO(11) | 4)
+#define PINMUX_GPIO11__FUNC_HFRP_JTAG0_TDI (MTK_PIN_NO(11) | 5)
+#define PINMUX_GPIO11__FUNC_IO_JTAG_TDI (MTK_PIN_NO(11) | 6)
+#define PINMUX_GPIO11__FUNC_CONN_BGF_MCU_TDO (MTK_PIN_NO(11) | 7)
+
+#define PINMUX_GPIO12__FUNC_GPIO12 (MTK_PIN_NO(12) | 0)
+#define PINMUX_GPIO12__FUNC_SCP_JTAG0_TDO_VLP (MTK_PIN_NO(12) | 2)
+#define PINMUX_GPIO12__FUNC_SPM_JTAG_TDO_VLP (MTK_PIN_NO(12) | 3)
+#define PINMUX_GPIO12__FUNC_SSPM_JTAG_TDO_VLP (MTK_PIN_NO(12) | 4)
+#define PINMUX_GPIO12__FUNC_HFRP_JTAG0_TDO (MTK_PIN_NO(12) | 5)
+#define PINMUX_GPIO12__FUNC_IO_JTAG_TDO (MTK_PIN_NO(12) | 6)
+#define PINMUX_GPIO12__FUNC_CONN_BGF_MCU_TMS (MTK_PIN_NO(12) | 7)
+
+#define PINMUX_GPIO13__FUNC_GPIO13 (MTK_PIN_NO(13) | 0)
+#define PINMUX_GPIO13__FUNC_MFG_EB_JTAG_TDI (MTK_PIN_NO(13) | 1)
+#define PINMUX_GPIO13__FUNC_CONN_WF_MCU_TDI (MTK_PIN_NO(13) | 2)
+#define PINMUX_GPIO13__FUNC_SCP_JTAG0_TDI_VCORE (MTK_PIN_NO(13) | 3)
+#define PINMUX_GPIO13__FUNC_SPM_JTAG_TDI_VCORE (MTK_PIN_NO(13) | 5)
+#define PINMUX_GPIO13__FUNC_MCUPM_JTAG_TDI (MTK_PIN_NO(13) | 6)
+
+#define PINMUX_GPIO14__FUNC_GPIO14 (MTK_PIN_NO(14) | 0)
+#define PINMUX_GPIO14__FUNC_MFG_EB_JTAG_TRSTN (MTK_PIN_NO(14) | 1)
+#define PINMUX_GPIO14__FUNC_CONN_WF_MCU_TRST_B (MTK_PIN_NO(14) | 2)
+#define PINMUX_GPIO14__FUNC_SCP_JTAG0_TRSTN_VCORE (MTK_PIN_NO(14) | 3)
+#define PINMUX_GPIO14__FUNC_SPM_JTAG_TRSTN_VCORE (MTK_PIN_NO(14) | 5)
+#define PINMUX_GPIO14__FUNC_MCUPM_JTAG_TRSTN (MTK_PIN_NO(14) | 6)
+
+#define PINMUX_GPIO15__FUNC_GPIO15 (MTK_PIN_NO(15) | 0)
+#define PINMUX_GPIO15__FUNC_MFG_EB_JTAG_TCK (MTK_PIN_NO(15) | 1)
+#define PINMUX_GPIO15__FUNC_CONN_WF_MCU_TCK (MTK_PIN_NO(15) | 2)
+#define PINMUX_GPIO15__FUNC_SCP_JTAG0_TCK_VCORE (MTK_PIN_NO(15) | 3)
+#define PINMUX_GPIO15__FUNC_SPM_JTAG_TCK_VCORE (MTK_PIN_NO(15) | 5)
+#define PINMUX_GPIO15__FUNC_MCUPM_JTAG_TCK (MTK_PIN_NO(15) | 6)
+
+#define PINMUX_GPIO16__FUNC_GPIO16 (MTK_PIN_NO(16) | 0)
+#define PINMUX_GPIO16__FUNC_MFG_EB_JTAG_TDO (MTK_PIN_NO(16) | 1)
+#define PINMUX_GPIO16__FUNC_CONN_WF_MCU_TDO (MTK_PIN_NO(16) | 2)
+#define PINMUX_GPIO16__FUNC_SCP_JTAG0_TDO_VCORE (MTK_PIN_NO(16) | 3)
+#define PINMUX_GPIO16__FUNC_SPM_JTAG_TDO_VCORE (MTK_PIN_NO(16) | 5)
+#define PINMUX_GPIO16__FUNC_MCUPM_JTAG_TDO (MTK_PIN_NO(16) | 6)
+
+#define PINMUX_GPIO17__FUNC_GPIO17 (MTK_PIN_NO(17) | 0)
+#define PINMUX_GPIO17__FUNC_MFG_EB_JTAG_TMS (MTK_PIN_NO(17) | 1)
+#define PINMUX_GPIO17__FUNC_CONN_WF_MCU_TMS (MTK_PIN_NO(17) | 2)
+#define PINMUX_GPIO17__FUNC_SCP_JTAG0_TMS_VCORE (MTK_PIN_NO(17) | 3)
+#define PINMUX_GPIO17__FUNC_SPM_JTAG_TMS_VCORE (MTK_PIN_NO(17) | 5)
+#define PINMUX_GPIO17__FUNC_MCUPM_JTAG_TMS (MTK_PIN_NO(17) | 6)
+
+#define PINMUX_GPIO18__FUNC_GPIO18 (MTK_PIN_NO(18) | 0)
+#define PINMUX_GPIO18__FUNC_CONN_BT_TXD (MTK_PIN_NO(18) | 2)
+#define PINMUX_GPIO18__FUNC_CONN_TCXOENA_REQ (MTK_PIN_NO(18) | 3)
+#define PINMUX_GPIO18__FUNC_GPS_L1_ELNA_EN (MTK_PIN_NO(18) | 6)
+
+#define PINMUX_GPIO19__FUNC_GPIO19 (MTK_PIN_NO(19) | 0)
+#define PINMUX_GPIO19__FUNC_PWM_0 (MTK_PIN_NO(19) | 1)
+#define PINMUX_GPIO19__FUNC_SDA10 (MTK_PIN_NO(19) | 3)
+#define PINMUX_GPIO19__FUNC_MD32_0_GPIO0 (MTK_PIN_NO(19) | 4)
+#define PINMUX_GPIO19__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(19) | 5)
+#define PINMUX_GPIO19__FUNC_DBG_MON_A9 (MTK_PIN_NO(19) | 7)
+
+#define PINMUX_GPIO20__FUNC_GPIO20 (MTK_PIN_NO(20) | 0)
+#define PINMUX_GPIO20__FUNC_PWM_1 (MTK_PIN_NO(20) | 1)
+#define PINMUX_GPIO20__FUNC_SPI4_CLK (MTK_PIN_NO(20) | 2)
+#define PINMUX_GPIO20__FUNC_GPS_L1_ELNA_EN (MTK_PIN_NO(20) | 4)
+#define PINMUX_GPIO20__FUNC_DAP_SONIC_SWCK (MTK_PIN_NO(20) | 6)
+#define PINMUX_GPIO20__FUNC_DBG_MON_A10 (MTK_PIN_NO(20) | 7)
+
+#define PINMUX_GPIO21__FUNC_GPIO21 (MTK_PIN_NO(21) | 0)
+#define PINMUX_GPIO21__FUNC_PWM_2 (MTK_PIN_NO(21) | 1)
+#define PINMUX_GPIO21__FUNC_SPI4_CSB (MTK_PIN_NO(21) | 2)
+#define PINMUX_GPIO21__FUNC_GPS_L5_ELNA_EN (MTK_PIN_NO(21) | 4)
+#define PINMUX_GPIO21__FUNC_IDDIG (MTK_PIN_NO(21) | 5)
+#define PINMUX_GPIO21__FUNC_DAP_SONIC_SWD (MTK_PIN_NO(21) | 6)
+#define PINMUX_GPIO21__FUNC_DBG_MON_A11 (MTK_PIN_NO(21) | 7)
+
+#define PINMUX_GPIO22__FUNC_GPIO22 (MTK_PIN_NO(22) | 0)
+#define PINMUX_GPIO22__FUNC_PWM_3 (MTK_PIN_NO(22) | 1)
+#define PINMUX_GPIO22__FUNC_SPI4_MO (MTK_PIN_NO(22) | 2)
+#define PINMUX_GPIO22__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(22) | 4)
+#define PINMUX_GPIO22__FUNC_VBUSVALID (MTK_PIN_NO(22) | 5)
+#define PINMUX_GPIO22__FUNC_DAP_MD32_SWCK (MTK_PIN_NO(22) | 6)
+#define PINMUX_GPIO22__FUNC_DBG_MON_A12 (MTK_PIN_NO(22) | 7)
+
+#define PINMUX_GPIO23__FUNC_GPIO23 (MTK_PIN_NO(23) | 0)
+#define PINMUX_GPIO23__FUNC_SPI4_MI (MTK_PIN_NO(23) | 2)
+#define PINMUX_GPIO23__FUNC_MD32_1_GPIO0 (MTK_PIN_NO(23) | 4)
+#define PINMUX_GPIO23__FUNC_USB_DRVVBUS (MTK_PIN_NO(23) | 5)
+#define PINMUX_GPIO23__FUNC_DAP_MD32_SWD (MTK_PIN_NO(23) | 6)
+#define PINMUX_GPIO23__FUNC_DBG_MON_A13 (MTK_PIN_NO(23) | 7)
+
+#define PINMUX_GPIO24__FUNC_GPIO24 (MTK_PIN_NO(24) | 0)
+#define PINMUX_GPIO24__FUNC_GPS_L5_ELNA_EN (MTK_PIN_NO(24) | 1)
+#define PINMUX_GPIO24__FUNC_SCL12 (MTK_PIN_NO(24) | 2)
+#define PINMUX_GPIO24__FUNC_SCL10 (MTK_PIN_NO(24) | 3)
+#define PINMUX_GPIO24__FUNC_CMVREF0 (MTK_PIN_NO(24) | 4)
+#define PINMUX_GPIO24__FUNC_CONN_WIFI_TXD (MTK_PIN_NO(24) | 5)
+#define PINMUX_GPIO24__FUNC_CMFLASH0 (MTK_PIN_NO(24) | 6)
+#define PINMUX_GPIO24__FUNC_DBG_MON_A14 (MTK_PIN_NO(24) | 7)
+
+#define PINMUX_GPIO25__FUNC_GPIO25 (MTK_PIN_NO(25) | 0)
+#define PINMUX_GPIO25__FUNC_SPI6_CLK (MTK_PIN_NO(25) | 1)
+#define PINMUX_GPIO25__FUNC_SCL11 (MTK_PIN_NO(25) | 2)
+#define PINMUX_GPIO25__FUNC_CMVREF1 (MTK_PIN_NO(25) | 4)
+#define PINMUX_GPIO25__FUNC_CMFLASH1 (MTK_PIN_NO(25) | 6)
+#define PINMUX_GPIO25__FUNC_DBG_MON_A15 (MTK_PIN_NO(25) | 7)
+
+#define PINMUX_GPIO26__FUNC_GPIO26 (MTK_PIN_NO(26) | 0)
+#define PINMUX_GPIO26__FUNC_SPI6_CSB (MTK_PIN_NO(26) | 1)
+#define PINMUX_GPIO26__FUNC_SDA11 (MTK_PIN_NO(26) | 2)
+#define PINMUX_GPIO26__FUNC_USB_DRVVBUS (MTK_PIN_NO(26) | 3)
+#define PINMUX_GPIO26__FUNC_CMVREF2 (MTK_PIN_NO(26) | 4)
+#define PINMUX_GPIO26__FUNC_CMFLASH2 (MTK_PIN_NO(26) | 6)
+#define PINMUX_GPIO26__FUNC_DBG_MON_A16 (MTK_PIN_NO(26) | 7)
+
+#define PINMUX_GPIO27__FUNC_GPIO27 (MTK_PIN_NO(27) | 0)
+#define PINMUX_GPIO27__FUNC_SPI6_MO (MTK_PIN_NO(27) | 1)
+#define PINMUX_GPIO27__FUNC_VBUSVALID (MTK_PIN_NO(27) | 3)
+#define PINMUX_GPIO27__FUNC_CMVREF3 (MTK_PIN_NO(27) | 4)
+#define PINMUX_GPIO27__FUNC_DMIC1_CLK (MTK_PIN_NO(27) | 5)
+#define PINMUX_GPIO27__FUNC_CMFLASH3 (MTK_PIN_NO(27) | 6)
+#define PINMUX_GPIO27__FUNC_DBG_MON_A17 (MTK_PIN_NO(27) | 7)
+
+#define PINMUX_GPIO28__FUNC_GPIO28 (MTK_PIN_NO(28) | 0)
+#define PINMUX_GPIO28__FUNC_SPI6_MI (MTK_PIN_NO(28) | 1)
+#define PINMUX_GPIO28__FUNC_IDDIG (MTK_PIN_NO(28) | 3)
+#define PINMUX_GPIO28__FUNC_DMIC1_DAT (MTK_PIN_NO(28) | 5)
+#define PINMUX_GPIO28__FUNC_CMFLASH0 (MTK_PIN_NO(28) | 6)
+#define PINMUX_GPIO28__FUNC_DBG_MON_A18 (MTK_PIN_NO(28) | 7)
+
+#define PINMUX_GPIO29__FUNC_GPIO29 (MTK_PIN_NO(29) | 0)
+#define PINMUX_GPIO29__FUNC_I2SIN2_BCK (MTK_PIN_NO(29) | 1)
+#define PINMUX_GPIO29__FUNC_TP_UTXD1_VCORE (MTK_PIN_NO(29) | 2)
+#define PINMUX_GPIO29__FUNC_MD_UTXD0 (MTK_PIN_NO(29) | 3)
+#define PINMUX_GPIO29__FUNC_SSPM_UTXD_AO_VCORE (MTK_PIN_NO(29) | 4)
+#define PINMUX_GPIO29__FUNC_MD32_1_TXD (MTK_PIN_NO(29) | 5)
+#define PINMUX_GPIO29__FUNC_CONN_BT_TXD (MTK_PIN_NO(29) | 6)
+#define PINMUX_GPIO29__FUNC_PTA_TXD (MTK_PIN_NO(29) | 7)
+
+#define PINMUX_GPIO30__FUNC_GPIO30 (MTK_PIN_NO(30) | 0)
+#define PINMUX_GPIO30__FUNC_I2SIN2_LRCK (MTK_PIN_NO(30) | 1)
+#define PINMUX_GPIO30__FUNC_TP_URXD1_VCORE (MTK_PIN_NO(30) | 2)
+#define PINMUX_GPIO30__FUNC_MD_URXD0 (MTK_PIN_NO(30) | 3)
+#define PINMUX_GPIO30__FUNC_SSPM_URXD_AO_VCORE (MTK_PIN_NO(30) | 4)
+#define PINMUX_GPIO30__FUNC_MD32_1_RXD (MTK_PIN_NO(30) | 5)
+#define PINMUX_GPIO30__FUNC_PTA_RXD (MTK_PIN_NO(30) | 7)
+
+#define PINMUX_GPIO31__FUNC_GPIO31 (MTK_PIN_NO(31) | 0)
+#define PINMUX_GPIO31__FUNC_I2SOUT2_DO (MTK_PIN_NO(31) | 1)
+#define PINMUX_GPIO31__FUNC_TP_UTXD2_VCORE (MTK_PIN_NO(31) | 2)
+#define PINMUX_GPIO31__FUNC_MD_UTXD1 (MTK_PIN_NO(31) | 3)
+#define PINMUX_GPIO31__FUNC_HFRP_UTXD1 (MTK_PIN_NO(31) | 4)
+#define PINMUX_GPIO31__FUNC_MD32_0_TXD (MTK_PIN_NO(31) | 5)
+#define PINMUX_GPIO31__FUNC_CONN_WIFI_TXD (MTK_PIN_NO(31) | 6)
+#define PINMUX_GPIO31__FUNC_CONN_BGF_UART0_TXD (MTK_PIN_NO(31) | 7)
+
+#define PINMUX_GPIO32__FUNC_GPIO32 (MTK_PIN_NO(32) | 0)
+#define PINMUX_GPIO32__FUNC_I2SIN2_DI (MTK_PIN_NO(32) | 1)
+#define PINMUX_GPIO32__FUNC_TP_URXD2_VCORE (MTK_PIN_NO(32) | 2)
+#define PINMUX_GPIO32__FUNC_MD_URXD1 (MTK_PIN_NO(32) | 3)
+#define PINMUX_GPIO32__FUNC_HFRP_URXD1 (MTK_PIN_NO(32) | 4)
+#define PINMUX_GPIO32__FUNC_MD32_0_RXD (MTK_PIN_NO(32) | 5)
+#define PINMUX_GPIO32__FUNC_CONN_BGF_UART0_RXD (MTK_PIN_NO(32) | 7)
+
+#define PINMUX_GPIO33__FUNC_GPIO33 (MTK_PIN_NO(33) | 0)
+#define PINMUX_GPIO33__FUNC_ANT_SEL0 (MTK_PIN_NO(33) | 1)
+#define PINMUX_GPIO33__FUNC_GPS_L1_ELNA_EN (MTK_PIN_NO(33) | 3)
+#define PINMUX_GPIO33__FUNC_SCL1 (MTK_PIN_NO(33) | 4)
+#define PINMUX_GPIO33__FUNC_CONN_BPI_BUS18_ANT1 (MTK_PIN_NO(33) | 5)
+#define PINMUX_GPIO33__FUNC_MD_UCTS0 (MTK_PIN_NO(33) | 6)
+
+#define PINMUX_GPIO34__FUNC_GPIO34 (MTK_PIN_NO(34) | 0)
+#define PINMUX_GPIO34__FUNC_ANT_SEL1 (MTK_PIN_NO(34) | 1)
+#define PINMUX_GPIO34__FUNC_GPS_L5_ELNA_EN (MTK_PIN_NO(34) | 3)
+#define PINMUX_GPIO34__FUNC_SDA1 (MTK_PIN_NO(34) | 4)
+#define PINMUX_GPIO34__FUNC_CONN_BPI_BUS19_ANT2 (MTK_PIN_NO(34) | 5)
+#define PINMUX_GPIO34__FUNC_MD_URTS0 (MTK_PIN_NO(34) | 6)
+
+#define PINMUX_GPIO35__FUNC_GPIO35 (MTK_PIN_NO(35) | 0)
+#define PINMUX_GPIO35__FUNC_ANT_SEL2 (MTK_PIN_NO(35) | 1)
+#define PINMUX_GPIO35__FUNC_SSPM_JTAG_TCK_VCORE (MTK_PIN_NO(35) | 2)
+#define PINMUX_GPIO35__FUNC_UDI_TCK (MTK_PIN_NO(35) | 3)
+#define PINMUX_GPIO35__FUNC_CONN_BPI_BUS20_ANT3 (MTK_PIN_NO(35) | 5)
+#define PINMUX_GPIO35__FUNC_MD_UCTS1 (MTK_PIN_NO(35) | 6)
+
+#define PINMUX_GPIO36__FUNC_GPIO36 (MTK_PIN_NO(36) | 0)
+#define PINMUX_GPIO36__FUNC_ANT_SEL3 (MTK_PIN_NO(36) | 1)
+#define PINMUX_GPIO36__FUNC_SSPM_JTAG_TRSTN_VCORE (MTK_PIN_NO(36) | 2)
+#define PINMUX_GPIO36__FUNC_UDI_NTRST (MTK_PIN_NO(36) | 3)
+#define PINMUX_GPIO36__FUNC_CONN_BPI_BUS21_ANT4 (MTK_PIN_NO(36) | 5)
+#define PINMUX_GPIO36__FUNC_MD_URTS1 (MTK_PIN_NO(36) | 6)
+
+#define PINMUX_GPIO37__FUNC_GPIO37 (MTK_PIN_NO(37) | 0)
+#define PINMUX_GPIO37__FUNC_ANT_SEL4 (MTK_PIN_NO(37) | 1)
+#define PINMUX_GPIO37__FUNC_SSPM_JTAG_TDI_VCORE (MTK_PIN_NO(37) | 2)
+#define PINMUX_GPIO37__FUNC_UDI_TDI (MTK_PIN_NO(37) | 3)
+#define PINMUX_GPIO37__FUNC_TP_UCTS1_VCORE (MTK_PIN_NO(37) | 6)
+
+#define PINMUX_GPIO38__FUNC_GPIO38 (MTK_PIN_NO(38) | 0)
+#define PINMUX_GPIO38__FUNC_ANT_SEL5 (MTK_PIN_NO(38) | 1)
+#define PINMUX_GPIO38__FUNC_SSPM_JTAG_TMS_VCORE (MTK_PIN_NO(38) | 2)
+#define PINMUX_GPIO38__FUNC_UDI_TMS (MTK_PIN_NO(38) | 3)
+#define PINMUX_GPIO38__FUNC_TP_URTS1_VCORE (MTK_PIN_NO(38) | 6)
+
+#define PINMUX_GPIO39__FUNC_GPIO39 (MTK_PIN_NO(39) | 0)
+#define PINMUX_GPIO39__FUNC_ANT_SEL6 (MTK_PIN_NO(39) | 1)
+#define PINMUX_GPIO39__FUNC_SSPM_JTAG_TDO_VCORE (MTK_PIN_NO(39) | 2)
+#define PINMUX_GPIO39__FUNC_UDI_TDO (MTK_PIN_NO(39) | 3)
+#define PINMUX_GPIO39__FUNC_CLKM3 (MTK_PIN_NO(39) | 5)
+
+#define PINMUX_GPIO40__FUNC_GPIO40 (MTK_PIN_NO(40) | 0)
+#define PINMUX_GPIO40__FUNC_ANT_SEL7 (MTK_PIN_NO(40) | 1)
+#define PINMUX_GPIO40__FUNC_PMSR_SMAP (MTK_PIN_NO(40) | 2)
+#define PINMUX_GPIO40__FUNC_CONN_TCXOENA_REQ (MTK_PIN_NO(40) | 3)
+#define PINMUX_GPIO40__FUNC_CONN_WIFI_TXD (MTK_PIN_NO(40) | 4)
+#define PINMUX_GPIO40__FUNC_GPS_PPS (MTK_PIN_NO(40) | 5)
+
+#define PINMUX_GPIO41__FUNC_GPIO41 (MTK_PIN_NO(41) | 0)
+#define PINMUX_GPIO41__FUNC_I2SIN1_MCK (MTK_PIN_NO(41) | 1)
+#define PINMUX_GPIO41__FUNC_IDDIG (MTK_PIN_NO(41) | 2)
+#define PINMUX_GPIO41__FUNC_GPS_PPS (MTK_PIN_NO(41) | 3)
+#define PINMUX_GPIO41__FUNC_HFRP_UCTS1 (MTK_PIN_NO(41) | 4)
+#define PINMUX_GPIO41__FUNC_TP_UCTS2_VCORE (MTK_PIN_NO(41) | 5)
+#define PINMUX_GPIO41__FUNC_ANT_SEL8 (MTK_PIN_NO(41) | 6)
+#define PINMUX_GPIO41__FUNC_DBG_MON_B1 (MTK_PIN_NO(41) | 7)
+
+#define PINMUX_GPIO42__FUNC_GPIO42 (MTK_PIN_NO(42) | 0)
+#define PINMUX_GPIO42__FUNC_I2SIN1_BCK (MTK_PIN_NO(42) | 1)
+#define PINMUX_GPIO42__FUNC_I2SIN4_BCK (MTK_PIN_NO(42) | 2)
+#define PINMUX_GPIO42__FUNC_HFRP_URTS1 (MTK_PIN_NO(42) | 4)
+#define PINMUX_GPIO42__FUNC_TP_URTS2_VCORE (MTK_PIN_NO(42) | 5)
+#define PINMUX_GPIO42__FUNC_ANT_SEL9 (MTK_PIN_NO(42) | 6)
+#define PINMUX_GPIO42__FUNC_DBG_MON_B2 (MTK_PIN_NO(42) | 7)
+
+#define PINMUX_GPIO43__FUNC_GPIO43 (MTK_PIN_NO(43) | 0)
+#define PINMUX_GPIO43__FUNC_I2SIN1_LRCK (MTK_PIN_NO(43) | 1)
+#define PINMUX_GPIO43__FUNC_I2SIN4_LRCK (MTK_PIN_NO(43) | 2)
+#define PINMUX_GPIO43__FUNC_ANT_SEL10 (MTK_PIN_NO(43) | 6)
+#define PINMUX_GPIO43__FUNC_DBG_MON_B3 (MTK_PIN_NO(43) | 7)
+
+#define PINMUX_GPIO44__FUNC_GPIO44 (MTK_PIN_NO(44) | 0)
+#define PINMUX_GPIO44__FUNC_I2SOUT1_DO (MTK_PIN_NO(44) | 1)
+#define PINMUX_GPIO44__FUNC_I2SOUT4_DATA0 (MTK_PIN_NO(44) | 2)
+#define PINMUX_GPIO44__FUNC_ANT_SEL11 (MTK_PIN_NO(44) | 6)
+#define PINMUX_GPIO44__FUNC_DBG_MON_B4 (MTK_PIN_NO(44) | 7)
+
+#define PINMUX_GPIO45__FUNC_GPIO45 (MTK_PIN_NO(45) | 0)
+#define PINMUX_GPIO45__FUNC_I2SIN1_DI (MTK_PIN_NO(45) | 1)
+#define PINMUX_GPIO45__FUNC_I2SIN4_DATA0 (MTK_PIN_NO(45) | 2)
+#define PINMUX_GPIO45__FUNC_AGPS_SYNC (MTK_PIN_NO(45) | 5)
+#define PINMUX_GPIO45__FUNC_ANT_SEL12 (MTK_PIN_NO(45) | 6)
+#define PINMUX_GPIO45__FUNC_DBG_MON_B5 (MTK_PIN_NO(45) | 7)
+
+#define PINMUX_GPIO46__FUNC_GPIO46 (MTK_PIN_NO(46) | 0)
+#define PINMUX_GPIO46__FUNC_MD_INT1_C2K_UIM0_HOT_PLUG (MTK_PIN_NO(46) | 1)
+#define PINMUX_GPIO46__FUNC_MD_INT2_C2K_UIM1_HOT_PLUG (MTK_PIN_NO(46) | 2)
+#define PINMUX_GPIO46__FUNC_SRCLKENAI0 (MTK_PIN_NO(46) | 3)
+#define PINMUX_GPIO46__FUNC_SSPM_UTXD_AO_VLP (MTK_PIN_NO(46) | 5)
+#define PINMUX_GPIO46__FUNC_MD_MCIF_UTXD0 (MTK_PIN_NO(46) | 6)
+#define PINMUX_GPIO46__FUNC_DBG_MON_B6 (MTK_PIN_NO(46) | 7)
+
+#define PINMUX_GPIO47__FUNC_GPIO47 (MTK_PIN_NO(47) | 0)
+#define PINMUX_GPIO47__FUNC_MD_INT2_C2K_UIM1_HOT_PLUG (MTK_PIN_NO(47) | 1)
+#define PINMUX_GPIO47__FUNC_MD_INT1_C2K_UIM0_HOT_PLUG (MTK_PIN_NO(47) | 2)
+#define PINMUX_GPIO47__FUNC_SRCLKENAI1 (MTK_PIN_NO(47) | 3)
+#define PINMUX_GPIO47__FUNC_SRCLKENA1 (MTK_PIN_NO(47) | 4)
+#define PINMUX_GPIO47__FUNC_SSPM_URXD_AO_VLP (MTK_PIN_NO(47) | 5)
+#define PINMUX_GPIO47__FUNC_MD_MCIF_URXD0 (MTK_PIN_NO(47) | 6)
+#define PINMUX_GPIO47__FUNC_DBG_MON_B7 (MTK_PIN_NO(47) | 7)
+
+#define PINMUX_GPIO48__FUNC_GPIO48 (MTK_PIN_NO(48) | 0)
+#define PINMUX_GPIO48__FUNC_UTXD0 (MTK_PIN_NO(48) | 1)
+#define PINMUX_GPIO48__FUNC_MD_UTXD1 (MTK_PIN_NO(48) | 3)
+#define PINMUX_GPIO48__FUNC_HFRP_UTXD1 (MTK_PIN_NO(48) | 4)
+#define PINMUX_GPIO48__FUNC_MD32_0_TXD (MTK_PIN_NO(48) | 5)
+
+#define PINMUX_GPIO49__FUNC_GPIO49 (MTK_PIN_NO(49) | 0)
+#define PINMUX_GPIO49__FUNC_URXD0 (MTK_PIN_NO(49) | 1)
+#define PINMUX_GPIO49__FUNC_MD_URXD1 (MTK_PIN_NO(49) | 3)
+#define PINMUX_GPIO49__FUNC_HFRP_URXD1 (MTK_PIN_NO(49) | 4)
+#define PINMUX_GPIO49__FUNC_MD32_0_RXD (MTK_PIN_NO(49) | 5)
+
+#define PINMUX_GPIO50__FUNC_GPIO50 (MTK_PIN_NO(50) | 0)
+#define PINMUX_GPIO50__FUNC_MD_UTXD0 (MTK_PIN_NO(50) | 1)
+#define PINMUX_GPIO50__FUNC_TP_UTXD1_VLP (MTK_PIN_NO(50) | 2)
+#define PINMUX_GPIO50__FUNC_CONN_BGF_UART0_TXD (MTK_PIN_NO(50) | 3)
+#define PINMUX_GPIO50__FUNC_SSPM_UTXD_AO_VLP (MTK_PIN_NO(50) | 4)
+#define PINMUX_GPIO50__FUNC_MD_MCIF_UTXD0 (MTK_PIN_NO(50) | 5)
+#define PINMUX_GPIO50__FUNC_TP_UTXD2_VLP (MTK_PIN_NO(50) | 6)
+#define PINMUX_GPIO50__FUNC_UTXD1 (MTK_PIN_NO(50) | 7)
+
+#define PINMUX_GPIO51__FUNC_GPIO51 (MTK_PIN_NO(51) | 0)
+#define PINMUX_GPIO51__FUNC_MD_URXD0 (MTK_PIN_NO(51) | 1)
+#define PINMUX_GPIO51__FUNC_TP_URXD1_VLP (MTK_PIN_NO(51) | 2)
+#define PINMUX_GPIO51__FUNC_CONN_BGF_UART0_RXD (MTK_PIN_NO(51) | 3)
+#define PINMUX_GPIO51__FUNC_SSPM_URXD_AO_VLP (MTK_PIN_NO(51) | 4)
+#define PINMUX_GPIO51__FUNC_MD_MCIF_URXD0 (MTK_PIN_NO(51) | 5)
+#define PINMUX_GPIO51__FUNC_TP_URXD2_VLP (MTK_PIN_NO(51) | 6)
+#define PINMUX_GPIO51__FUNC_URXD1 (MTK_PIN_NO(51) | 7)
+
+#define PINMUX_GPIO52__FUNC_GPIO52 (MTK_PIN_NO(52) | 0)
+#define PINMUX_GPIO52__FUNC_KPROW0 (MTK_PIN_NO(52) | 1)
+#define PINMUX_GPIO52__FUNC_CMFLASH0 (MTK_PIN_NO(52) | 2)
+#define PINMUX_GPIO52__FUNC_SDA12 (MTK_PIN_NO(52) | 3)
+#define PINMUX_GPIO52__FUNC_DSI_TE1 (MTK_PIN_NO(52) | 4)
+
+#define PINMUX_GPIO53__FUNC_GPIO53 (MTK_PIN_NO(53) | 0)
+#define PINMUX_GPIO53__FUNC_KPROW1 (MTK_PIN_NO(53) | 1)
+#define PINMUX_GPIO53__FUNC_CMFLASH1 (MTK_PIN_NO(53) | 2)
+#define PINMUX_GPIO53__FUNC_SCL12 (MTK_PIN_NO(53) | 3)
+#define PINMUX_GPIO53__FUNC_LCM_RST1 (MTK_PIN_NO(53) | 4)
+#define PINMUX_GPIO53__FUNC_EXTIF0_ACT (MTK_PIN_NO(53) | 6)
+
+#define PINMUX_GPIO54__FUNC_GPIO54 (MTK_PIN_NO(54) | 0)
+#define PINMUX_GPIO54__FUNC_KPCOL0_VLP (MTK_PIN_NO(54) | 1)
+#define PINMUX_GPIO54__FUNC_KPCOL0_VLP_A (MTK_PIN_NO(54) | 7)
+
+#define PINMUX_GPIO55__FUNC_GPIO55 (MTK_PIN_NO(55) | 0)
+#define PINMUX_GPIO55__FUNC_KPCOL1 (MTK_PIN_NO(55) | 1)
+#define PINMUX_GPIO55__FUNC_SDA12 (MTK_PIN_NO(55) | 3)
+#define PINMUX_GPIO55__FUNC_DISP_PWM1 (MTK_PIN_NO(55) | 4)
+#define PINMUX_GPIO55__FUNC_JTRSTN_SEL1_VCORE (MTK_PIN_NO(55) | 7)
+
+#define PINMUX_GPIO56__FUNC_GPIO56 (MTK_PIN_NO(56) | 0)
+#define PINMUX_GPIO56__FUNC_SPI0_CLK (MTK_PIN_NO(56) | 1)
+#define PINMUX_GPIO56__FUNC_JTCK_SEL1_VCORE (MTK_PIN_NO(56) | 7)
+
+#define PINMUX_GPIO57__FUNC_GPIO57 (MTK_PIN_NO(57) | 0)
+#define PINMUX_GPIO57__FUNC_SPI0_CSB (MTK_PIN_NO(57) | 1)
+#define PINMUX_GPIO57__FUNC_JTMS_SEL1_VCORE (MTK_PIN_NO(57) | 7)
+
+#define PINMUX_GPIO58__FUNC_GPIO58 (MTK_PIN_NO(58) | 0)
+#define PINMUX_GPIO58__FUNC_SPI0_MO (MTK_PIN_NO(58) | 1)
+#define PINMUX_GPIO58__FUNC_JTDO_SEL1_VCORE (MTK_PIN_NO(58) | 7)
+
+#define PINMUX_GPIO59__FUNC_GPIO59 (MTK_PIN_NO(59) | 0)
+#define PINMUX_GPIO59__FUNC_SPI0_MI (MTK_PIN_NO(59) | 1)
+#define PINMUX_GPIO59__FUNC_JTDI_SEL1_VCORE (MTK_PIN_NO(59) | 7)
+
+#define PINMUX_GPIO60__FUNC_GPIO60 (MTK_PIN_NO(60) | 0)
+#define PINMUX_GPIO60__FUNC_SCP_SPI1_CK (MTK_PIN_NO(60) | 1)
+#define PINMUX_GPIO60__FUNC_SPI1_CLK (MTK_PIN_NO(60) | 2)
+#define PINMUX_GPIO60__FUNC_SCP_SCL3 (MTK_PIN_NO(60) | 4)
+#define PINMUX_GPIO60__FUNC_TP_GPIO0_AO (MTK_PIN_NO(60) | 5)
+#define PINMUX_GPIO60__FUNC_UTXD0 (MTK_PIN_NO(60) | 6)
+#define PINMUX_GPIO60__FUNC_TP_UTXD2_VLP (MTK_PIN_NO(60) | 7)
+
+#define PINMUX_GPIO61__FUNC_GPIO61 (MTK_PIN_NO(61) | 0)
+#define PINMUX_GPIO61__FUNC_SCP_SPI1_CS (MTK_PIN_NO(61) | 1)
+#define PINMUX_GPIO61__FUNC_SPI1_CSB (MTK_PIN_NO(61) | 2)
+#define PINMUX_GPIO61__FUNC_TP_GPIO1_AO (MTK_PIN_NO(61) | 5)
+#define PINMUX_GPIO61__FUNC_URXD0 (MTK_PIN_NO(61) | 6)
+#define PINMUX_GPIO61__FUNC_TP_URXD2_VLP (MTK_PIN_NO(61) | 7)
+
+#define PINMUX_GPIO62__FUNC_GPIO62 (MTK_PIN_NO(62) | 0)
+#define PINMUX_GPIO62__FUNC_SCP_SPI1_MO (MTK_PIN_NO(62) | 1)
+#define PINMUX_GPIO62__FUNC_SPI1_MO (MTK_PIN_NO(62) | 2)
+#define PINMUX_GPIO62__FUNC_SCP_SCL3 (MTK_PIN_NO(62) | 3)
+#define PINMUX_GPIO62__FUNC_SCP_SDA3 (MTK_PIN_NO(62) | 4)
+#define PINMUX_GPIO62__FUNC_TP_GPIO2_AO (MTK_PIN_NO(62) | 5)
+#define PINMUX_GPIO62__FUNC_DBG_MON_B29 (MTK_PIN_NO(62) | 7)
+
+#define PINMUX_GPIO63__FUNC_GPIO63 (MTK_PIN_NO(63) | 0)
+#define PINMUX_GPIO63__FUNC_SCP_SPI1_MI (MTK_PIN_NO(63) | 1)
+#define PINMUX_GPIO63__FUNC_SPI1_MI (MTK_PIN_NO(63) | 2)
+#define PINMUX_GPIO63__FUNC_SCP_SDA3 (MTK_PIN_NO(63) | 3)
+#define PINMUX_GPIO63__FUNC_TP_GPIO3_AO (MTK_PIN_NO(63) | 5)
+#define PINMUX_GPIO63__FUNC_DBG_MON_B30 (MTK_PIN_NO(63) | 7)
+
+#define PINMUX_GPIO64__FUNC_GPIO64 (MTK_PIN_NO(64) | 0)
+#define PINMUX_GPIO64__FUNC_SCP_SPI2_CK (MTK_PIN_NO(64) | 1)
+#define PINMUX_GPIO64__FUNC_SPI2_CLK (MTK_PIN_NO(64) | 2)
+#define PINMUX_GPIO64__FUNC_SCP_SCL2 (MTK_PIN_NO(64) | 4)
+#define PINMUX_GPIO64__FUNC_TP_GPIO4_AO (MTK_PIN_NO(64) | 5)
+
+#define PINMUX_GPIO65__FUNC_GPIO65 (MTK_PIN_NO(65) | 0)
+#define PINMUX_GPIO65__FUNC_SCP_SPI2_CS (MTK_PIN_NO(65) | 1)
+#define PINMUX_GPIO65__FUNC_SPI2_CSB (MTK_PIN_NO(65) | 2)
+#define PINMUX_GPIO65__FUNC_TP_GPIO5_AO (MTK_PIN_NO(65) | 5)
+#define PINMUX_GPIO65__FUNC_DBG_MON_B31 (MTK_PIN_NO(65) | 7)
+
+#define PINMUX_GPIO66__FUNC_GPIO66 (MTK_PIN_NO(66) | 0)
+#define PINMUX_GPIO66__FUNC_SCP_SPI2_MO (MTK_PIN_NO(66) | 1)
+#define PINMUX_GPIO66__FUNC_SPI2_MO (MTK_PIN_NO(66) | 2)
+#define PINMUX_GPIO66__FUNC_SCP_SCL2 (MTK_PIN_NO(66) | 3)
+#define PINMUX_GPIO66__FUNC_SCP_SDA2 (MTK_PIN_NO(66) | 4)
+#define PINMUX_GPIO66__FUNC_TP_GPIO6_AO (MTK_PIN_NO(66) | 5)
+
+#define PINMUX_GPIO67__FUNC_GPIO67 (MTK_PIN_NO(67) | 0)
+#define PINMUX_GPIO67__FUNC_SCP_SPI2_MI (MTK_PIN_NO(67) | 1)
+#define PINMUX_GPIO67__FUNC_SPI2_MI (MTK_PIN_NO(67) | 2)
+#define PINMUX_GPIO67__FUNC_SCP_SDA2 (MTK_PIN_NO(67) | 3)
+#define PINMUX_GPIO67__FUNC_TP_GPIO7_AO (MTK_PIN_NO(67) | 5)
+
+#define PINMUX_GPIO68__FUNC_GPIO68 (MTK_PIN_NO(68) | 0)
+#define PINMUX_GPIO68__FUNC_SCP_SPI3_CK (MTK_PIN_NO(68) | 1)
+#define PINMUX_GPIO68__FUNC_SPI3_CLK (MTK_PIN_NO(68) | 2)
+#define PINMUX_GPIO68__FUNC_MD_INT4 (MTK_PIN_NO(68) | 3)
+#define PINMUX_GPIO68__FUNC_SCP_SCL4 (MTK_PIN_NO(68) | 4)
+#define PINMUX_GPIO68__FUNC_TP_GPIO8_AO (MTK_PIN_NO(68) | 5)
+#define PINMUX_GPIO68__FUNC_DBG_MON_A19 (MTK_PIN_NO(68) | 7)
+
+#define PINMUX_GPIO69__FUNC_GPIO69 (MTK_PIN_NO(69) | 0)
+#define PINMUX_GPIO69__FUNC_SCP_SPI3_CS (MTK_PIN_NO(69) | 1)
+#define PINMUX_GPIO69__FUNC_SPI3_CSB (MTK_PIN_NO(69) | 2)
+#define PINMUX_GPIO69__FUNC_MD_INT3 (MTK_PIN_NO(69) | 3)
+#define PINMUX_GPIO69__FUNC_TP_GPIO9_AO (MTK_PIN_NO(69) | 5)
+#define PINMUX_GPIO69__FUNC_DBG_MON_A20 (MTK_PIN_NO(69) | 7)
+
+#define PINMUX_GPIO70__FUNC_GPIO70 (MTK_PIN_NO(70) | 0)
+#define PINMUX_GPIO70__FUNC_SCP_SPI3_MO (MTK_PIN_NO(70) | 1)
+#define PINMUX_GPIO70__FUNC_SPI3_MO (MTK_PIN_NO(70) | 2)
+#define PINMUX_GPIO70__FUNC_SCP_SCL4 (MTK_PIN_NO(70) | 3)
+#define PINMUX_GPIO70__FUNC_SCP_SDA4 (MTK_PIN_NO(70) | 4)
+#define PINMUX_GPIO70__FUNC_TP_GPIO10_AO (MTK_PIN_NO(70) | 5)
+#define PINMUX_GPIO70__FUNC_DBG_MON_A21 (MTK_PIN_NO(70) | 7)
+
+#define PINMUX_GPIO71__FUNC_GPIO71 (MTK_PIN_NO(71) | 0)
+#define PINMUX_GPIO71__FUNC_SCP_SPI3_MI (MTK_PIN_NO(71) | 1)
+#define PINMUX_GPIO71__FUNC_SPI3_MI (MTK_PIN_NO(71) | 2)
+#define PINMUX_GPIO71__FUNC_SCP_SDA4 (MTK_PIN_NO(71) | 3)
+#define PINMUX_GPIO71__FUNC_MD_INT0 (MTK_PIN_NO(71) | 4)
+#define PINMUX_GPIO71__FUNC_TP_GPIO11_AO (MTK_PIN_NO(71) | 5)
+#define PINMUX_GPIO71__FUNC_DBG_MON_A22 (MTK_PIN_NO(71) | 7)
+
+#define PINMUX_GPIO72__FUNC_GPIO72 (MTK_PIN_NO(72) | 0)
+#define PINMUX_GPIO72__FUNC_SPI5_CLK (MTK_PIN_NO(72) | 1)
+#define PINMUX_GPIO72__FUNC_SCP_SPI0_CK (MTK_PIN_NO(72) | 2)
+#define PINMUX_GPIO72__FUNC_UCTS2 (MTK_PIN_NO(72) | 3)
+#define PINMUX_GPIO72__FUNC_MBISTREADEN_TRIGGER (MTK_PIN_NO(72) | 4)
+#define PINMUX_GPIO72__FUNC_TP_GPIO12_AO (MTK_PIN_NO(72) | 5)
+#define PINMUX_GPIO72__FUNC_EXTIF0_ACT (MTK_PIN_NO(72) | 6)
+#define PINMUX_GPIO72__FUNC_DAP_SONIC_SWCK (MTK_PIN_NO(72) | 7)
+
+#define PINMUX_GPIO73__FUNC_GPIO73 (MTK_PIN_NO(73) | 0)
+#define PINMUX_GPIO73__FUNC_SPI5_CSB (MTK_PIN_NO(73) | 1)
+#define PINMUX_GPIO73__FUNC_SCP_SPI0_CS (MTK_PIN_NO(73) | 2)
+#define PINMUX_GPIO73__FUNC_URTS2 (MTK_PIN_NO(73) | 3)
+#define PINMUX_GPIO73__FUNC_MBISTWRITEEN_TRIGGER (MTK_PIN_NO(73) | 4)
+#define PINMUX_GPIO73__FUNC_TP_GPIO13_AO (MTK_PIN_NO(73) | 5)
+#define PINMUX_GPIO73__FUNC_EXTIF0_PRI (MTK_PIN_NO(73) | 6)
+#define PINMUX_GPIO73__FUNC_DAP_SONIC_SWD (MTK_PIN_NO(73) | 7)
+
+#define PINMUX_GPIO74__FUNC_GPIO74 (MTK_PIN_NO(74) | 0)
+#define PINMUX_GPIO74__FUNC_SPI5_MO (MTK_PIN_NO(74) | 1)
+#define PINMUX_GPIO74__FUNC_SCP_SPI0_MO (MTK_PIN_NO(74) | 2)
+#define PINMUX_GPIO74__FUNC_UTXD2 (MTK_PIN_NO(74) | 3)
+#define PINMUX_GPIO74__FUNC_TP_UTXD2_VCORE (MTK_PIN_NO(74) | 4)
+#define PINMUX_GPIO74__FUNC_TP_GPIO14_AO (MTK_PIN_NO(74) | 5)
+#define PINMUX_GPIO74__FUNC_EXTIF0_GNT_B (MTK_PIN_NO(74) | 6)
+#define PINMUX_GPIO74__FUNC_DAP_MD32_SWCK (MTK_PIN_NO(74) | 7)
+
+#define PINMUX_GPIO75__FUNC_GPIO75 (MTK_PIN_NO(75) | 0)
+#define PINMUX_GPIO75__FUNC_SPI5_MI (MTK_PIN_NO(75) | 1)
+#define PINMUX_GPIO75__FUNC_SCP_SPI0_MI (MTK_PIN_NO(75) | 2)
+#define PINMUX_GPIO75__FUNC_URXD2 (MTK_PIN_NO(75) | 3)
+#define PINMUX_GPIO75__FUNC_TP_URXD2_VCORE (MTK_PIN_NO(75) | 4)
+#define PINMUX_GPIO75__FUNC_TP_GPIO15_AO (MTK_PIN_NO(75) | 5)
+#define PINMUX_GPIO75__FUNC_DAP_MD32_SWD (MTK_PIN_NO(75) | 7)
+
+#define PINMUX_GPIO76__FUNC_GPIO76 (MTK_PIN_NO(76) | 0)
+#define PINMUX_GPIO76__FUNC_AP_GOOD (MTK_PIN_NO(76) | 1)
+#define PINMUX_GPIO76__FUNC_CONN_WIFI_TXD (MTK_PIN_NO(76) | 3)
+#define PINMUX_GPIO76__FUNC_GPS_PPS (MTK_PIN_NO(76) | 4)
+#define PINMUX_GPIO76__FUNC_PMSR_SMAP (MTK_PIN_NO(76) | 5)
+#define PINMUX_GPIO76__FUNC_AGPS_SYNC (MTK_PIN_NO(76) | 6)
+
+#define PINMUX_GPIO77__FUNC_GPIO77 (MTK_PIN_NO(77) | 0)
+#define PINMUX_GPIO77__FUNC_MSDC1_CLK (MTK_PIN_NO(77) | 1)
+#define PINMUX_GPIO77__FUNC_MD1_SIM2_SCLK (MTK_PIN_NO(77) | 2)
+#define PINMUX_GPIO77__FUNC_UDI_TCK (MTK_PIN_NO(77) | 3)
+#define PINMUX_GPIO77__FUNC_CONN_DSP_JCK (MTK_PIN_NO(77) | 4)
+#define PINMUX_GPIO77__FUNC_TSFDC_EN (MTK_PIN_NO(77) | 6)
+#define PINMUX_GPIO77__FUNC_SSPM_JTAG_TCK_VCORE (MTK_PIN_NO(77) | 7)
+
+#define PINMUX_GPIO78__FUNC_GPIO78 (MTK_PIN_NO(78) | 0)
+#define PINMUX_GPIO78__FUNC_MSDC1_CMD (MTK_PIN_NO(78) | 1)
+#define PINMUX_GPIO78__FUNC_CONN_WF_MCU_AICE_TMSC (MTK_PIN_NO(78) | 2)
+#define PINMUX_GPIO78__FUNC_UDI_TMS (MTK_PIN_NO(78) | 3)
+#define PINMUX_GPIO78__FUNC_CONN_DSP_JMS (MTK_PIN_NO(78) | 4)
+#define PINMUX_GPIO78__FUNC_TSFDC_VCO_RST (MTK_PIN_NO(78) | 6)
+#define PINMUX_GPIO78__FUNC_SSPM_JTAG_TMS_VCORE (MTK_PIN_NO(78) | 7)
+
+#define PINMUX_GPIO79__FUNC_GPIO79 (MTK_PIN_NO(79) | 0)
+#define PINMUX_GPIO79__FUNC_MSDC1_DAT0 (MTK_PIN_NO(79) | 1)
+#define PINMUX_GPIO79__FUNC_MD1_SIM2_SRST (MTK_PIN_NO(79) | 2)
+#define PINMUX_GPIO79__FUNC_UDI_TDI (MTK_PIN_NO(79) | 3)
+#define PINMUX_GPIO79__FUNC_CONN_DSP_JDI (MTK_PIN_NO(79) | 4)
+#define PINMUX_GPIO79__FUNC_TSFDC_TSSEL2 (MTK_PIN_NO(79) | 6)
+#define PINMUX_GPIO79__FUNC_SSPM_JTAG_TDI_VCORE (MTK_PIN_NO(79) | 7)
+
+#define PINMUX_GPIO80__FUNC_GPIO80 (MTK_PIN_NO(80) | 0)
+#define PINMUX_GPIO80__FUNC_MSDC1_DAT1 (MTK_PIN_NO(80) | 1)
+#define PINMUX_GPIO80__FUNC_MD1_SIM2_SIO (MTK_PIN_NO(80) | 2)
+#define PINMUX_GPIO80__FUNC_UDI_TDO (MTK_PIN_NO(80) | 3)
+#define PINMUX_GPIO80__FUNC_CONN_DSP_JDO (MTK_PIN_NO(80) | 4)
+#define PINMUX_GPIO80__FUNC_TSFDC_TSSEL1 (MTK_PIN_NO(80) | 6)
+#define PINMUX_GPIO80__FUNC_SSPM_JTAG_TDO_VCORE (MTK_PIN_NO(80) | 7)
+
+#define PINMUX_GPIO81__FUNC_GPIO81 (MTK_PIN_NO(81) | 0)
+#define PINMUX_GPIO81__FUNC_MSDC1_DAT2 (MTK_PIN_NO(81) | 1)
+#define PINMUX_GPIO81__FUNC_CONN_WF_MCU_AICE_TCKC (MTK_PIN_NO(81) | 2)
+#define PINMUX_GPIO81__FUNC_UDI_NTRST (MTK_PIN_NO(81) | 3)
+#define PINMUX_GPIO81__FUNC_CONN_BGF_MCU_AICE_TCKC (MTK_PIN_NO(81) | 4)
+#define PINMUX_GPIO81__FUNC_MIPI3_D_SDATA (MTK_PIN_NO(81) | 5)
+#define PINMUX_GPIO81__FUNC_TSFDC_TSSEL0 (MTK_PIN_NO(81) | 6)
+#define PINMUX_GPIO81__FUNC_SSPM_JTAG_TRSTN_VCORE (MTK_PIN_NO(81) | 7)
+
+#define PINMUX_GPIO82__FUNC_GPIO82 (MTK_PIN_NO(82) | 0)
+#define PINMUX_GPIO82__FUNC_MSDC1_DAT3 (MTK_PIN_NO(82) | 1)
+#define PINMUX_GPIO82__FUNC_CONN_BGF_MCU_AICE_TMSC (MTK_PIN_NO(82) | 3)
+#define PINMUX_GPIO82__FUNC_CONN_DSP_JINTP (MTK_PIN_NO(82) | 4)
+#define PINMUX_GPIO82__FUNC_MIPI3_D_SCLK (MTK_PIN_NO(82) | 5)
+#define PINMUX_GPIO82__FUNC_TSFDC_RCK_SELB (MTK_PIN_NO(82) | 6)
+
+#define PINMUX_GPIO83__FUNC_GPIO83 (MTK_PIN_NO(83) | 0)
+#define PINMUX_GPIO83__FUNC_MD1_SIM1_SCLK (MTK_PIN_NO(83) | 1)
+#define PINMUX_GPIO83__FUNC_TSFDC_26M (MTK_PIN_NO(83) | 6)
+
+#define PINMUX_GPIO84__FUNC_GPIO84 (MTK_PIN_NO(84) | 0)
+#define PINMUX_GPIO84__FUNC_MD1_SIM1_SRST (MTK_PIN_NO(84) | 1)
+#define PINMUX_GPIO84__FUNC_SPM_JTAG_TCK_VCORE (MTK_PIN_NO(84) | 3)
+#define PINMUX_GPIO84__FUNC_APU_JTAG_TCK (MTK_PIN_NO(84) | 4)
+#define PINMUX_GPIO84__FUNC_TSFDC_SDO (MTK_PIN_NO(84) | 6)
+#define PINMUX_GPIO84__FUNC_CONN_DSP_L5_JCK (MTK_PIN_NO(84) | 7)
+
+#define PINMUX_GPIO85__FUNC_GPIO85 (MTK_PIN_NO(85) | 0)
+#define PINMUX_GPIO85__FUNC_MD1_SIM1_SIO (MTK_PIN_NO(85) | 1)
+#define PINMUX_GPIO85__FUNC_SPM_JTAG_TRSTN_VCORE (MTK_PIN_NO(85) | 3)
+#define PINMUX_GPIO85__FUNC_APU_JTAG_TRST (MTK_PIN_NO(85) | 4)
+#define PINMUX_GPIO85__FUNC_TSFDC_FOUT (MTK_PIN_NO(85) | 6)
+#define PINMUX_GPIO85__FUNC_CONN_DSP_L5_JINTP (MTK_PIN_NO(85) | 7)
+
+#define PINMUX_GPIO86__FUNC_GPIO86 (MTK_PIN_NO(86) | 0)
+#define PINMUX_GPIO86__FUNC_MD1_SIM2_SCLK (MTK_PIN_NO(86) | 1)
+#define PINMUX_GPIO86__FUNC_SPM_JTAG_TDI_VCORE (MTK_PIN_NO(86) | 3)
+#define PINMUX_GPIO86__FUNC_APU_JTAG_TDI (MTK_PIN_NO(86) | 4)
+#define PINMUX_GPIO86__FUNC_TSFDC_SCK (MTK_PIN_NO(86) | 6)
+#define PINMUX_GPIO86__FUNC_CONN_DSP_L5_JDI (MTK_PIN_NO(86) | 7)
+
+#define PINMUX_GPIO87__FUNC_GPIO87 (MTK_PIN_NO(87) | 0)
+#define PINMUX_GPIO87__FUNC_MD1_SIM2_SRST (MTK_PIN_NO(87) | 1)
+#define PINMUX_GPIO87__FUNC_SPM_JTAG_TMS_VCORE (MTK_PIN_NO(87) | 3)
+#define PINMUX_GPIO87__FUNC_APU_JTAG_TMS (MTK_PIN_NO(87) | 4)
+#define PINMUX_GPIO87__FUNC_TSFDC_SDI (MTK_PIN_NO(87) | 6)
+#define PINMUX_GPIO87__FUNC_CONN_DSP_L5_JMS (MTK_PIN_NO(87) | 7)
+
+#define PINMUX_GPIO88__FUNC_GPIO88 (MTK_PIN_NO(88) | 0)
+#define PINMUX_GPIO88__FUNC_MD1_SIM2_SIO (MTK_PIN_NO(88) | 1)
+#define PINMUX_GPIO88__FUNC_SPM_JTAG_TDO_VCORE (MTK_PIN_NO(88) | 3)
+#define PINMUX_GPIO88__FUNC_APU_JTAG_TDO (MTK_PIN_NO(88) | 4)
+#define PINMUX_GPIO88__FUNC_TSFDC_SCF (MTK_PIN_NO(88) | 6)
+#define PINMUX_GPIO88__FUNC_CONN_DSP_L5_JDO (MTK_PIN_NO(88) | 7)
+
+#define PINMUX_GPIO89__FUNC_GPIO89 (MTK_PIN_NO(89) | 0)
+#define PINMUX_GPIO89__FUNC_DSI_TE (MTK_PIN_NO(89) | 1)
+#define PINMUX_GPIO89__FUNC_DBG_MON_B8 (MTK_PIN_NO(89) | 7)
+
+#define PINMUX_GPIO90__FUNC_GPIO90 (MTK_PIN_NO(90) | 0)
+#define PINMUX_GPIO90__FUNC_LCM_RST (MTK_PIN_NO(90) | 1)
+#define PINMUX_GPIO90__FUNC_DBG_MON_B9 (MTK_PIN_NO(90) | 7)
+
+#define PINMUX_GPIO91__FUNC_GPIO91 (MTK_PIN_NO(91) | 0)
+#define PINMUX_GPIO91__FUNC_DISP_PWM (MTK_PIN_NO(91) | 1)
+#define PINMUX_GPIO91__FUNC_DBG_MON_B10 (MTK_PIN_NO(91) | 7)
+
+#define PINMUX_GPIO92__FUNC_GPIO92 (MTK_PIN_NO(92) | 0)
+#define PINMUX_GPIO92__FUNC_CMMCLK0 (MTK_PIN_NO(92) | 1)
+#define PINMUX_GPIO92__FUNC_DBG_MON_A23 (MTK_PIN_NO(92) | 7)
+
+#define PINMUX_GPIO93__FUNC_GPIO93 (MTK_PIN_NO(93) | 0)
+#define PINMUX_GPIO93__FUNC_CMMCLK1 (MTK_PIN_NO(93) | 1)
+#define PINMUX_GPIO93__FUNC_DBG_MON_A24 (MTK_PIN_NO(93) | 7)
+
+#define PINMUX_GPIO94__FUNC_GPIO94 (MTK_PIN_NO(94) | 0)
+#define PINMUX_GPIO94__FUNC_CMMCLK2 (MTK_PIN_NO(94) | 1)
+#define PINMUX_GPIO94__FUNC_DBG_MON_A25 (MTK_PIN_NO(94) | 7)
+
+#define PINMUX_GPIO95__FUNC_GPIO95 (MTK_PIN_NO(95) | 0)
+#define PINMUX_GPIO95__FUNC_CMMCLK3 (MTK_PIN_NO(95) | 1)
+#define PINMUX_GPIO95__FUNC_MD32_1_TXD (MTK_PIN_NO(95) | 5)
+#define PINMUX_GPIO95__FUNC_PTA_TXD (MTK_PIN_NO(95) | 6)
+#define PINMUX_GPIO95__FUNC_DBG_MON_A26 (MTK_PIN_NO(95) | 7)
+
+#define PINMUX_GPIO96__FUNC_GPIO96 (MTK_PIN_NO(96) | 0)
+#define PINMUX_GPIO96__FUNC_CMMCLK4 (MTK_PIN_NO(96) | 1)
+#define PINMUX_GPIO96__FUNC_MD32_1_RXD (MTK_PIN_NO(96) | 5)
+#define PINMUX_GPIO96__FUNC_PTA_RXD (MTK_PIN_NO(96) | 6)
+#define PINMUX_GPIO96__FUNC_DBG_MON_A27 (MTK_PIN_NO(96) | 7)
+
+#define PINMUX_GPIO97__FUNC_GPIO97 (MTK_PIN_NO(97) | 0)
+#define PINMUX_GPIO97__FUNC_MD_UCNT_A_TGL (MTK_PIN_NO(97) | 1)
+
+#define PINMUX_GPIO98__FUNC_GPIO98 (MTK_PIN_NO(98) | 0)
+#define PINMUX_GPIO98__FUNC_DIGRF_IRQ (MTK_PIN_NO(98) | 1)
+
+#define PINMUX_GPIO99__FUNC_GPIO99 (MTK_PIN_NO(99) | 0)
+#define PINMUX_GPIO99__FUNC_BPI_BUS0 (MTK_PIN_NO(99) | 1)
+#define PINMUX_GPIO99__FUNC_MFG_TSFDC_EN (MTK_PIN_NO(99) | 4)
+#define PINMUX_GPIO99__FUNC_ANT_SEL0 (MTK_PIN_NO(99) | 6)
+#define PINMUX_GPIO99__FUNC_DBG_MON_B11 (MTK_PIN_NO(99) | 7)
+
+#define PINMUX_GPIO100__FUNC_GPIO100 (MTK_PIN_NO(100) | 0)
+#define PINMUX_GPIO100__FUNC_BPI_BUS1 (MTK_PIN_NO(100) | 1)
+#define PINMUX_GPIO100__FUNC_MFG_TSFDC_VCO_RST (MTK_PIN_NO(100) | 4)
+#define PINMUX_GPIO100__FUNC_ANT_SEL1 (MTK_PIN_NO(100) | 6)
+#define PINMUX_GPIO100__FUNC_DBG_MON_B12 (MTK_PIN_NO(100) | 7)
+
+#define PINMUX_GPIO101__FUNC_GPIO101 (MTK_PIN_NO(101) | 0)
+#define PINMUX_GPIO101__FUNC_BPI_BUS2 (MTK_PIN_NO(101) | 1)
+#define PINMUX_GPIO101__FUNC_DMIC1_CLK (MTK_PIN_NO(101) | 3)
+#define PINMUX_GPIO101__FUNC_MFG_TSFDC_TSSEL2 (MTK_PIN_NO(101) | 4)
+#define PINMUX_GPIO101__FUNC_ANT_SEL2 (MTK_PIN_NO(101) | 6)
+#define PINMUX_GPIO101__FUNC_DBG_MON_B13 (MTK_PIN_NO(101) | 7)
+
+#define PINMUX_GPIO102__FUNC_GPIO102 (MTK_PIN_NO(102) | 0)
+#define PINMUX_GPIO102__FUNC_BPI_BUS3 (MTK_PIN_NO(102) | 1)
+#define PINMUX_GPIO102__FUNC_DMIC1_DAT (MTK_PIN_NO(102) | 3)
+#define PINMUX_GPIO102__FUNC_MFG_TSFDC_TSSEL1 (MTK_PIN_NO(102) | 4)
+#define PINMUX_GPIO102__FUNC_ANT_SEL3 (MTK_PIN_NO(102) | 6)
+#define PINMUX_GPIO102__FUNC_DBG_MON_B14 (MTK_PIN_NO(102) | 7)
+
+#define PINMUX_GPIO103__FUNC_GPIO103 (MTK_PIN_NO(103) | 0)
+#define PINMUX_GPIO103__FUNC_BPI_BUS4 (MTK_PIN_NO(103) | 1)
+#define PINMUX_GPIO103__FUNC_MFG_TSFDC_TSSEL0 (MTK_PIN_NO(103) | 4)
+#define PINMUX_GPIO103__FUNC_ANT_SEL4 (MTK_PIN_NO(103) | 6)
+#define PINMUX_GPIO103__FUNC_DBG_MON_B15 (MTK_PIN_NO(103) | 7)
+
+#define PINMUX_GPIO104__FUNC_GPIO104 (MTK_PIN_NO(104) | 0)
+#define PINMUX_GPIO104__FUNC_BPI_BUS5 (MTK_PIN_NO(104) | 1)
+#define PINMUX_GPIO104__FUNC_MFG_TSFDC_RCK_SELB (MTK_PIN_NO(104) | 4)
+#define PINMUX_GPIO104__FUNC_ANT_SEL5 (MTK_PIN_NO(104) | 6)
+#define PINMUX_GPIO104__FUNC_DBG_MON_B16 (MTK_PIN_NO(104) | 7)
+
+#define PINMUX_GPIO105__FUNC_GPIO105 (MTK_PIN_NO(105) | 0)
+#define PINMUX_GPIO105__FUNC_BPI_BUS6 (MTK_PIN_NO(105) | 1)
+#define PINMUX_GPIO105__FUNC_CONN_BPI_BUS6 (MTK_PIN_NO(105) | 2)
+#define PINMUX_GPIO105__FUNC_ANT_SEL6 (MTK_PIN_NO(105) | 6)
+#define PINMUX_GPIO105__FUNC_DBG_MON_B17 (MTK_PIN_NO(105) | 7)
+
+#define PINMUX_GPIO106__FUNC_GPIO106 (MTK_PIN_NO(106) | 0)
+#define PINMUX_GPIO106__FUNC_BPI_BUS7 (MTK_PIN_NO(106) | 1)
+#define PINMUX_GPIO106__FUNC_CONN_BPI_BUS7 (MTK_PIN_NO(106) | 2)
+#define PINMUX_GPIO106__FUNC_MFG_TSFDC_SDO (MTK_PIN_NO(106) | 4)
+#define PINMUX_GPIO106__FUNC_AUD_DAC_26M_CLK (MTK_PIN_NO(106) | 5)
+#define PINMUX_GPIO106__FUNC_ANT_SEL7 (MTK_PIN_NO(106) | 6)
+#define PINMUX_GPIO106__FUNC_DBG_MON_B18 (MTK_PIN_NO(106) | 7)
+
+#define PINMUX_GPIO107__FUNC_GPIO107 (MTK_PIN_NO(107) | 0)
+#define PINMUX_GPIO107__FUNC_BPI_BUS8 (MTK_PIN_NO(107) | 1)
+#define PINMUX_GPIO107__FUNC_CONN_BPI_BUS8 (MTK_PIN_NO(107) | 2)
+#define PINMUX_GPIO107__FUNC_MFG_TSFDC_FOUT (MTK_PIN_NO(107) | 4)
+#define PINMUX_GPIO107__FUNC_I2SOUT4_DATA0 (MTK_PIN_NO(107) | 5)
+#define PINMUX_GPIO107__FUNC_ANT_SEL8 (MTK_PIN_NO(107) | 6)
+#define PINMUX_GPIO107__FUNC_DBG_MON_B19 (MTK_PIN_NO(107) | 7)
+
+#define PINMUX_GPIO108__FUNC_GPIO108 (MTK_PIN_NO(108) | 0)
+#define PINMUX_GPIO108__FUNC_BPI_BUS9 (MTK_PIN_NO(108) | 1)
+#define PINMUX_GPIO108__FUNC_CONN_BPI_BUS9 (MTK_PIN_NO(108) | 2)
+#define PINMUX_GPIO108__FUNC_I2SOUT4_DATA1 (MTK_PIN_NO(108) | 5)
+#define PINMUX_GPIO108__FUNC_ANT_SEL9 (MTK_PIN_NO(108) | 6)
+#define PINMUX_GPIO108__FUNC_DBG_MON_B20 (MTK_PIN_NO(108) | 7)
+
+#define PINMUX_GPIO109__FUNC_GPIO109 (MTK_PIN_NO(109) | 0)
+#define PINMUX_GPIO109__FUNC_BPI_BUS10 (MTK_PIN_NO(109) | 1)
+#define PINMUX_GPIO109__FUNC_CONN_BPI_BUS10 (MTK_PIN_NO(109) | 2)
+#define PINMUX_GPIO109__FUNC_I2SOUT4_DATA2 (MTK_PIN_NO(109) | 5)
+#define PINMUX_GPIO109__FUNC_ANT_SEL10 (MTK_PIN_NO(109) | 6)
+#define PINMUX_GPIO109__FUNC_DBG_MON_B21 (MTK_PIN_NO(109) | 7)
+
+#define PINMUX_GPIO110__FUNC_GPIO110 (MTK_PIN_NO(110) | 0)
+#define PINMUX_GPIO110__FUNC_BPI_BUS11 (MTK_PIN_NO(110) | 1)
+#define PINMUX_GPIO110__FUNC_CONN_BPI_BUS11_OLAT0 (MTK_PIN_NO(110) | 2)
+#define PINMUX_GPIO110__FUNC_I2SOUT4_DATA3 (MTK_PIN_NO(110) | 5)
+#define PINMUX_GPIO110__FUNC_ANT_SEL11 (MTK_PIN_NO(110) | 6)
+#define PINMUX_GPIO110__FUNC_DBG_MON_B22 (MTK_PIN_NO(110) | 7)
+
+#define PINMUX_GPIO111__FUNC_GPIO111 (MTK_PIN_NO(111) | 0)
+#define PINMUX_GPIO111__FUNC_BPI_BUS12 (MTK_PIN_NO(111) | 1)
+#define PINMUX_GPIO111__FUNC_CONN_BPI_BUS12_OLAT1 (MTK_PIN_NO(111) | 2)
+#define PINMUX_GPIO111__FUNC_CLKM0 (MTK_PIN_NO(111) | 3)
+#define PINMUX_GPIO111__FUNC_I2SIN4_BCK (MTK_PIN_NO(111) | 5)
+#define PINMUX_GPIO111__FUNC_ANT_SEL12 (MTK_PIN_NO(111) | 6)
+#define PINMUX_GPIO111__FUNC_DBG_MON_B23 (MTK_PIN_NO(111) | 7)
+
+#define PINMUX_GPIO112__FUNC_GPIO112 (MTK_PIN_NO(112) | 0)
+#define PINMUX_GPIO112__FUNC_BPI_BUS13 (MTK_PIN_NO(112) | 1)
+#define PINMUX_GPIO112__FUNC_CONN_BPI_BUS13_OLAT2 (MTK_PIN_NO(112) | 2)
+#define PINMUX_GPIO112__FUNC_CLKM1 (MTK_PIN_NO(112) | 3)
+#define PINMUX_GPIO112__FUNC_I2SIN4_DATA0 (MTK_PIN_NO(112) | 5)
+#define PINMUX_GPIO112__FUNC_ANT_SEL13 (MTK_PIN_NO(112) | 6)
+#define PINMUX_GPIO112__FUNC_DBG_MON_B24 (MTK_PIN_NO(112) | 7)
+
+#define PINMUX_GPIO113__FUNC_GPIO113 (MTK_PIN_NO(113) | 0)
+#define PINMUX_GPIO113__FUNC_BPI_BUS14 (MTK_PIN_NO(113) | 1)
+#define PINMUX_GPIO113__FUNC_CONN_BPI_BUS14_OLAT3 (MTK_PIN_NO(113) | 2)
+#define PINMUX_GPIO113__FUNC_CLKM2 (MTK_PIN_NO(113) | 3)
+#define PINMUX_GPIO113__FUNC_I2SIN4_DATA1 (MTK_PIN_NO(113) | 5)
+#define PINMUX_GPIO113__FUNC_ANT_SEL14 (MTK_PIN_NO(113) | 6)
+#define PINMUX_GPIO113__FUNC_DBG_MON_B25 (MTK_PIN_NO(113) | 7)
+
+#define PINMUX_GPIO114__FUNC_GPIO114 (MTK_PIN_NO(114) | 0)
+#define PINMUX_GPIO114__FUNC_BPI_BUS15 (MTK_PIN_NO(114) | 1)
+#define PINMUX_GPIO114__FUNC_CONN_BPI_BUS15_OLAT4 (MTK_PIN_NO(114) | 2)
+#define PINMUX_GPIO114__FUNC_CLKM3 (MTK_PIN_NO(114) | 3)
+#define PINMUX_GPIO114__FUNC_I2SIN4_DATA2 (MTK_PIN_NO(114) | 5)
+#define PINMUX_GPIO114__FUNC_ANT_SEL15 (MTK_PIN_NO(114) | 6)
+#define PINMUX_GPIO114__FUNC_DBG_MON_B26 (MTK_PIN_NO(114) | 7)
+
+#define PINMUX_GPIO115__FUNC_GPIO115 (MTK_PIN_NO(115) | 0)
+#define PINMUX_GPIO115__FUNC_BPI_BUS16 (MTK_PIN_NO(115) | 1)
+#define PINMUX_GPIO115__FUNC_CONN_BPI_BUS16_OLAT5 (MTK_PIN_NO(115) | 2)
+#define PINMUX_GPIO115__FUNC_I2SIN4_DATA3 (MTK_PIN_NO(115) | 5)
+#define PINMUX_GPIO115__FUNC_ANT_SEL16 (MTK_PIN_NO(115) | 6)
+#define PINMUX_GPIO115__FUNC_DBG_MON_B27 (MTK_PIN_NO(115) | 7)
+
+#define PINMUX_GPIO116__FUNC_GPIO116 (MTK_PIN_NO(116) | 0)
+#define PINMUX_GPIO116__FUNC_BPI_BUS17 (MTK_PIN_NO(116) | 1)
+#define PINMUX_GPIO116__FUNC_CONN_BPI_BUS17_ANT0 (MTK_PIN_NO(116) | 2)
+#define PINMUX_GPIO116__FUNC_I2SIN4_LRCK (MTK_PIN_NO(116) | 5)
+#define PINMUX_GPIO116__FUNC_ANT_SEL17 (MTK_PIN_NO(116) | 6)
+#define PINMUX_GPIO116__FUNC_DBG_MON_B28 (MTK_PIN_NO(116) | 7)
+
+#define PINMUX_GPIO117__FUNC_GPIO117 (MTK_PIN_NO(117) | 0)
+#define PINMUX_GPIO117__FUNC_MIPI0_D_SCLK (MTK_PIN_NO(117) | 1)
+#define PINMUX_GPIO117__FUNC_CONN_MIPI0_SCLK (MTK_PIN_NO(117) | 2)
+#define PINMUX_GPIO117__FUNC_BPI_BUS18 (MTK_PIN_NO(117) | 3)
+#define PINMUX_GPIO117__FUNC_ANT_SEL18 (MTK_PIN_NO(117) | 6)
+
+#define PINMUX_GPIO118__FUNC_GPIO118 (MTK_PIN_NO(118) | 0)
+#define PINMUX_GPIO118__FUNC_MIPI0_D_SDATA (MTK_PIN_NO(118) | 1)
+#define PINMUX_GPIO118__FUNC_CONN_MIPI0_SDATA (MTK_PIN_NO(118) | 2)
+#define PINMUX_GPIO118__FUNC_BPI_BUS19 (MTK_PIN_NO(118) | 3)
+#define PINMUX_GPIO118__FUNC_ANT_SEL19 (MTK_PIN_NO(118) | 6)
+
+#define PINMUX_GPIO119__FUNC_GPIO119 (MTK_PIN_NO(119) | 0)
+#define PINMUX_GPIO119__FUNC_MIPI1_D_SCLK (MTK_PIN_NO(119) | 1)
+#define PINMUX_GPIO119__FUNC_CONN_MIPI1_SCLK (MTK_PIN_NO(119) | 2)
+#define PINMUX_GPIO119__FUNC_BPI_BUS20 (MTK_PIN_NO(119) | 3)
+#define PINMUX_GPIO119__FUNC_ANT_SEL20 (MTK_PIN_NO(119) | 6)
+
+#define PINMUX_GPIO120__FUNC_GPIO120 (MTK_PIN_NO(120) | 0)
+#define PINMUX_GPIO120__FUNC_MIPI1_D_SDATA (MTK_PIN_NO(120) | 1)
+#define PINMUX_GPIO120__FUNC_CONN_MIPI1_SDATA (MTK_PIN_NO(120) | 2)
+#define PINMUX_GPIO120__FUNC_BPI_BUS21 (MTK_PIN_NO(120) | 3)
+#define PINMUX_GPIO120__FUNC_ANT_SEL21 (MTK_PIN_NO(120) | 6)
+
+#define PINMUX_GPIO121__FUNC_GPIO121 (MTK_PIN_NO(121) | 0)
+#define PINMUX_GPIO121__FUNC_MIPI2_D_SCLK (MTK_PIN_NO(121) | 1)
+#define PINMUX_GPIO121__FUNC_MIPI4_D_SCLK (MTK_PIN_NO(121) | 2)
+#define PINMUX_GPIO121__FUNC_BPI_BUS22 (MTK_PIN_NO(121) | 3)
+#define PINMUX_GPIO121__FUNC_MD_GPS_L1_BLANK (MTK_PIN_NO(121) | 6)
+
+#define PINMUX_GPIO122__FUNC_GPIO122 (MTK_PIN_NO(122) | 0)
+#define PINMUX_GPIO122__FUNC_MIPI2_D_SDATA (MTK_PIN_NO(122) | 1)
+#define PINMUX_GPIO122__FUNC_MIPI4_D_SDATA (MTK_PIN_NO(122) | 2)
+#define PINMUX_GPIO122__FUNC_BPI_BUS23 (MTK_PIN_NO(122) | 3)
+#define PINMUX_GPIO122__FUNC_MD_GPS_L5_BLANK (MTK_PIN_NO(122) | 6)
+
+#define PINMUX_GPIO123__FUNC_GPIO123 (MTK_PIN_NO(123) | 0)
+#define PINMUX_GPIO123__FUNC_MIPI_M_SCLK (MTK_PIN_NO(123) | 1)
+
+#define PINMUX_GPIO124__FUNC_GPIO124 (MTK_PIN_NO(124) | 0)
+#define PINMUX_GPIO124__FUNC_MIPI_M_SDATA (MTK_PIN_NO(124) | 1)
+
+#define PINMUX_GPIO125__FUNC_GPIO125 (MTK_PIN_NO(125) | 0)
+#define PINMUX_GPIO125__FUNC_SCL0 (MTK_PIN_NO(125) | 1)
+#define PINMUX_GPIO125__FUNC_SCP_SCL4 (MTK_PIN_NO(125) | 2)
+#define PINMUX_GPIO125__FUNC_TP_UTXD2_VLP (MTK_PIN_NO(125) | 3)
+#define PINMUX_GPIO125__FUNC_TP_UCTS1_VLP (MTK_PIN_NO(125) | 4)
+#define PINMUX_GPIO125__FUNC_TP_GPIO4_AO (MTK_PIN_NO(125) | 5)
+#define PINMUX_GPIO125__FUNC_UTXD2 (MTK_PIN_NO(125) | 6)
+
+#define PINMUX_GPIO126__FUNC_GPIO126 (MTK_PIN_NO(126) | 0)
+#define PINMUX_GPIO126__FUNC_SDA0 (MTK_PIN_NO(126) | 1)
+#define PINMUX_GPIO126__FUNC_SCP_SDA4 (MTK_PIN_NO(126) | 2)
+#define PINMUX_GPIO126__FUNC_TP_URXD2_VLP (MTK_PIN_NO(126) | 3)
+#define PINMUX_GPIO126__FUNC_TP_URTS1_VLP (MTK_PIN_NO(126) | 4)
+#define PINMUX_GPIO126__FUNC_TP_GPIO5_AO (MTK_PIN_NO(126) | 5)
+#define PINMUX_GPIO126__FUNC_URXD2 (MTK_PIN_NO(126) | 6)
+
+#define PINMUX_GPIO127__FUNC_GPIO127 (MTK_PIN_NO(127) | 0)
+#define PINMUX_GPIO127__FUNC_SCL1 (MTK_PIN_NO(127) | 1)
+#define PINMUX_GPIO127__FUNC_SCP_SCL5 (MTK_PIN_NO(127) | 2)
+#define PINMUX_GPIO127__FUNC_TP_UCTS2_VLP (MTK_PIN_NO(127) | 3)
+#define PINMUX_GPIO127__FUNC_TP_UTXD1_VLP (MTK_PIN_NO(127) | 4)
+#define PINMUX_GPIO127__FUNC_TP_GPIO6_AO (MTK_PIN_NO(127) | 5)
+#define PINMUX_GPIO127__FUNC_MD_MCIF_UTXD0 (MTK_PIN_NO(127) | 6)
+
+#define PINMUX_GPIO128__FUNC_GPIO128 (MTK_PIN_NO(128) | 0)
+#define PINMUX_GPIO128__FUNC_SDA1 (MTK_PIN_NO(128) | 1)
+#define PINMUX_GPIO128__FUNC_SCP_SDA5 (MTK_PIN_NO(128) | 2)
+#define PINMUX_GPIO128__FUNC_TP_URTS2_VLP (MTK_PIN_NO(128) | 3)
+#define PINMUX_GPIO128__FUNC_TP_URXD1_VLP (MTK_PIN_NO(128) | 4)
+#define PINMUX_GPIO128__FUNC_TP_GPIO7_AO (MTK_PIN_NO(128) | 5)
+#define PINMUX_GPIO128__FUNC_MD_MCIF_URXD0 (MTK_PIN_NO(128) | 6)
+
+#define PINMUX_GPIO129__FUNC_GPIO129 (MTK_PIN_NO(129) | 0)
+#define PINMUX_GPIO129__FUNC_SCL2 (MTK_PIN_NO(129) | 1)
+
+#define PINMUX_GPIO130__FUNC_GPIO130 (MTK_PIN_NO(130) | 0)
+#define PINMUX_GPIO130__FUNC_SDA2 (MTK_PIN_NO(130) | 1)
+
+#define PINMUX_GPIO131__FUNC_GPIO131 (MTK_PIN_NO(131) | 0)
+#define PINMUX_GPIO131__FUNC_SCL3 (MTK_PIN_NO(131) | 1)
+#define PINMUX_GPIO131__FUNC_TP_UTXD2_VCORE (MTK_PIN_NO(131) | 3)
+#define PINMUX_GPIO131__FUNC_SSPM_UTXD_AO_VCORE (MTK_PIN_NO(131) | 6)
+
+#define PINMUX_GPIO132__FUNC_GPIO132 (MTK_PIN_NO(132) | 0)
+#define PINMUX_GPIO132__FUNC_SDA3 (MTK_PIN_NO(132) | 1)
+#define PINMUX_GPIO132__FUNC_TP_URXD2_VCORE (MTK_PIN_NO(132) | 3)
+#define PINMUX_GPIO132__FUNC_SSPM_URXD_AO_VCORE (MTK_PIN_NO(132) | 6)
+
+#define PINMUX_GPIO133__FUNC_GPIO133 (MTK_PIN_NO(133) | 0)
+#define PINMUX_GPIO133__FUNC_SCL4 (MTK_PIN_NO(133) | 1)
+
+#define PINMUX_GPIO134__FUNC_GPIO134 (MTK_PIN_NO(134) | 0)
+#define PINMUX_GPIO134__FUNC_SDA4 (MTK_PIN_NO(134) | 1)
+
+#define PINMUX_GPIO135__FUNC_GPIO135 (MTK_PIN_NO(135) | 0)
+#define PINMUX_GPIO135__FUNC_SCL5 (MTK_PIN_NO(135) | 1)
+
+#define PINMUX_GPIO136__FUNC_GPIO136 (MTK_PIN_NO(136) | 0)
+#define PINMUX_GPIO136__FUNC_SDA5 (MTK_PIN_NO(136) | 1)
+
+#define PINMUX_GPIO137__FUNC_GPIO137 (MTK_PIN_NO(137) | 0)
+#define PINMUX_GPIO137__FUNC_SCL6 (MTK_PIN_NO(137) | 1)
+
+#define PINMUX_GPIO138__FUNC_GPIO138 (MTK_PIN_NO(138) | 0)
+#define PINMUX_GPIO138__FUNC_SDA6 (MTK_PIN_NO(138) | 1)
+
+#define PINMUX_GPIO139__FUNC_GPIO139 (MTK_PIN_NO(139) | 0)
+#define PINMUX_GPIO139__FUNC_SCL7 (MTK_PIN_NO(139) | 1)
+#define PINMUX_GPIO139__FUNC_TP_UTXD1_VCORE (MTK_PIN_NO(139) | 3)
+#define PINMUX_GPIO139__FUNC_MD_UTXD0 (MTK_PIN_NO(139) | 4)
+#define PINMUX_GPIO139__FUNC_UTXD1 (MTK_PIN_NO(139) | 6)
+
+#define PINMUX_GPIO140__FUNC_GPIO140 (MTK_PIN_NO(140) | 0)
+#define PINMUX_GPIO140__FUNC_SDA7 (MTK_PIN_NO(140) | 1)
+#define PINMUX_GPIO140__FUNC_TP_URXD1_VCORE (MTK_PIN_NO(140) | 3)
+#define PINMUX_GPIO140__FUNC_MD_URXD0 (MTK_PIN_NO(140) | 4)
+#define PINMUX_GPIO140__FUNC_URXD1 (MTK_PIN_NO(140) | 6)
+
+#define PINMUX_GPIO141__FUNC_GPIO141 (MTK_PIN_NO(141) | 0)
+#define PINMUX_GPIO141__FUNC_SCL8 (MTK_PIN_NO(141) | 1)
+
+#define PINMUX_GPIO142__FUNC_GPIO142 (MTK_PIN_NO(142) | 0)
+#define PINMUX_GPIO142__FUNC_SDA8 (MTK_PIN_NO(142) | 1)
+
+#define PINMUX_GPIO143__FUNC_GPIO143 (MTK_PIN_NO(143) | 0)
+#define PINMUX_GPIO143__FUNC_SCL9 (MTK_PIN_NO(143) | 1)
+#define PINMUX_GPIO143__FUNC_GPS_L1_ELNA_EN (MTK_PIN_NO(143) | 2)
+#define PINMUX_GPIO143__FUNC_HFRP_UTXD1 (MTK_PIN_NO(143) | 3)
+#define PINMUX_GPIO143__FUNC_CONN_BGF_MCU_AICE_TMSC (MTK_PIN_NO(143) | 4)
+#define PINMUX_GPIO143__FUNC_CONN_WF_MCU_AICE_TMSC (MTK_PIN_NO(143) | 5)
+#define PINMUX_GPIO143__FUNC_MBISTREADEN_TRIGGER (MTK_PIN_NO(143) | 7)
+
+#define PINMUX_GPIO144__FUNC_GPIO144 (MTK_PIN_NO(144) | 0)
+#define PINMUX_GPIO144__FUNC_SDA9 (MTK_PIN_NO(144) | 1)
+#define PINMUX_GPIO144__FUNC_GPS_L5_ELNA_EN (MTK_PIN_NO(144) | 2)
+#define PINMUX_GPIO144__FUNC_HFRP_URXD1 (MTK_PIN_NO(144) | 3)
+#define PINMUX_GPIO144__FUNC_CONN_BGF_MCU_AICE_TCKC (MTK_PIN_NO(144) | 4)
+#define PINMUX_GPIO144__FUNC_CONN_WF_MCU_AICE_TCKC (MTK_PIN_NO(144) | 5)
+#define PINMUX_GPIO144__FUNC_MBISTWRITEEN_TRIGGER (MTK_PIN_NO(144) | 7)
+
+#define PINMUX_GPIO145__FUNC_GPIO145 (MTK_PIN_NO(145) | 0)
+#define PINMUX_GPIO145__FUNC_SCL10 (MTK_PIN_NO(145) | 1)
+#define PINMUX_GPIO145__FUNC_SCP_SCL0 (MTK_PIN_NO(145) | 2)
+#define PINMUX_GPIO145__FUNC_TP_GPIO8_AO (MTK_PIN_NO(145) | 5)
+
+#define PINMUX_GPIO146__FUNC_GPIO146 (MTK_PIN_NO(146) | 0)
+#define PINMUX_GPIO146__FUNC_SDA10 (MTK_PIN_NO(146) | 1)
+#define PINMUX_GPIO146__FUNC_SCP_SDA0 (MTK_PIN_NO(146) | 2)
+#define PINMUX_GPIO146__FUNC_TP_GPIO9_AO (MTK_PIN_NO(146) | 5)
+
+#define PINMUX_GPIO147__FUNC_GPIO147 (MTK_PIN_NO(147) | 0)
+#define PINMUX_GPIO147__FUNC_SCL11 (MTK_PIN_NO(147) | 1)
+#define PINMUX_GPIO147__FUNC_SCP_SCL1 (MTK_PIN_NO(147) | 2)
+#define PINMUX_GPIO147__FUNC_SCP_DMIC_CLK (MTK_PIN_NO(147) | 3)
+#define PINMUX_GPIO147__FUNC_DMIC_CLK (MTK_PIN_NO(147) | 4)
+#define PINMUX_GPIO147__FUNC_TP_GPIO10_AO (MTK_PIN_NO(147) | 5)
+#define PINMUX_GPIO147__FUNC_EXTIF0_PRI (MTK_PIN_NO(147) | 6)
+
+#define PINMUX_GPIO148__FUNC_GPIO148 (MTK_PIN_NO(148) | 0)
+#define PINMUX_GPIO148__FUNC_SDA11 (MTK_PIN_NO(148) | 1)
+#define PINMUX_GPIO148__FUNC_SCP_SDA1 (MTK_PIN_NO(148) | 2)
+#define PINMUX_GPIO148__FUNC_SCP_DMIC_DAT (MTK_PIN_NO(148) | 3)
+#define PINMUX_GPIO148__FUNC_DMIC_DAT (MTK_PIN_NO(148) | 4)
+#define PINMUX_GPIO148__FUNC_TP_GPIO11_AO (MTK_PIN_NO(148) | 5)
+#define PINMUX_GPIO148__FUNC_EXTIF0_GNT_B (MTK_PIN_NO(148) | 6)
+
+#define PINMUX_GPIO149__FUNC_GPIO149 (MTK_PIN_NO(149) | 0)
+#define PINMUX_GPIO149__FUNC_KPROW2 (MTK_PIN_NO(149) | 1)
+#define PINMUX_GPIO149__FUNC_PWM_VLP (MTK_PIN_NO(149) | 2)
+#define PINMUX_GPIO149__FUNC_MD_INT0 (MTK_PIN_NO(149) | 4)
+#define PINMUX_GPIO149__FUNC_TP_GPIO12_AO (MTK_PIN_NO(149) | 5)
+#define PINMUX_GPIO149__FUNC_SCL0 (MTK_PIN_NO(149) | 6)
+#define PINMUX_GPIO149__FUNC_DBG_MON_A28 (MTK_PIN_NO(149) | 7)
+
+#define PINMUX_GPIO150__FUNC_GPIO150 (MTK_PIN_NO(150) | 0)
+#define PINMUX_GPIO150__FUNC_KPCOL2 (MTK_PIN_NO(150) | 1)
+#define PINMUX_GPIO150__FUNC_PWM_VLP (MTK_PIN_NO(150) | 2)
+#define PINMUX_GPIO150__FUNC_CMMCLK5 (MTK_PIN_NO(150) | 3)
+#define PINMUX_GPIO150__FUNC_MD_INT3 (MTK_PIN_NO(150) | 4)
+#define PINMUX_GPIO150__FUNC_TP_GPIO13_AO (MTK_PIN_NO(150) | 5)
+#define PINMUX_GPIO150__FUNC_SDA0 (MTK_PIN_NO(150) | 6)
+
+#define PINMUX_GPIO151__FUNC_GPIO151 (MTK_PIN_NO(151) | 0)
+#define PINMUX_GPIO151__FUNC_SRCLKENAI0 (MTK_PIN_NO(151) | 1)
+#define PINMUX_GPIO151__FUNC_MD_INT4 (MTK_PIN_NO(151) | 4)
+#define PINMUX_GPIO151__FUNC_TP_GPIO14_AO (MTK_PIN_NO(151) | 5)
+#define PINMUX_GPIO151__FUNC_DBG_MON_A29 (MTK_PIN_NO(151) | 7)
+
+#define PINMUX_GPIO152__FUNC_GPIO152 (MTK_PIN_NO(152) | 0)
+#define PINMUX_GPIO152__FUNC_SRCLKENAI1 (MTK_PIN_NO(152) | 1)
+#define PINMUX_GPIO152__FUNC_SPMI_M_TRIG_FLAG (MTK_PIN_NO(152) | 4)
+#define PINMUX_GPIO152__FUNC_TP_GPIO15_AO (MTK_PIN_NO(152) | 5)
+#define PINMUX_GPIO152__FUNC_DBG_MON_A30 (MTK_PIN_NO(152) | 7)
+
+#define PINMUX_GPIO153__FUNC_GPIO153 (MTK_PIN_NO(153) | 0)
+#define PINMUX_GPIO153__FUNC_MD1_SIM2_SCLK (MTK_PIN_NO(153) | 1)
+#define PINMUX_GPIO153__FUNC_DISP_PWM1 (MTK_PIN_NO(153) | 2)
+#define PINMUX_GPIO153__FUNC_SPMI_P_TRIG_FLAG (MTK_PIN_NO(153) | 4)
+#define PINMUX_GPIO153__FUNC_DBG_MON_A0 (MTK_PIN_NO(153) | 7)
+
+#define PINMUX_GPIO154__FUNC_GPIO154 (MTK_PIN_NO(154) | 0)
+#define PINMUX_GPIO154__FUNC_MD1_SIM2_SRST (MTK_PIN_NO(154) | 1)
+#define PINMUX_GPIO154__FUNC_LCM_RST1 (MTK_PIN_NO(154) | 2)
+#define PINMUX_GPIO154__FUNC_GPS_L1_ELNA_EN (MTK_PIN_NO(154) | 3)
+#define PINMUX_GPIO154__FUNC_CMFLASH2 (MTK_PIN_NO(154) | 4)
+#define PINMUX_GPIO154__FUNC_MBISTREADEN_TRIGGER (MTK_PIN_NO(154) | 5)
+#define PINMUX_GPIO154__FUNC_DBG_MON_A1 (MTK_PIN_NO(154) | 7)
+
+#define PINMUX_GPIO155__FUNC_GPIO155 (MTK_PIN_NO(155) | 0)
+#define PINMUX_GPIO155__FUNC_MD1_SIM2_SIO (MTK_PIN_NO(155) | 1)
+#define PINMUX_GPIO155__FUNC_DSI_TE1 (MTK_PIN_NO(155) | 2)
+#define PINMUX_GPIO155__FUNC_GPS_L5_ELNA_EN (MTK_PIN_NO(155) | 3)
+#define PINMUX_GPIO155__FUNC_CMFLASH3 (MTK_PIN_NO(155) | 4)
+#define PINMUX_GPIO155__FUNC_MBISTWRITEEN_TRIGGER (MTK_PIN_NO(155) | 5)
+#define PINMUX_GPIO155__FUNC_DBG_MON_A2 (MTK_PIN_NO(155) | 7)
+
+#define PINMUX_GPIO156__FUNC_GPIO156 (MTK_PIN_NO(156) | 0)
+#define PINMUX_GPIO156__FUNC_SPMI_M_SCL (MTK_PIN_NO(156) | 1)
+
+#define PINMUX_GPIO157__FUNC_GPIO157 (MTK_PIN_NO(157) | 0)
+#define PINMUX_GPIO157__FUNC_SPMI_M_SDA (MTK_PIN_NO(157) | 1)
+
+#define PINMUX_GPIO158__FUNC_GPIO158 (MTK_PIN_NO(158) | 0)
+#define PINMUX_GPIO158__FUNC_SPMI_P_SCL (MTK_PIN_NO(158) | 1)
+
+#define PINMUX_GPIO159__FUNC_GPIO159 (MTK_PIN_NO(159) | 0)
+#define PINMUX_GPIO159__FUNC_SPMI_P_SDA (MTK_PIN_NO(159) | 1)
+
+#define PINMUX_GPIO160__FUNC_GPIO160 (MTK_PIN_NO(160) | 0)
+#define PINMUX_GPIO160__FUNC_SRCLKENA0 (MTK_PIN_NO(160) | 1)
+
+#define PINMUX_GPIO161__FUNC_GPIO161 (MTK_PIN_NO(161) | 0)
+#define PINMUX_GPIO161__FUNC_SCP_VREQ_VAO (MTK_PIN_NO(161) | 1)
+
+#define PINMUX_GPIO162__FUNC_GPIO162 (MTK_PIN_NO(162) | 0)
+#define PINMUX_GPIO162__FUNC_RTC32K_CK (MTK_PIN_NO(162) | 1)
+
+#define PINMUX_GPIO163__FUNC_GPIO163 (MTK_PIN_NO(163) | 0)
+#define PINMUX_GPIO163__FUNC_WATCHDOG (MTK_PIN_NO(163) | 1)
+
+#define PINMUX_GPIO164__FUNC_GPIO164 (MTK_PIN_NO(164) | 0)
+#define PINMUX_GPIO164__FUNC_AUD_CLK_MOSI (MTK_PIN_NO(164) | 1)
+#define PINMUX_GPIO164__FUNC_AUD_CLK_MOSI_A (MTK_PIN_NO(164) | 3)
+
+#define PINMUX_GPIO165__FUNC_GPIO165 (MTK_PIN_NO(165) | 0)
+#define PINMUX_GPIO165__FUNC_AUD_SYNC_MOSI (MTK_PIN_NO(165) | 1)
+
+#define PINMUX_GPIO166__FUNC_GPIO166 (MTK_PIN_NO(166) | 0)
+#define PINMUX_GPIO166__FUNC_AUD_DAT_MOSI0 (MTK_PIN_NO(166) | 1)
+#define PINMUX_GPIO166__FUNC_AUD_DAT_MOSI0_A (MTK_PIN_NO(166) | 3)
+
+#define PINMUX_GPIO167__FUNC_GPIO167 (MTK_PIN_NO(167) | 0)
+#define PINMUX_GPIO167__FUNC_AUD_DAT_MOSI1 (MTK_PIN_NO(167) | 1)
+#define PINMUX_GPIO167__FUNC_AUD_DAT_MOSI1_A (MTK_PIN_NO(167) | 3)
+
+#define PINMUX_GPIO168__FUNC_GPIO168 (MTK_PIN_NO(168) | 0)
+#define PINMUX_GPIO168__FUNC_AUD_NLE_MOSI0 (MTK_PIN_NO(168) | 1)
+#define PINMUX_GPIO168__FUNC_AUD_SYNC_MISO (MTK_PIN_NO(168) | 2)
+
+#define PINMUX_GPIO169__FUNC_GPIO169 (MTK_PIN_NO(169) | 0)
+#define PINMUX_GPIO169__FUNC_AUD_NLE_MOSI1 (MTK_PIN_NO(169) | 1)
+#define PINMUX_GPIO169__FUNC_AUD_CLK_MISO (MTK_PIN_NO(169) | 2)
+#define PINMUX_GPIO169__FUNC_AUD_CLK_MISO_A (MTK_PIN_NO(169) | 3)
+
+#define PINMUX_GPIO170__FUNC_GPIO170 (MTK_PIN_NO(170) | 0)
+#define PINMUX_GPIO170__FUNC_AUD_DAT_MISO0 (MTK_PIN_NO(170) | 1)
+#define PINMUX_GPIO170__FUNC_VOW_DAT_MISO (MTK_PIN_NO(170) | 2)
+#define PINMUX_GPIO170__FUNC_AUD_DAT_MISO0_A (MTK_PIN_NO(170) | 3)
+
+#define PINMUX_GPIO171__FUNC_GPIO171 (MTK_PIN_NO(171) | 0)
+#define PINMUX_GPIO171__FUNC_AUD_DAT_MISO1 (MTK_PIN_NO(171) | 1)
+#define PINMUX_GPIO171__FUNC_VOW_CLK_MISO (MTK_PIN_NO(171) | 2)
+#define PINMUX_GPIO171__FUNC_AUD_DAT_MISO1_A (MTK_PIN_NO(171) | 3)
+
+#define PINMUX_GPIO172__FUNC_GPIO172 (MTK_PIN_NO(172) | 0)
+#define PINMUX_GPIO172__FUNC_CONN_TOP_CLK (MTK_PIN_NO(172) | 1)
+#define PINMUX_GPIO172__FUNC_DBG_MON_A31 (MTK_PIN_NO(172) | 7)
+
+#define PINMUX_GPIO173__FUNC_GPIO173 (MTK_PIN_NO(173) | 0)
+#define PINMUX_GPIO173__FUNC_CONN_TOP_DATA (MTK_PIN_NO(173) | 1)
+
+#define PINMUX_GPIO174__FUNC_GPIO174 (MTK_PIN_NO(174) | 0)
+#define PINMUX_GPIO174__FUNC_CONN_BT_CLK (MTK_PIN_NO(174) | 1)
+
+#define PINMUX_GPIO175__FUNC_GPIO175 (MTK_PIN_NO(175) | 0)
+#define PINMUX_GPIO175__FUNC_CONN_BT_DATA (MTK_PIN_NO(175) | 1)
+
+#define PINMUX_GPIO176__FUNC_GPIO176 (MTK_PIN_NO(176) | 0)
+#define PINMUX_GPIO176__FUNC_CONN_HRST_B (MTK_PIN_NO(176) | 1)
+
+#define PINMUX_GPIO177__FUNC_GPIO177 (MTK_PIN_NO(177) | 0)
+#define PINMUX_GPIO177__FUNC_CONN_WB_PTA (MTK_PIN_NO(177) | 1)
+
+#define PINMUX_GPIO178__FUNC_GPIO178 (MTK_PIN_NO(178) | 0)
+#define PINMUX_GPIO178__FUNC_CONN_WF_CTRL0 (MTK_PIN_NO(178) | 1)
+
+#define PINMUX_GPIO179__FUNC_GPIO179 (MTK_PIN_NO(179) | 0)
+#define PINMUX_GPIO179__FUNC_CONN_WF_CTRL1 (MTK_PIN_NO(179) | 1)
+
+#define PINMUX_GPIO180__FUNC_GPIO180 (MTK_PIN_NO(180) | 0)
+#define PINMUX_GPIO180__FUNC_CONN_WF_CTRL2 (MTK_PIN_NO(180) | 1)
+
+#define PINMUX_GPIO181__FUNC_GPIO181 (MTK_PIN_NO(181) | 0)
+#define PINMUX_GPIO181__FUNC_CONN_WF_CTRL3 (MTK_PIN_NO(181) | 1)
+#define PINMUX_GPIO181__FUNC_CONN_TOP_CLK_2 (MTK_PIN_NO(181) | 2)
+#define PINMUX_GPIO181__FUNC_GPS_L1_ELNA_EN (MTK_PIN_NO(181) | 3)
+
+#define PINMUX_GPIO182__FUNC_GPIO182 (MTK_PIN_NO(182) | 0)
+#define PINMUX_GPIO182__FUNC_CONN_WF_CTRL4 (MTK_PIN_NO(182) | 1)
+#define PINMUX_GPIO182__FUNC_CONN_TOP_DATA_2 (MTK_PIN_NO(182) | 2)
+#define PINMUX_GPIO182__FUNC_GPS_L5_ELNA_EN (MTK_PIN_NO(182) | 3)
+
+#define PINMUX_GPIO183__FUNC_GPIO183 (MTK_PIN_NO(183) | 0)
+#define PINMUX_GPIO183__FUNC_CONN_HRST_B_2 (MTK_PIN_NO(183) | 1)
+
+#define PINMUX_GPIO184__FUNC_GPIO184 (MTK_PIN_NO(184) | 0)
+#define PINMUX_GPIO184__FUNC_MSDC0_DSL (MTK_PIN_NO(184) | 1)
+#define PINMUX_GPIO184__FUNC_ANT_SEL13 (MTK_PIN_NO(184) | 3)
+
+#define PINMUX_GPIO185__FUNC_GPIO185 (MTK_PIN_NO(185) | 0)
+#define PINMUX_GPIO185__FUNC_MSDC0_CLK (MTK_PIN_NO(185) | 1)
+#define PINMUX_GPIO185__FUNC_CONN_TCXOENA_REQ (MTK_PIN_NO(185) | 2)
+#define PINMUX_GPIO185__FUNC_ANT_SEL14 (MTK_PIN_NO(185) | 3)
+
+#define PINMUX_GPIO186__FUNC_GPIO186 (MTK_PIN_NO(186) | 0)
+#define PINMUX_GPIO186__FUNC_MSDC0_CMD (MTK_PIN_NO(186) | 1)
+#define PINMUX_GPIO186__FUNC_GPS_L1_ELNA_EN (MTK_PIN_NO(186) | 2)
+#define PINMUX_GPIO186__FUNC_ANT_SEL15 (MTK_PIN_NO(186) | 3)
+#define PINMUX_GPIO186__FUNC_I2SOUT4_DATA0 (MTK_PIN_NO(186) | 5)
+
+#define PINMUX_GPIO187__FUNC_GPIO187 (MTK_PIN_NO(187) | 0)
+#define PINMUX_GPIO187__FUNC_MSDC0_RSTB (MTK_PIN_NO(187) | 1)
+#define PINMUX_GPIO187__FUNC_GPS_L5_ELNA_EN (MTK_PIN_NO(187) | 2)
+#define PINMUX_GPIO187__FUNC_ANT_SEL16 (MTK_PIN_NO(187) | 3)
+#define PINMUX_GPIO187__FUNC_I2SOUT4_DATA1 (MTK_PIN_NO(187) | 5)
+
+#define PINMUX_GPIO188__FUNC_GPIO188 (MTK_PIN_NO(188) | 0)
+#define PINMUX_GPIO188__FUNC_MSDC0_DAT0 (MTK_PIN_NO(188) | 1)
+#define PINMUX_GPIO188__FUNC_ANT_SEL17 (MTK_PIN_NO(188) | 3)
+#define PINMUX_GPIO188__FUNC_I2SOUT4_DATA2 (MTK_PIN_NO(188) | 5)
+
+#define PINMUX_GPIO189__FUNC_GPIO189 (MTK_PIN_NO(189) | 0)
+#define PINMUX_GPIO189__FUNC_MSDC0_DAT1 (MTK_PIN_NO(189) | 1)
+#define PINMUX_GPIO189__FUNC_ANT_SEL18 (MTK_PIN_NO(189) | 3)
+#define PINMUX_GPIO189__FUNC_I2SOUT4_DATA3 (MTK_PIN_NO(189) | 5)
+
+#define PINMUX_GPIO190__FUNC_GPIO190 (MTK_PIN_NO(190) | 0)
+#define PINMUX_GPIO190__FUNC_MSDC0_DAT2 (MTK_PIN_NO(190) | 1)
+#define PINMUX_GPIO190__FUNC_DMIC1_CLK (MTK_PIN_NO(190) | 2)
+#define PINMUX_GPIO190__FUNC_ANT_SEL19 (MTK_PIN_NO(190) | 3)
+#define PINMUX_GPIO190__FUNC_I2SIN4_BCK (MTK_PIN_NO(190) | 5)
+
+#define PINMUX_GPIO191__FUNC_GPIO191 (MTK_PIN_NO(191) | 0)
+#define PINMUX_GPIO191__FUNC_MSDC0_DAT3 (MTK_PIN_NO(191) | 1)
+#define PINMUX_GPIO191__FUNC_DMIC1_DAT (MTK_PIN_NO(191) | 2)
+#define PINMUX_GPIO191__FUNC_ANT_SEL20 (MTK_PIN_NO(191) | 3)
+#define PINMUX_GPIO191__FUNC_I2SIN4_DATA0 (MTK_PIN_NO(191) | 5)
+
+#define PINMUX_GPIO192__FUNC_GPIO192 (MTK_PIN_NO(192) | 0)
+#define PINMUX_GPIO192__FUNC_MSDC0_DAT4 (MTK_PIN_NO(192) | 1)
+#define PINMUX_GPIO192__FUNC_IDDIG (MTK_PIN_NO(192) | 2)
+#define PINMUX_GPIO192__FUNC_ANT_SEL21 (MTK_PIN_NO(192) | 3)
+#define PINMUX_GPIO192__FUNC_UFS_MPHY_SCL (MTK_PIN_NO(192) | 4)
+#define PINMUX_GPIO192__FUNC_I2SIN4_DATA1 (MTK_PIN_NO(192) | 5)
+
+#define PINMUX_GPIO193__FUNC_GPIO193 (MTK_PIN_NO(193) | 0)
+#define PINMUX_GPIO193__FUNC_MSDC0_DAT5 (MTK_PIN_NO(193) | 1)
+#define PINMUX_GPIO193__FUNC_USB_DRVVBUS (MTK_PIN_NO(193) | 2)
+#define PINMUX_GPIO193__FUNC_UFS_MPHY_SDA (MTK_PIN_NO(193) | 4)
+#define PINMUX_GPIO193__FUNC_I2SIN4_DATA2 (MTK_PIN_NO(193) | 5)
+
+#define PINMUX_GPIO194__FUNC_GPIO194 (MTK_PIN_NO(194) | 0)
+#define PINMUX_GPIO194__FUNC_MSDC0_DAT6 (MTK_PIN_NO(194) | 1)
+#define PINMUX_GPIO194__FUNC_VBUSVALID (MTK_PIN_NO(194) | 2)
+#define PINMUX_GPIO194__FUNC_I2SIN4_DATA3 (MTK_PIN_NO(194) | 5)
+
+#define PINMUX_GPIO195__FUNC_GPIO195 (MTK_PIN_NO(195) | 0)
+#define PINMUX_GPIO195__FUNC_MSDC0_DAT7 (MTK_PIN_NO(195) | 1)
+#define PINMUX_GPIO195__FUNC_I2SIN4_LRCK (MTK_PIN_NO(195) | 5)
+
+#endif /* __MT6878_PINFUNC_H */

-- 
2.51.0


^ permalink raw reply	[flat|nested] 12+ messages in thread

* Re: [PATCH 1/4] dt-bindings: pinctrl: mediatek: Document MT6878 pin controller bindings
  2025-09-08 19:17 ` [PATCH 1/4] dt-bindings: pinctrl: mediatek: Document MT6878 pin controller bindings Igor Belwon
@ 2025-09-09  7:37   ` Krzysztof Kozlowski
  2025-09-09 12:14     ` Igor Belwon
  0 siblings, 1 reply; 12+ messages in thread
From: Krzysztof Kozlowski @ 2025-09-09  7:37 UTC (permalink / raw)
  To: Igor Belwon
  Cc: Linus Walleij, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
	Matthias Brugger, AngeloGioacchino Del Regno, Sean Wang,
	linux-gpio, devicetree, linux-kernel, linux-arm-kernel,
	linux-mediatek

On Mon, Sep 08, 2025 at 09:17:55PM +0200, Igor Belwon wrote:
> Add device-tree bindings for the pin controller and the EINT controller
> found in the MediaTek MT6878 SoC.
> 
> Signed-off-by: Igor Belwon <igor.belwon@mentallysanemainliners.org>
> ---
>  .../bindings/pinctrl/mediatek,mt6878-pinctrl.yaml  |  209 ++++
>  include/dt-bindings/pinctrl/mt6878-pinfunc.h       | 1201 ++++++++++++++++++++
>  2 files changed, 1410 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/pinctrl/mediatek,mt6878-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/mediatek,mt6878-pinctrl.yaml
> new file mode 100644
> index 0000000000000000000000000000000000000000..ecd24ab23a0c41810828ddb8827ab39c4cd3d2fc
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/pinctrl/mediatek,mt6878-pinctrl.yaml
> @@ -0,0 +1,209 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/pinctrl/mediatek,mt6878-pinctrl.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: MediaTek MT6878 Pin Controller
> +
> +maintainers:
> +  - Igor Belwon <igor.belwon@mentallysanemainliners.org>
> +
> +description:
> +  The MediaTek MT6878 Pin controller is used to control SoC pins.
> +
> +properties:
> +  compatible:
> +    const: mediatek,mt6878-pinctrl
> +
> +  reg:
> +    items:
> +      - description: pin controller base
> +      - description: bl group IO
> +      - description: bm group IO
> +      - description: br group IO
> +      - description: bl1 group IO
> +      - description: br1 group IO
> +      - description: lm group IO
> +      - description: lt group IO
> +      - description: rm group IO
> +      - description: rt group IO
> +      - description: EINT controller E block
> +      - description: EINT controller S block
> +      - description: EINT controller W block
> +      - description: EINT controller C block
> +
> +  reg-names:
> +    items:
> +      - const: base
> +      - const: bl
> +      - const: bm
> +      - const: br
> +      - const: bl1
> +      - const: br1
> +      - const: lm
> +      - const: lt
> +      - const: rm
> +      - const: rt
> +      - const: eint-e
> +      - const: eint-s
> +      - const: eint-w
> +      - const: eint-c
> +
> +  gpio-controller: true
> +
> +  '#gpio-cells':
> +    description:
> +      Number of cells in GPIO specifier. Since the generic GPIO binding is used,
> +      the amount of cells must be specified as 2. See the below mentioned gpio
> +      binding representation for description of particular cells.
> +    const: 2
> +
> +  gpio-ranges:
> +    maxItems: 1
> +
> +  gpio-line-names: true

How many GPIOs do you have? No limit?

> +
> +  interrupts:
> +    description: The interrupt outputs to sysirq
> +    maxItems: 1
> +
> +  interrupt-controller: true
> +
> +  '#interrupt-cells':
> +    const: 2
> +
> +# PIN CONFIGURATION NODES
> +patternProperties:
> +  '-pins$':
> +    type: object
> +    additionalProperties: false
> +
> +    patternProperties:
> +      '^pins':
> +        type: object
> +        allOf:
> +          - $ref: /schemas/pinctrl/pincfg-node.yaml
> +          - $ref: /schemas/pinctrl/pinmux-node.yaml
> +        description:
> +          A pinctrl node should contain at least one subnodes representing the
> +          pinctrl groups available on the machine. Each subnode will list the
> +          pins it needs, and how they should be configured, with regard to muxer
> +          configuration, pullups, drive strength, input enable/disable and input
> +          schmitt.
> +
> +        properties:
> +          pinmux:
> +            description:
> +              Integer array, represents gpio pin number and mux setting.
> +              Supported pin number and mux are defined as macros in
> +              arch/arm64/boot/dts/mediatek/mt8196-pinfunc.h for this SoC.
> +
> +          drive-strength:
> +            enum: [2, 4, 6, 8, 10, 12, 14, 16]
> +
> +          drive-strength-microamp:
> +            enum: [125, 250, 500, 1000]
> +
> +          bias-pull-down:
> +            oneOf:
> +              - type: boolean
> +              - enum: [75000, 5000]
> +                description: Pull down RSEL type resistance values (in ohms)
> +            description:
> +              For normal pull down type there is no need to specify a resistance
> +              value, hence this can be specified as a boolean property.
> +              For RSEL pull down type a resistance value (in ohms) can be added.
> +
> +          bias-pull-up:
> +            oneOf:
> +              - type: boolean
> +              - enum: [10000, 5000, 4000, 3000]
> +                description: Pull up RSEL type resistance values (in ohms)
> +            description:
> +              For normal pull up type there is no need to specify a resistance
> +              value, hence this can be specified as a boolean property.
> +              For RSEL pull up type a resistance value (in ohms) can be added.
> +
> +          bias-disable: true
> +
> +          output-high: true
> +
> +          output-low: true
> +
> +          input-enable: true
> +
> +          input-disable: true
> +
> +          input-schmitt-enable: true
> +
> +          input-schmitt-disable: true
> +
> +        required:
> +          - pinmux
> +
> +        additionalProperties: false
> +
> +required:
> +  - compatible
> +  - reg
> +  - interrupts
> +  - interrupt-controller
> +  - '#interrupt-cells'
> +  - gpio-controller
> +  - '#gpio-cells'
> +  - gpio-ranges
> +
> +additionalProperties: false
> +
> +examples:
> +  - |
> +    #include <dt-bindings/interrupt-controller/arm-gic.h>
> +    #include <dt-bindings/pinctrl/mt65xx.h>

Why including mt65xx?

> +    #define PINMUX_GPIO0__FUNC_GPIO0 (MTK_PIN_NO(0) | 0)

I don't understand why do you need it? Didn't you have header for that?
Or you prepared for header removal (see my further comment), but then it
is just confusing.

> +    #define PINMUX_GPIO99__FUNC_SCL0 (MTK_PIN_NO(99) | 1)
> +    #define PINMUX_GPIO100__FUNC_SDA0 (MTK_PIN_NO(100) | 1)
> +
> +    pio: pinctrl@10005000 {
> +        compatible = "mediatek,mt6878-pinctrl";
> +        reg = <0x10005000 0x1000>,
> +              <0x11d10000 0x1000>,
> +              <0x11d30000 0x1000>,
> +              <0x11d40000 0x1000>,
> +              <0x11d50000 0x1000>,
> +              <0x11d60000 0x1000>,
> +              <0x11e20000 0x1000>,
> +              <0x11e30000 0x1000>,
> +              <0x11eb0000 0x1000>,
> +              <0x11ec0000 0x1000>,
> +              <0x11ce0000 0x1000>,
> +              <0x11de0000 0x1000>,
> +              <0x11e60000 0x1000>,
> +              <0x1c01e000 0x1000>;
> +        reg-names = "base", "bl", "bm", "br", "bl1", "br1",
> +                    "lm", "lt", "rm", "rt", "eint-e", "eint-s",
> +                    "eint-w", "eint-c";
> +        gpio-controller;
> +        #gpio-cells = <2>;
> +        gpio-ranges = <&pio 0 0 220>;
> +        interrupt-controller;
> +        interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH 0>;
> +        #interrupt-cells = <2>;
> +
> +        gpio-pins {
> +            pins {
> +                pinmux = <PINMUX_GPIO0__FUNC_GPIO0>;
> +                bias-pull-up = <4000>;
> +                drive-strength = <6>;
> +            };
> +        };
> +
> +        i2c0-pins {
> +            pins-bus {
> +                pinmux = <PINMUX_GPIO99__FUNC_SCL0>,
> +                         <PINMUX_GPIO100__FUNC_SDA0>;
> +                bias-pull-down = <75000>;
> +                drive-strength-microamp = <1000>;
> +            };
> +        };
> +    };
> diff --git a/include/dt-bindings/pinctrl/mt6878-pinfunc.h b/include/dt-bindings/pinctrl/mt6878-pinfunc.h
> new file mode 100644
> index 0000000000000000000000000000000000000000..4e8e475a74549b513ac7075ac2ef0fe6f7f1d097
> --- /dev/null
> +++ b/include/dt-bindings/pinctrl/mt6878-pinfunc.h

This is now in DTS.

> @@ -0,0 +1,1201 @@
> +/* SPDX-License-Identifier: GPL-2.0 */

Otherwise wrong license and wrong filename (vendor prefix, filename
matching binding).

Best regards,
Krzysztof


^ permalink raw reply	[flat|nested] 12+ messages in thread

* Re: [PATCH 1/4] dt-bindings: pinctrl: mediatek: Document MT6878 pin controller bindings
  2025-09-09  7:37   ` Krzysztof Kozlowski
@ 2025-09-09 12:14     ` Igor Belwon
  0 siblings, 0 replies; 12+ messages in thread
From: Igor Belwon @ 2025-09-09 12:14 UTC (permalink / raw)
  To: Krzysztof Kozlowski, Igor Belwon
  Cc: Linus Walleij, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
	Matthias Brugger, AngeloGioacchino Del Regno, Sean Wang,
	linux-gpio, devicetree, linux-kernel, linux-arm-kernel,
	linux-mediatek

On Tue Sep 9, 2025 at 9:37 AM CEST, Krzysztof Kozlowski wrote:
> On Mon, Sep 08, 2025 at 09:17:55PM +0200, Igor Belwon wrote:
>> Add device-tree bindings for the pin controller and the EINT controller
>> found in the MediaTek MT6878 SoC.
>> 
>> Signed-off-by: Igor Belwon <igor.belwon@mentallysanemainliners.org>
>> ---
>>  .../bindings/pinctrl/mediatek,mt6878-pinctrl.yaml  |  209 ++++
>>  include/dt-bindings/pinctrl/mt6878-pinfunc.h       | 1201 ++++++++++++++++++++
>>  2 files changed, 1410 insertions(+)
>> 
>> diff --git a/Documentation/devicetree/bindings/pinctrl/mediatek,mt6878-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/mediatek,mt6878-pinctrl.yaml
>> new file mode 100644
>> index 0000000000000000000000000000000000000000..ecd24ab23a0c41810828ddb8827ab39c4cd3d2fc
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/pinctrl/mediatek,mt6878-pinctrl.yaml
>> @@ -0,0 +1,209 @@
>> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
>> +%YAML 1.2
>> +---
>> +$id: http://devicetree.org/schemas/pinctrl/mediatek,mt6878-pinctrl.yaml#
>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
>> +
>> +title: MediaTek MT6878 Pin Controller
>> +
>> +maintainers:
>> +  - Igor Belwon <igor.belwon@mentallysanemainliners.org>
>> +
>> +description:
>> +  The MediaTek MT6878 Pin controller is used to control SoC pins.
>> +
>> +properties:
>> +  compatible:
>> +    const: mediatek,mt6878-pinctrl
>> +
>> +  reg:
>> +    items:
>> +      - description: pin controller base
>> +      - description: bl group IO
>> +      - description: bm group IO
>> +      - description: br group IO
>> +      - description: bl1 group IO
>> +      - description: br1 group IO
>> +      - description: lm group IO
>> +      - description: lt group IO
>> +      - description: rm group IO
>> +      - description: rt group IO
>> +      - description: EINT controller E block
>> +      - description: EINT controller S block
>> +      - description: EINT controller W block
>> +      - description: EINT controller C block
>> +
>> +  reg-names:
>> +    items:
>> +      - const: base
>> +      - const: bl
>> +      - const: bm
>> +      - const: br
>> +      - const: bl1
>> +      - const: br1
>> +      - const: lm
>> +      - const: lt
>> +      - const: rm
>> +      - const: rt
>> +      - const: eint-e
>> +      - const: eint-s
>> +      - const: eint-w
>> +      - const: eint-c
>> +
>> +  gpio-controller: true
>> +
>> +  '#gpio-cells':
>> +    description:
>> +      Number of cells in GPIO specifier. Since the generic GPIO binding is used,
>> +      the amount of cells must be specified as 2. See the below mentioned gpio
>> +      binding representation for description of particular cells.
>> +    const: 2
>> +
>> +  gpio-ranges:
>> +    maxItems: 1
>> +
>> +  gpio-line-names: true
>
> How many GPIOs do you have? No limit?
>

How shall I limit the GPIOs?
The maximum amount that this SoC supports is 216, looking into
dt-bindings for pinctrl, I haven't seen a SoC that limits them in
bindings. Maybe I missed it though...

>> +
>> +  interrupts:
>> +    description: The interrupt outputs to sysirq
>> +    maxItems: 1
>> +
>> +  interrupt-controller: true
>> +
>> +  '#interrupt-cells':
>> +    const: 2
>> +
>> +# PIN CONFIGURATION NODES
>> +patternProperties:
>> +  '-pins$':
>> +    type: object
>> +    additionalProperties: false
>> +
>> +    patternProperties:
>> +      '^pins':
>> +        type: object
>> +        allOf:
>> +          - $ref: /schemas/pinctrl/pincfg-node.yaml
>> +          - $ref: /schemas/pinctrl/pinmux-node.yaml
>> +        description:
>> +          A pinctrl node should contain at least one subnodes representing the
>> +          pinctrl groups available on the machine. Each subnode will list the
>> +          pins it needs, and how they should be configured, with regard to muxer
>> +          configuration, pullups, drive strength, input enable/disable and input
>> +          schmitt.
>> +
>> +        properties:
>> +          pinmux:
>> +            description:
>> +              Integer array, represents gpio pin number and mux setting.
>> +              Supported pin number and mux are defined as macros in
>> +              arch/arm64/boot/dts/mediatek/mt8196-pinfunc.h for this SoC.
>> +
>> +          drive-strength:
>> +            enum: [2, 4, 6, 8, 10, 12, 14, 16]
>> +
>> +          drive-strength-microamp:
>> +            enum: [125, 250, 500, 1000]
>> +
>> +          bias-pull-down:
>> +            oneOf:
>> +              - type: boolean
>> +              - enum: [75000, 5000]
>> +                description: Pull down RSEL type resistance values (in ohms)
>> +            description:
>> +              For normal pull down type there is no need to specify a resistance
>> +              value, hence this can be specified as a boolean property.
>> +              For RSEL pull down type a resistance value (in ohms) can be added.
>> +
>> +          bias-pull-up:
>> +            oneOf:
>> +              - type: boolean
>> +              - enum: [10000, 5000, 4000, 3000]
>> +                description: Pull up RSEL type resistance values (in ohms)
>> +            description:
>> +              For normal pull up type there is no need to specify a resistance
>> +              value, hence this can be specified as a boolean property.
>> +              For RSEL pull up type a resistance value (in ohms) can be added.
>> +
>> +          bias-disable: true
>> +
>> +          output-high: true
>> +
>> +          output-low: true
>> +
>> +          input-enable: true
>> +
>> +          input-disable: true
>> +
>> +          input-schmitt-enable: true
>> +
>> +          input-schmitt-disable: true
>> +
>> +        required:
>> +          - pinmux
>> +
>> +        additionalProperties: false
>> +
>> +required:
>> +  - compatible
>> +  - reg
>> +  - interrupts
>> +  - interrupt-controller
>> +  - '#interrupt-cells'
>> +  - gpio-controller
>> +  - '#gpio-cells'
>> +  - gpio-ranges
>> +
>> +additionalProperties: false
>> +
>> +examples:
>> +  - |
>> +    #include <dt-bindings/interrupt-controller/arm-gic.h>
>> +    #include <dt-bindings/pinctrl/mt65xx.h>
>
> Why including mt65xx?
>
>> +    #define PINMUX_GPIO0__FUNC_GPIO0 (MTK_PIN_NO(0) | 0)
>
> I don't understand why do you need it? Didn't you have header for that?
> Or you prepared for header removal (see my further comment), but then it
> is just confusing.
>

Will use the new header in V2.

>> +    #define PINMUX_GPIO99__FUNC_SCL0 (MTK_PIN_NO(99) | 1)
>> +    #define PINMUX_GPIO100__FUNC_SDA0 (MTK_PIN_NO(100) | 1)
>> +
>> +    pio: pinctrl@10005000 {
>> +        compatible = "mediatek,mt6878-pinctrl";
>> +        reg = <0x10005000 0x1000>,
>> +              <0x11d10000 0x1000>,
>> +              <0x11d30000 0x1000>,
>> +              <0x11d40000 0x1000>,
>> +              <0x11d50000 0x1000>,
>> +              <0x11d60000 0x1000>,
>> +              <0x11e20000 0x1000>,
>> +              <0x11e30000 0x1000>,
>> +              <0x11eb0000 0x1000>,
>> +              <0x11ec0000 0x1000>,
>> +              <0x11ce0000 0x1000>,
>> +              <0x11de0000 0x1000>,
>> +              <0x11e60000 0x1000>,
>> +              <0x1c01e000 0x1000>;
>> +        reg-names = "base", "bl", "bm", "br", "bl1", "br1",
>> +                    "lm", "lt", "rm", "rt", "eint-e", "eint-s",
>> +                    "eint-w", "eint-c";
>> +        gpio-controller;
>> +        #gpio-cells = <2>;
>> +        gpio-ranges = <&pio 0 0 220>;
>> +        interrupt-controller;
>> +        interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH 0>;
>> +        #interrupt-cells = <2>;
>> +
>> +        gpio-pins {
>> +            pins {
>> +                pinmux = <PINMUX_GPIO0__FUNC_GPIO0>;
>> +                bias-pull-up = <4000>;
>> +                drive-strength = <6>;
>> +            };
>> +        };
>> +
>> +        i2c0-pins {
>> +            pins-bus {
>> +                pinmux = <PINMUX_GPIO99__FUNC_SCL0>,
>> +                         <PINMUX_GPIO100__FUNC_SDA0>;
>> +                bias-pull-down = <75000>;
>> +                drive-strength-microamp = <1000>;
>> +            };
>> +        };
>> +    };
>> diff --git a/include/dt-bindings/pinctrl/mt6878-pinfunc.h b/include/dt-bindings/pinctrl/mt6878-pinfunc.h
>> new file mode 100644
>> index 0000000000000000000000000000000000000000..4e8e475a74549b513ac7075ac2ef0fe6f7f1d097
>> --- /dev/null
>> +++ b/include/dt-bindings/pinctrl/mt6878-pinfunc.h
>
> This is now in DTS.

Will move over in V2.

>
>> @@ -0,0 +1,1201 @@
>> +/* SPDX-License-Identifier: GPL-2.0 */
>
> Otherwise wrong license and wrong filename (vendor prefix, filename
> matching binding).
>
> Best regards,
> Krzysztof

Thanks,
Igor

^ permalink raw reply	[flat|nested] 12+ messages in thread

* [PATCH 2/4] pinctrl: mediatek: Add support for eh bit
  2025-09-08 19:17 [PATCH 0/4] Add support for mt6878 pinctrl Igor Belwon
  2025-09-08 19:17 ` [PATCH 1/4] dt-bindings: pinctrl: mediatek: Document MT6878 pin controller bindings Igor Belwon
@ 2025-09-08 19:17 ` Igor Belwon
  2025-09-09  7:57   ` AngeloGioacchino Del Regno
  2025-09-08 19:17 ` [PATCH 3/4] pinctrl: mediatek: Add debounce times for MT6878 Igor Belwon
  2025-09-08 19:17 ` [PATCH 4/4] pinctrl: mediatek: Add support for MT6878 pinctrl Igor Belwon
  3 siblings, 1 reply; 12+ messages in thread
From: Igor Belwon @ 2025-09-08 19:17 UTC (permalink / raw)
  To: Linus Walleij, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
	Matthias Brugger, AngeloGioacchino Del Regno, Sean Wang
  Cc: linux-gpio, devicetree, linux-kernel, linux-arm-kernel,
	linux-mediatek, Igor Belwon

The eh bit is used for setting drive mode for i2c pins on recent SoCs.
Add support for it.

Signed-off-by: Igor Belwon <igor.belwon@mentallysanemainliners.org>
---
 drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.c | 60 ++++++++++++++++++++++++
 drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.h | 24 ++++++++++
 drivers/pinctrl/mediatek/pinctrl-paris.c         | 30 +++++++++---
 3 files changed, 108 insertions(+), 6 deletions(-)

diff --git a/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.c b/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.c
index 4918d38abfc29de1f27ee75bc6a51c32b3ca1ac5..51fbdbdf61c901bb7ee43405d36f2c1602b3616f 100644
--- a/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.c
+++ b/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.c
@@ -249,6 +249,58 @@ static int mtk_xt_find_eint_num(struct mtk_pinctrl *hw, unsigned long eint_n)
 	return EINT_NA;
 }
 
+/*
+ * The eh register determines the selection of the driving control
+ * for i2c pins.
+ * eh = 0: Non-i2c mode.
+ * eh = 1: i2c mode.
+ */
+int mtk_eh_ctrl(struct mtk_pinctrl *hw, const struct mtk_pin_desc *desc,
+		u16 mode)
+{
+	const struct mtk_eh_pin_pinmux *p = hw->soc->eh_pin_pinmux;
+	u32 eh_info_num = hw->soc->neh_pins;
+	u32 val = 0, on = 0, found = 0, i = 0;
+	int err;
+
+	while (i < eh_info_num) {
+		if (desc->number == p[i].pin) {
+			found = 1;
+			if (mode == p[i].pinmux) {
+				on = 1;
+				break;
+			}
+		}
+		/*
+		 * It is possible that one pin may have more than one pinmux
+		 *   that shall enable eh.
+		 * Besides, we assume that hw->soc->eh_pin_pinmux is sorted
+		 *   according to field 'pin'.
+		 * So when desc->number < p->pin, it mean no match will be
+		 *   found and we can leave.
+		 */
+		if (desc->number < p[i].pin)
+			break;
+
+		i++;
+	}
+
+	if (!found)
+		return 0;
+
+	err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_DRV_EH, &val);
+	if (err)
+		return err;
+
+	if (on)
+		val |= on;
+	else
+		val &= MTK_EH_ENABLE_MASK;
+
+	return mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DRV_EH, val);
+}
+EXPORT_SYMBOL_GPL(mtk_eh_ctrl);
+
 /*
  * Virtual GPIO only used inside SOC and not being exported to outside SOC.
  * Some modules use virtual GPIO as eint (e.g. pmif or usb).
@@ -1231,6 +1283,10 @@ int mtk_pinconf_adv_drive_set(struct mtk_pinctrl *hw,
 	int e0 = !!(arg & 2);
 	int e1 = !!(arg & 4);
 
+	err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DRV_EH, arg);
+	if (!err)
+		return 0;
+
 	err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DRV_EN, en);
 	if (err)
 		return err;
@@ -1256,6 +1312,10 @@ int mtk_pinconf_adv_drive_get(struct mtk_pinctrl *hw,
 	u32 en, e0, e1;
 	int err;
 
+	err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_DRV_EH, val);
+	if (!err)
+		return 0;
+
 	err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_DRV_EN, &en);
 	if (err)
 		return err;
diff --git a/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.h b/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.h
index fa7c0ed49346486ba32ec615aa2b3483217f5077..a2ff8ae5ba43e5be87c8b478c07d9d4640c2e8ec 100644
--- a/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.h
+++ b/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.h
@@ -35,6 +35,8 @@
 				 MTK_PULL_PUPD_R1R0_TYPE |\
 				 MTK_PULL_RSEL_TYPE)
 
+#define MTK_EH_ENABLE_MASK	0xfffffffe
+
 #define EINT_NA	U16_MAX
 #define NO_EINT_SUPPORT	EINT_NA
 
@@ -67,6 +69,11 @@
 		.down_rsel = _down_rsel,				\
 	}
 
+#define PIN_MUX_EH(_pin, _pinmux) {						\
+		.pin = _pin,						\
+		.pinmux = _pinmux,					\
+	}
+
 /* List these attributes which could be modified for the pin */
 enum {
 	PINCTRL_PIN_REG_MODE,
@@ -88,6 +95,7 @@ enum {
 	PINCTRL_PIN_REG_IES,
 	PINCTRL_PIN_REG_PULLEN,
 	PINCTRL_PIN_REG_PULLSEL,
+	PINCTRL_PIN_REG_DRV_EH,
 	PINCTRL_PIN_REG_DRV_EN,
 	PINCTRL_PIN_REG_DRV_E0,
 	PINCTRL_PIN_REG_DRV_E1,
@@ -204,6 +212,17 @@ struct mtk_eint_desc {
 	u16 eint_n;
 };
 
+/**
+ * struct mtk_eh_pin_pinmux - entry recording (pin, pinmux) whose
+ *			      eh can be enabled
+ * @pin:                pin number
+ * @pinmux:             pinmux number
+ */
+struct mtk_eh_pin_pinmux {
+	u16 pin;
+	u16 pinmux;
+};
+
 /**
  * struct mtk_pin_desc - the structure that providing information
  *			       for each pin of chips
@@ -252,6 +271,8 @@ struct mtk_pin_soc {
 	const unsigned int		*pull_type;
 	const struct mtk_pin_rsel	*pin_rsel;
 	unsigned int			npin_rsel;
+	const struct mtk_eh_pin_pinmux  *eh_pin_pinmux;
+	unsigned int			neh_pins;
 
 	/* Specific pinconfig operations */
 	int (*bias_disable_set)(struct mtk_pinctrl *hw,
@@ -311,6 +332,9 @@ int mtk_hw_set_value(struct mtk_pinctrl *hw, const struct mtk_pin_desc *desc,
 int mtk_hw_get_value(struct mtk_pinctrl *hw, const struct mtk_pin_desc *desc,
 		     int field, int *value);
 
+int mtk_eh_ctrl(struct mtk_pinctrl *hw, const struct mtk_pin_desc *desc,
+		u16 mode);
+
 int mtk_build_eint(struct mtk_pinctrl *hw, struct platform_device *pdev);
 
 int mtk_pinconf_bias_disable_set(struct mtk_pinctrl *hw,
diff --git a/drivers/pinctrl/mediatek/pinctrl-paris.c b/drivers/pinctrl/mediatek/pinctrl-paris.c
index 3e714554789d0e7e31ecce92388f53b906bdf122..f87447d6f879a3f7b57db44ed97cc91f8e93b425 100644
--- a/drivers/pinctrl/mediatek/pinctrl-paris.c
+++ b/drivers/pinctrl/mediatek/pinctrl-paris.c
@@ -104,13 +104,21 @@ static int mtk_pinmux_gpio_request_enable(struct pinctrl_dev *pctldev,
 					  struct pinctrl_gpio_range *range,
 					  unsigned int pin)
 {
+	int err;
 	struct mtk_pinctrl *hw = pinctrl_dev_get_drvdata(pctldev);
 	const struct mtk_pin_desc *desc;
 
 	desc = (const struct mtk_pin_desc *)&hw->soc->pins[pin];
 
-	return mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_MODE,
-				hw->soc->gpio_m);
+	err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_MODE,
+			       hw->soc->gpio_m);
+	if (err)
+		return err;
+
+	if (hw->soc->eh_pin_pinmux)
+		err = mtk_eh_ctrl(hw, desc, hw->soc->gpio_m);
+
+	return err;
 }
 
 static int mtk_pinmux_gpio_set_direction(struct pinctrl_dev *pctldev,
@@ -749,10 +757,10 @@ static int mtk_pmx_set_mux(struct pinctrl_dev *pctldev,
 	struct mtk_pinctrl_group *grp = hw->groups + group;
 	const struct mtk_func_desc *desc_func;
 	const struct mtk_pin_desc *desc;
-	bool ret;
+	int err;
 
-	ret = mtk_pctrl_is_function_valid(hw, grp->pin, function);
-	if (!ret) {
+	err = mtk_pctrl_is_function_valid(hw, grp->pin, function);
+	if (!err) {
 		dev_err(hw->dev, "invalid function %d on group %d .\n",
 			function, group);
 		return -EINVAL;
@@ -763,7 +771,17 @@ static int mtk_pmx_set_mux(struct pinctrl_dev *pctldev,
 		return -EINVAL;
 
 	desc = (const struct mtk_pin_desc *)&hw->soc->pins[grp->pin];
-	return mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_MODE, desc_func->muxval);
+
+	err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_MODE,
+			       desc_func->muxval);
+
+	if (!err)
+		return err;
+
+	if (hw->soc->eh_pin_pinmux)
+		err = mtk_eh_ctrl(hw, desc, desc_func->muxval);
+
+	return err;
 }
 
 static const struct pinmux_ops mtk_pmxops = {

-- 
2.51.0


^ permalink raw reply	[flat|nested] 12+ messages in thread

* Re: [PATCH 2/4] pinctrl: mediatek: Add support for eh bit
  2025-09-08 19:17 ` [PATCH 2/4] pinctrl: mediatek: Add support for eh bit Igor Belwon
@ 2025-09-09  7:57   ` AngeloGioacchino Del Regno
  2025-09-09 11:53     ` Igor Belwon
  0 siblings, 1 reply; 12+ messages in thread
From: AngeloGioacchino Del Regno @ 2025-09-09  7:57 UTC (permalink / raw)
  To: Igor Belwon, Linus Walleij, Rob Herring, Krzysztof Kozlowski,
	Conor Dooley, Matthias Brugger, Sean Wang
  Cc: linux-gpio, devicetree, linux-kernel, linux-arm-kernel, linux-mediatek

Il 08/09/25 21:17, Igor Belwon ha scritto:
> The eh bit is used for setting drive mode for i2c pins on recent SoCs.
> Add support for it.
> 
> Signed-off-by: Igor Belwon <igor.belwon@mentallysanemainliners.org>

Noupe, this commit is not needed at all.

I get that this may be tricky to understand... but summarizing, what the
downstream calls "EH" in upstream is "DRV_ADV" :-)

Check the comments on patch [4/4] about how to change EH to DRV_ADV.

Cheers,
Angelo

^ permalink raw reply	[flat|nested] 12+ messages in thread

* Re: [PATCH 2/4] pinctrl: mediatek: Add support for eh bit
  2025-09-09  7:57   ` AngeloGioacchino Del Regno
@ 2025-09-09 11:53     ` Igor Belwon
  0 siblings, 0 replies; 12+ messages in thread
From: Igor Belwon @ 2025-09-09 11:53 UTC (permalink / raw)
  To: AngeloGioacchino Del Regno
  Cc: linux-gpio, devicetree, linux-kernel, linux-arm-kernel, linux-mediatek

On Tue Sep 9, 2025 at 9:57 AM CEST, AngeloGioacchino Del Regno wrote:
> Il 08/09/25 21:17, Igor Belwon ha scritto:
>> The eh bit is used for setting drive mode for i2c pins on recent SoCs.
>> Add support for it.
>> 
>> Signed-off-by: Igor Belwon <igor.belwon@mentallysanemainliners.org>
>
> Noupe, this commit is not needed at all.
>
> I get that this may be tricky to understand... but summarizing, what the
> downstream calls "EH" in upstream is "DRV_ADV" :-)
>
> Check the comments on patch [4/4] about how to change EH to DRV_ADV.
>
> Cheers,
> Angelo

Whoops, sorry, I don't know how I missed that.
Will change as in your comments and drop this commit.

Thanks,
Igor

^ permalink raw reply	[flat|nested] 12+ messages in thread

* [PATCH 3/4] pinctrl: mediatek: Add debounce times for MT6878
  2025-09-08 19:17 [PATCH 0/4] Add support for mt6878 pinctrl Igor Belwon
  2025-09-08 19:17 ` [PATCH 1/4] dt-bindings: pinctrl: mediatek: Document MT6878 pin controller bindings Igor Belwon
  2025-09-08 19:17 ` [PATCH 2/4] pinctrl: mediatek: Add support for eh bit Igor Belwon
@ 2025-09-08 19:17 ` Igor Belwon
  2025-09-09  8:00   ` AngeloGioacchino Del Regno
  2025-09-08 19:17 ` [PATCH 4/4] pinctrl: mediatek: Add support for MT6878 pinctrl Igor Belwon
  3 siblings, 1 reply; 12+ messages in thread
From: Igor Belwon @ 2025-09-08 19:17 UTC (permalink / raw)
  To: Linus Walleij, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
	Matthias Brugger, AngeloGioacchino Del Regno, Sean Wang
  Cc: linux-gpio, devicetree, linux-kernel, linux-arm-kernel,
	linux-mediatek, Igor Belwon

MT6878 uses different debounce times than other SoCs. Add them to the
EINT driver.
---
 drivers/pinctrl/mediatek/mtk-eint.c | 5 +++++
 drivers/pinctrl/mediatek/mtk-eint.h | 1 +
 2 files changed, 6 insertions(+)

diff --git a/drivers/pinctrl/mediatek/mtk-eint.c b/drivers/pinctrl/mediatek/mtk-eint.c
index 9f175c73613f84b47c0160947f32da7aca7d5a18..c8c5097c11c4d14eb41bdd7f9cb93b4a5756d2b2 100644
--- a/drivers/pinctrl/mediatek/mtk-eint.c
+++ b/drivers/pinctrl/mediatek/mtk-eint.c
@@ -66,6 +66,11 @@ const unsigned int debounce_time_mt6795[] = {
 };
 EXPORT_SYMBOL_GPL(debounce_time_mt6795);
 
+const unsigned int debounce_time_mt6878[] = {
+	156, 313, 625, 1250, 20000, 40000, 80000, 160000, 320000, 640000, 0
+};
+EXPORT_SYMBOL_GPL(debounce_time_mt6878);
+
 static void __iomem *mtk_eint_get_offset(struct mtk_eint *eint,
 					 unsigned int eint_num,
 					 unsigned int offset)
diff --git a/drivers/pinctrl/mediatek/mtk-eint.h b/drivers/pinctrl/mediatek/mtk-eint.h
index fc31a4c0c77bf28b106943e9292d0dcc425c4922..3cdd6f6310cd0da5aa74623c5f1dbe8f8495d689 100644
--- a/drivers/pinctrl/mediatek/mtk-eint.h
+++ b/drivers/pinctrl/mediatek/mtk-eint.h
@@ -52,6 +52,7 @@ struct mtk_eint_pin {
 extern const unsigned int debounce_time_mt2701[];
 extern const unsigned int debounce_time_mt6765[];
 extern const unsigned int debounce_time_mt6795[];
+extern const unsigned int debounce_time_mt6878[];
 
 struct mtk_eint;
 

-- 
2.51.0


^ permalink raw reply	[flat|nested] 12+ messages in thread

* Re: [PATCH 3/4] pinctrl: mediatek: Add debounce times for MT6878
  2025-09-08 19:17 ` [PATCH 3/4] pinctrl: mediatek: Add debounce times for MT6878 Igor Belwon
@ 2025-09-09  8:00   ` AngeloGioacchino Del Regno
  2025-09-09 11:54     ` Igor Belwon
  0 siblings, 1 reply; 12+ messages in thread
From: AngeloGioacchino Del Regno @ 2025-09-09  8:00 UTC (permalink / raw)
  To: Igor Belwon, Linus Walleij, Rob Herring, Krzysztof Kozlowski,
	Conor Dooley, Matthias Brugger, Sean Wang
  Cc: linux-gpio, devicetree, linux-kernel, linux-arm-kernel, linux-mediatek

Il 08/09/25 21:17, Igor Belwon ha scritto:
> MT6878 uses different debounce times than other SoCs. Add them to the
> EINT driver.

The only reason why I can't give you a R-b for this is that you forgot to add
your S-o-b...

Cheers,
Angelo

> ---
>   drivers/pinctrl/mediatek/mtk-eint.c | 5 +++++
>   drivers/pinctrl/mediatek/mtk-eint.h | 1 +
>   2 files changed, 6 insertions(+)
> 
> diff --git a/drivers/pinctrl/mediatek/mtk-eint.c b/drivers/pinctrl/mediatek/mtk-eint.c
> index 9f175c73613f84b47c0160947f32da7aca7d5a18..c8c5097c11c4d14eb41bdd7f9cb93b4a5756d2b2 100644
> --- a/drivers/pinctrl/mediatek/mtk-eint.c
> +++ b/drivers/pinctrl/mediatek/mtk-eint.c
> @@ -66,6 +66,11 @@ const unsigned int debounce_time_mt6795[] = {
>   };
>   EXPORT_SYMBOL_GPL(debounce_time_mt6795);
>   
> +const unsigned int debounce_time_mt6878[] = {
> +	156, 313, 625, 1250, 20000, 40000, 80000, 160000, 320000, 640000, 0
> +};
> +EXPORT_SYMBOL_GPL(debounce_time_mt6878);
> +
>   static void __iomem *mtk_eint_get_offset(struct mtk_eint *eint,
>   					 unsigned int eint_num,
>   					 unsigned int offset)
> diff --git a/drivers/pinctrl/mediatek/mtk-eint.h b/drivers/pinctrl/mediatek/mtk-eint.h
> index fc31a4c0c77bf28b106943e9292d0dcc425c4922..3cdd6f6310cd0da5aa74623c5f1dbe8f8495d689 100644
> --- a/drivers/pinctrl/mediatek/mtk-eint.h
> +++ b/drivers/pinctrl/mediatek/mtk-eint.h
> @@ -52,6 +52,7 @@ struct mtk_eint_pin {
>   extern const unsigned int debounce_time_mt2701[];
>   extern const unsigned int debounce_time_mt6765[];
>   extern const unsigned int debounce_time_mt6795[];
> +extern const unsigned int debounce_time_mt6878[];
>   
>   struct mtk_eint;
>   
> 


^ permalink raw reply	[flat|nested] 12+ messages in thread

* Re: [PATCH 3/4] pinctrl: mediatek: Add debounce times for MT6878
  2025-09-09  8:00   ` AngeloGioacchino Del Regno
@ 2025-09-09 11:54     ` Igor Belwon
  0 siblings, 0 replies; 12+ messages in thread
From: Igor Belwon @ 2025-09-09 11:54 UTC (permalink / raw)
  To: AngeloGioacchino Del Regno, Igor Belwon, Linus Walleij,
	Rob Herring, Krzysztof Kozlowski, Conor Dooley, Matthias Brugger,
	Sean Wang
  Cc: linux-gpio, devicetree, linux-kernel, linux-arm-kernel, linux-mediatek

On Tue Sep 9, 2025 at 10:00 AM CEST, AngeloGioacchino Del Regno wrote:
> Il 08/09/25 21:17, Igor Belwon ha scritto:
>> MT6878 uses different debounce times than other SoCs. Add them to the
>> EINT driver.
>
> The only reason why I can't give you a R-b for this is that you forgot to add
> your S-o-b...
>
> Cheers,
> Angelo
>

My apologies (again).
I was rebasing these changes and rewording them a bunch, probably got
lost somewhere there. I wonder why b4 didn't scream at me.
Will add.

Thanks,
Igor

^ permalink raw reply	[flat|nested] 12+ messages in thread

* [PATCH 4/4] pinctrl: mediatek: Add support for MT6878 pinctrl
  2025-09-08 19:17 [PATCH 0/4] Add support for mt6878 pinctrl Igor Belwon
                   ` (2 preceding siblings ...)
  2025-09-08 19:17 ` [PATCH 3/4] pinctrl: mediatek: Add debounce times for MT6878 Igor Belwon
@ 2025-09-08 19:17 ` Igor Belwon
  2025-09-09  7:59   ` AngeloGioacchino Del Regno
  3 siblings, 1 reply; 12+ messages in thread
From: Igor Belwon @ 2025-09-08 19:17 UTC (permalink / raw)
  To: Linus Walleij, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
	Matthias Brugger, AngeloGioacchino Del Regno, Sean Wang
  Cc: linux-gpio, devicetree, linux-kernel, linux-arm-kernel,
	linux-mediatek, Igor Belwon

Add driver support for the pin controller found in the MediaTek
Dimensity 7300 (MT6878) SoC.

Signed-off-by: Igor Belwon <igor.belwon@mentallysanemainliners.org>
---
 drivers/pinctrl/mediatek/Kconfig              |   10 +
 drivers/pinctrl/mediatek/Makefile             |    1 +
 drivers/pinctrl/mediatek/pinctrl-mt6878.c     | 1559 +++++++++++++++++
 drivers/pinctrl/mediatek/pinctrl-mtk-mt6878.h | 2248 +++++++++++++++++++++++++
 4 files changed, 3818 insertions(+)

diff --git a/drivers/pinctrl/mediatek/Kconfig b/drivers/pinctrl/mediatek/Kconfig
index 5b191e12a8aa9d19f05bfbc51037aa788e9a3c36..4819617d936836eca59e8cc8c4ee8323ba92604f 100644
--- a/drivers/pinctrl/mediatek/Kconfig
+++ b/drivers/pinctrl/mediatek/Kconfig
@@ -181,6 +181,16 @@ config PINCTRL_MT6797
 	default ARM64 && ARCH_MEDIATEK
 	select PINCTRL_MTK_PARIS
 
+config PINCTRL_MT6878
+	bool "MediaTek MT6878 pin control"
+	depends on OF
+	depends on ARM64 || COMPILE_TEST
+	default ARM64 && ARCH_MEDIATEK
+	select PINCTRL_MTK_PARIS
+	help
+	  Say yes here to support pin controller and gpio driver
+	  on the MediaTek MT6878 SoC.
+
 config PINCTRL_MT6893
 	bool "MediaTek Dimensity MT6893 pin control"
 	depends on OF
diff --git a/drivers/pinctrl/mediatek/Makefile b/drivers/pinctrl/mediatek/Makefile
index 5d4646939ba3ab3586483d36acf5cd701b3bf0dc..ae765bd999657cd887b605e201290c041efd020e 100644
--- a/drivers/pinctrl/mediatek/Makefile
+++ b/drivers/pinctrl/mediatek/Makefile
@@ -23,6 +23,7 @@ obj-$(CONFIG_PINCTRL_MT6765)		+= pinctrl-mt6765.o
 obj-$(CONFIG_PINCTRL_MT6779)		+= pinctrl-mt6779.o
 obj-$(CONFIG_PINCTRL_MT6795)		+= pinctrl-mt6795.o
 obj-$(CONFIG_PINCTRL_MT6797)		+= pinctrl-mt6797.o
+obj-$(CONFIG_PINCTRL_MT6878)		+= pinctrl-mt6878.o
 obj-$(CONFIG_PINCTRL_MT6893)		+= pinctrl-mt6893.o
 obj-$(CONFIG_PINCTRL_MT7622)		+= pinctrl-mt7622.o
 obj-$(CONFIG_PINCTRL_MT7623)		+= pinctrl-mt7623.o
diff --git a/drivers/pinctrl/mediatek/pinctrl-mt6878.c b/drivers/pinctrl/mediatek/pinctrl-mt6878.c
new file mode 100644
index 0000000000000000000000000000000000000000..679f8cff1c516565daf9cd85f7b5036b0bcbd159
--- /dev/null
+++ b/drivers/pinctrl/mediatek/pinctrl-mt6878.c
@@ -0,0 +1,1559 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2023 MediaTek Inc.
+ * Author: Light Hsieh <light.hsieh@mediatek.com>
+ *
+ * Copyright (C) 2025 Igor Belwon <igor.belwon@mentallysanemainliners.org>
+ */
+
+#include <linux/module.h>
+#include "pinctrl-mtk-mt6878.h"
+#include "pinctrl-paris.h"
+
+/* MT6878 have multiple bases to program pin configuration listed as the below:
+ * GPIO_BASE: 0x10005000
+ * IOCFG_BL_BASE: 0x11D10000
+ * IOCFG_BM_BASE: 0x11D30000
+ * IOCFG_BR_BASE: 0x11D40000
+ * IOCFG_BL1_BASE: 0x11D50000
+ * IOCFG_BR1_BASE: 0x11D60000
+ * IOCFG_LM_BASE: 0x11E20000
+ * IOCFG_LT_BASE: 0x11E30000
+ * IOCFG_RM_BASE: 0x11EB0000
+ * IOCFG_RT_BASE: 0x11EC0000
+ * _i_based could be used to indicate what base the pin should be mapped into.
+ */
+
+#define PIN_FIELD_BASE(s_pin, e_pin, i_base, s_addr, x_addrs, s_bit, x_bits) \
+	PIN_FIELD_CALC(s_pin, e_pin, i_base, s_addr, x_addrs, s_bit, x_bits, \
+			32, 0)
+
+#define PINS_FIELD_BASE(s_pin, e_pin, i_base, s_addr, x_addrs, s_bit, x_bits) \
+	PIN_FIELD_CALC(s_pin, e_pin, i_base, s_addr, x_addrs, s_bit, x_bits,  \
+			32, 1)
+
+static const struct mtk_pin_field_calc mt6878_pin_mode_range[] = {
+	PIN_FIELD_BASE(0, 7, 0, 0x0300, 0x10, 0, 4),
+	PIN_FIELD_BASE(8, 15, 0, 0x0310, 0x10, 0, 4),
+	PIN_FIELD_BASE(16, 23, 0, 0x0320, 0x10, 0, 4),
+	PIN_FIELD_BASE(24, 31, 0, 0x0330, 0x10, 0, 4),
+	PIN_FIELD_BASE(32, 39, 0, 0x0340, 0x10, 0, 4),
+	PIN_FIELD_BASE(40, 47, 0, 0x0350, 0x10, 0, 4),
+	PIN_FIELD_BASE(48, 55, 0, 0x0360, 0x10, 0, 4),
+	PIN_FIELD_BASE(56, 63, 0, 0x0370, 0x10, 0, 4),
+	PIN_FIELD_BASE(64, 71, 0, 0x0380, 0x10, 0, 4),
+	PIN_FIELD_BASE(72, 79, 0, 0x0390, 0x10, 0, 4),
+	PIN_FIELD_BASE(80, 87, 0, 0x03a0, 0x10, 0, 4),
+	PIN_FIELD_BASE(88, 95, 0, 0x03b0, 0x10, 0, 4),
+	PIN_FIELD_BASE(96, 103, 0, 0x03c0, 0x10, 0, 4),
+	PIN_FIELD_BASE(104, 111, 0, 0x03d0, 0x10, 0, 4),
+	PIN_FIELD_BASE(112, 119, 0, 0x03e0, 0x10, 0, 4),
+	PIN_FIELD_BASE(120, 127, 0, 0x03f0, 0x10, 0, 4),
+	PIN_FIELD_BASE(128, 135, 0, 0x0400, 0x10, 0, 4),
+	PIN_FIELD_BASE(136, 143, 0, 0x0410, 0x10, 0, 4),
+	PIN_FIELD_BASE(144, 151, 0, 0x0420, 0x10, 0, 4),
+	PIN_FIELD_BASE(152, 159, 0, 0x0430, 0x10, 0, 4),
+	PIN_FIELD_BASE(160, 167, 0, 0x0440, 0x10, 0, 4),
+	PIN_FIELD_BASE(168, 175, 0, 0x0450, 0x10, 0, 4),
+	PIN_FIELD_BASE(176, 183, 0, 0x0460, 0x10, 0, 4),
+	PIN_FIELD_BASE(184, 191, 0, 0x0470, 0x10, 0, 4),
+	PIN_FIELD_BASE(192, 195, 0, 0x0480, 0x10, 0, 4),
+};
+
+static const struct mtk_pin_field_calc mt6878_pin_dir_range[] = {
+	PIN_FIELD_BASE(0, 31, 0, 0x0000, 0x10, 0, 1),
+	PIN_FIELD_BASE(32, 63, 0, 0x0010, 0x10, 0, 1),
+	PIN_FIELD_BASE(64, 95, 0, 0x0020, 0x10, 0, 1),
+	PIN_FIELD_BASE(96, 127, 0, 0x0030, 0x10, 0, 1),
+	PIN_FIELD_BASE(128, 159, 0, 0x0040, 0x10, 0, 1),
+	PIN_FIELD_BASE(160, 191, 0, 0x0050, 0x10, 0, 1),
+	PIN_FIELD_BASE(192, 195, 0, 0x0060, 0x10, 0, 1),
+};
+
+static const struct mtk_pin_field_calc mt6878_pin_di_range[] = {
+	PIN_FIELD_BASE(0, 31, 0, 0x0200, 0x10, 0, 1),
+	PIN_FIELD_BASE(32, 63, 0, 0x0210, 0x10, 0, 1),
+	PIN_FIELD_BASE(64, 95, 0, 0x0220, 0x10, 0, 1),
+	PIN_FIELD_BASE(96, 127, 0, 0x0230, 0x10, 0, 1),
+	PIN_FIELD_BASE(128, 159, 0, 0x0240, 0x10, 0, 1),
+	PIN_FIELD_BASE(160, 191, 0, 0x0250, 0x10, 0, 1),
+	PIN_FIELD_BASE(192, 195, 0, 0x0260, 0x10, 0, 1),
+};
+
+static const struct mtk_pin_field_calc mt6878_pin_do_range[] = {
+	PIN_FIELD_BASE(0, 31, 0, 0x0100, 0x10, 0, 1),
+	PIN_FIELD_BASE(32, 63, 0, 0x0110, 0x10, 0, 1),
+	PIN_FIELD_BASE(64, 95, 0, 0x0120, 0x10, 0, 1),
+	PIN_FIELD_BASE(96, 127, 0, 0x0130, 0x10, 0, 1),
+	PIN_FIELD_BASE(128, 159, 0, 0x0140, 0x10, 0, 1),
+	PIN_FIELD_BASE(160, 191, 0, 0x0150, 0x10, 0, 1),
+	PIN_FIELD_BASE(192, 195, 0, 0x0160, 0x10, 0, 1),
+};
+
+static const struct mtk_pin_field_calc mt6878_pin_ies_range[] = {
+	PIN_FIELD_BASE(0, 0, 3, 0x0070, 0x10, 9, 1),
+	PIN_FIELD_BASE(1, 1, 3, 0x0070, 0x10, 10, 1),
+	PIN_FIELD_BASE(2, 2, 3, 0x0070, 0x10, 11, 1),
+	PIN_FIELD_BASE(3, 3, 3, 0x0070, 0x10, 12, 1),
+	PIN_FIELD_BASE(4, 4, 3, 0x0070, 0x10, 13, 1),
+	PIN_FIELD_BASE(5, 5, 3, 0x0070, 0x10, 14, 1),
+	PIN_FIELD_BASE(6, 6, 4, 0x0050, 0x10, 13, 1),
+	PIN_FIELD_BASE(7, 7, 4, 0x0050, 0x10, 14, 1),
+	PIN_FIELD_BASE(8, 8, 4, 0x0050, 0x10, 15, 1),
+	PIN_FIELD_BASE(9, 9, 4, 0x0050, 0x10, 16, 1),
+	PIN_FIELD_BASE(10, 10, 4, 0x0050, 0x10, 10, 1),
+	PIN_FIELD_BASE(11, 11, 4, 0x0050, 0x10, 11, 1),
+	PIN_FIELD_BASE(12, 12, 4, 0x0050, 0x10, 12, 1),
+	PIN_FIELD_BASE(13, 13, 6, 0x0070, 0x10, 4, 1),
+	PIN_FIELD_BASE(14, 14, 6, 0x0070, 0x10, 5, 1),
+	PIN_FIELD_BASE(15, 15, 6, 0x0070, 0x10, 6, 1),
+	PIN_FIELD_BASE(16, 16, 6, 0x0070, 0x10, 7, 1),
+	PIN_FIELD_BASE(17, 17, 6, 0x0070, 0x10, 8, 1),
+	PIN_FIELD_BASE(18, 18, 6, 0x0070, 0x10, 9, 1),
+	PIN_FIELD_BASE(19, 19, 3, 0x0070, 0x10, 0, 1),
+	PIN_FIELD_BASE(20, 20, 3, 0x0070, 0x10, 1, 1),
+	PIN_FIELD_BASE(21, 21, 3, 0x0070, 0x10, 2, 1),
+	PIN_FIELD_BASE(22, 22, 3, 0x0070, 0x10, 3, 1),
+	PIN_FIELD_BASE(23, 23, 3, 0x0070, 0x10, 4, 1),
+	PIN_FIELD_BASE(24, 24, 5, 0x0040, 0x10, 1, 1),
+	PIN_FIELD_BASE(25, 25, 3, 0x0070, 0x10, 5, 1),
+	PIN_FIELD_BASE(26, 26, 3, 0x0070, 0x10, 6, 1),
+	PIN_FIELD_BASE(27, 27, 3, 0x0070, 0x10, 7, 1),
+	PIN_FIELD_BASE(28, 28, 3, 0x0070, 0x10, 8, 1),
+	PIN_FIELD_BASE(29, 29, 6, 0x0070, 0x10, 10, 1),
+	PIN_FIELD_BASE(30, 30, 6, 0x0070, 0x10, 12, 1),
+	PIN_FIELD_BASE(31, 31, 6, 0x0070, 0x10, 13, 1),
+	PIN_FIELD_BASE(32, 32, 6, 0x0070, 0x10, 11, 1),
+	PIN_FIELD_BASE(33, 33, 9, 0x0050, 0x10, 0, 1),
+	PIN_FIELD_BASE(34, 34, 9, 0x0050, 0x10, 1, 1),
+	PIN_FIELD_BASE(35, 35, 9, 0x0050, 0x10, 2, 1),
+	PIN_FIELD_BASE(36, 36, 8, 0x0090, 0x10, 0, 1),
+	PIN_FIELD_BASE(37, 37, 8, 0x0090, 0x10, 1, 1),
+	PIN_FIELD_BASE(38, 38, 8, 0x0090, 0x10, 2, 1),
+	PIN_FIELD_BASE(39, 39, 8, 0x0090, 0x10, 3, 1),
+	PIN_FIELD_BASE(40, 40, 8, 0x0090, 0x10, 4, 1),
+	PIN_FIELD_BASE(41, 41, 4, 0x0050, 0x10, 20, 1),
+	PIN_FIELD_BASE(42, 42, 4, 0x0050, 0x10, 17, 1),
+	PIN_FIELD_BASE(43, 43, 4, 0x0050, 0x10, 19, 1),
+	PIN_FIELD_BASE(44, 44, 4, 0x0050, 0x10, 21, 1),
+	PIN_FIELD_BASE(45, 45, 4, 0x0050, 0x10, 18, 1),
+	PIN_FIELD_BASE(46, 46, 4, 0x0050, 0x10, 22, 1),
+	PIN_FIELD_BASE(47, 47, 4, 0x0050, 0x10, 23, 1),
+	PIN_FIELD_BASE(48, 48, 3, 0x0070, 0x10, 25, 1),
+	PIN_FIELD_BASE(49, 49, 3, 0x0070, 0x10, 23, 1),
+	PIN_FIELD_BASE(50, 50, 3, 0x0070, 0x10, 26, 1),
+	PIN_FIELD_BASE(51, 51, 3, 0x0070, 0x10, 24, 1),
+	PIN_FIELD_BASE(52, 52, 3, 0x0070, 0x10, 17, 1),
+	PIN_FIELD_BASE(53, 53, 3, 0x0070, 0x10, 18, 1),
+	PIN_FIELD_BASE(54, 54, 3, 0x0070, 0x10, 15, 1),
+	PIN_FIELD_BASE(55, 55, 3, 0x0070, 0x10, 16, 1),
+	PIN_FIELD_BASE(56, 56, 5, 0x0040, 0x10, 8, 1),
+	PIN_FIELD_BASE(57, 57, 5, 0x0040, 0x10, 9, 1),
+	PIN_FIELD_BASE(58, 58, 3, 0x0070, 0x10, 22, 1),
+	PIN_FIELD_BASE(59, 59, 3, 0x0070, 0x10, 21, 1),
+	PIN_FIELD_BASE(60, 60, 8, 0x0090, 0x10, 21, 1),
+	PIN_FIELD_BASE(61, 61, 8, 0x0090, 0x10, 22, 1),
+	PIN_FIELD_BASE(62, 62, 8, 0x0090, 0x10, 24, 1),
+	PIN_FIELD_BASE(63, 63, 8, 0x0090, 0x10, 23, 1),
+	PIN_FIELD_BASE(64, 64, 8, 0x0090, 0x10, 25, 1),
+	PIN_FIELD_BASE(65, 65, 8, 0x0090, 0x10, 26, 1),
+	PIN_FIELD_BASE(66, 66, 8, 0x0090, 0x10, 28, 1),
+	PIN_FIELD_BASE(67, 67, 8, 0x0090, 0x10, 27, 1),
+	PIN_FIELD_BASE(68, 68, 5, 0x0040, 0x10, 3, 1),
+	PIN_FIELD_BASE(69, 69, 5, 0x0040, 0x10, 4, 1),
+	PIN_FIELD_BASE(70, 70, 5, 0x0040, 0x10, 6, 1),
+	PIN_FIELD_BASE(71, 71, 5, 0x0040, 0x10, 5, 1),
+	PIN_FIELD_BASE(72, 72, 5, 0x0040, 0x10, 10, 1),
+	PIN_FIELD_BASE(73, 73, 5, 0x0040, 0x10, 11, 1),
+	PIN_FIELD_BASE(74, 74, 5, 0x0040, 0x10, 13, 1),
+	PIN_FIELD_BASE(75, 75, 5, 0x0040, 0x10, 12, 1),
+	PIN_FIELD_BASE(76, 76, 5, 0x0040, 0x10, 0, 1),
+	PIN_FIELD_BASE(77, 77, 2, 0x0040, 0x10, 0, 1),
+	PIN_FIELD_BASE(78, 78, 2, 0x0040, 0x10, 1, 1),
+	PIN_FIELD_BASE(79, 79, 2, 0x0040, 0x10, 2, 1),
+	PIN_FIELD_BASE(80, 80, 2, 0x0040, 0x10, 3, 1),
+	PIN_FIELD_BASE(81, 81, 2, 0x0040, 0x10, 4, 1),
+	PIN_FIELD_BASE(82, 82, 2, 0x0040, 0x10, 5, 1),
+	PIN_FIELD_BASE(83, 83, 2, 0x0040, 0x10, 9, 1),
+	PIN_FIELD_BASE(84, 84, 2, 0x0040, 0x10, 11, 1),
+	PIN_FIELD_BASE(85, 85, 2, 0x0040, 0x10, 10, 1),
+	PIN_FIELD_BASE(86, 86, 2, 0x0040, 0x10, 12, 1),
+	PIN_FIELD_BASE(87, 87, 2, 0x0040, 0x10, 14, 1),
+	PIN_FIELD_BASE(88, 88, 2, 0x0040, 0x10, 13, 1),
+	PIN_FIELD_BASE(89, 89, 4, 0x0050, 0x10, 9, 1),
+	PIN_FIELD_BASE(90, 90, 4, 0x0050, 0x10, 24, 1),
+	PIN_FIELD_BASE(91, 91, 4, 0x0050, 0x10, 8, 1),
+	PIN_FIELD_BASE(92, 92, 8, 0x0090, 0x10, 5, 1),
+	PIN_FIELD_BASE(93, 93, 8, 0x0090, 0x10, 6, 1),
+	PIN_FIELD_BASE(94, 94, 8, 0x0090, 0x10, 7, 1),
+	PIN_FIELD_BASE(95, 95, 8, 0x0090, 0x10, 8, 1),
+	PIN_FIELD_BASE(96, 96, 8, 0x0090, 0x10, 9, 1),
+	PIN_FIELD_BASE(97, 97, 1, 0x0070, 0x10, 19, 1),
+	PIN_FIELD_BASE(98, 98, 1, 0x0070, 0x10, 18, 1),
+	PIN_FIELD_BASE(99, 99, 1, 0x0070, 0x10, 0, 1),
+	PIN_FIELD_BASE(100, 100, 1, 0x0070, 0x10, 1, 1),
+	PIN_FIELD_BASE(101, 101, 1, 0x0070, 0x10, 10, 1),
+	PIN_FIELD_BASE(102, 102, 1, 0x0070, 0x10, 11, 1),
+	PIN_FIELD_BASE(103, 103, 1, 0x0070, 0x10, 12, 1),
+	PIN_FIELD_BASE(104, 104, 1, 0x0070, 0x10, 13, 1),
+	PIN_FIELD_BASE(105, 105, 1, 0x0070, 0x10, 14, 1),
+	PIN_FIELD_BASE(106, 106, 1, 0x0070, 0x10, 15, 1),
+	PIN_FIELD_BASE(107, 107, 1, 0x0070, 0x10, 16, 1),
+	PIN_FIELD_BASE(108, 108, 1, 0x0070, 0x10, 17, 1),
+	PIN_FIELD_BASE(109, 109, 1, 0x0070, 0x10, 2, 1),
+	PIN_FIELD_BASE(110, 110, 1, 0x0070, 0x10, 3, 1),
+	PIN_FIELD_BASE(111, 111, 1, 0x0070, 0x10, 4, 1),
+	PIN_FIELD_BASE(112, 112, 1, 0x0070, 0x10, 5, 1),
+	PIN_FIELD_BASE(113, 113, 1, 0x0070, 0x10, 6, 1),
+	PIN_FIELD_BASE(114, 114, 1, 0x0070, 0x10, 7, 1),
+	PIN_FIELD_BASE(115, 115, 1, 0x0070, 0x10, 8, 1),
+	PIN_FIELD_BASE(116, 116, 1, 0x0070, 0x10, 9, 1),
+	PIN_FIELD_BASE(117, 117, 1, 0x0070, 0x10, 20, 1),
+	PIN_FIELD_BASE(118, 118, 1, 0x0070, 0x10, 21, 1),
+	PIN_FIELD_BASE(119, 119, 1, 0x0070, 0x10, 22, 1),
+	PIN_FIELD_BASE(120, 120, 1, 0x0070, 0x10, 23, 1),
+	PIN_FIELD_BASE(121, 121, 1, 0x0070, 0x10, 24, 1),
+	PIN_FIELD_BASE(122, 122, 1, 0x0070, 0x10, 25, 1),
+	PIN_FIELD_BASE(123, 123, 1, 0x0070, 0x10, 26, 1),
+	PIN_FIELD_BASE(124, 124, 1, 0x0070, 0x10, 27, 1),
+	PIN_FIELD_BASE(125, 125, 8, 0x0090, 0x10, 20, 1),
+	PIN_FIELD_BASE(126, 126, 8, 0x0090, 0x10, 29, 1),
+	PIN_FIELD_BASE(127, 127, 8, 0x0090, 0x10, 30, 1),
+	PIN_FIELD_BASE(128, 128, 8, 0x0090, 0x10, 31, 1),
+	PIN_FIELD_BASE(129, 129, 8, 0x0090, 0x10, 10, 1),
+	PIN_FIELD_BASE(130, 130, 8, 0x0090, 0x10, 13, 1),
+	PIN_FIELD_BASE(131, 131, 6, 0x0070, 0x10, 14, 1),
+	PIN_FIELD_BASE(132, 132, 6, 0x0070, 0x10, 17, 1),
+	PIN_FIELD_BASE(133, 133, 8, 0x0090, 0x10, 11, 1),
+	PIN_FIELD_BASE(134, 134, 8, 0x0090, 0x10, 14, 1),
+	PIN_FIELD_BASE(135, 135, 6, 0x0070, 0x10, 15, 1),
+	PIN_FIELD_BASE(136, 136, 6, 0x0070, 0x10, 18, 1),
+	PIN_FIELD_BASE(137, 137, 6, 0x0070, 0x10, 16, 1),
+	PIN_FIELD_BASE(138, 138, 6, 0x0070, 0x10, 19, 1),
+	PIN_FIELD_BASE(139, 139, 6, 0x0070, 0x10, 0, 1),
+	PIN_FIELD_BASE(140, 140, 6, 0x0070, 0x10, 2, 1),
+	PIN_FIELD_BASE(141, 141, 6, 0x0070, 0x10, 1, 1),
+	PIN_FIELD_BASE(142, 142, 6, 0x0070, 0x10, 3, 1),
+	PIN_FIELD_BASE(143, 143, 8, 0x0090, 0x10, 12, 1),
+	PIN_FIELD_BASE(144, 144, 8, 0x0090, 0x10, 15, 1),
+	PIN_FIELD_BASE(145, 145, 5, 0x0040, 0x10, 2, 1),
+	PIN_FIELD_BASE(146, 146, 5, 0x0040, 0x10, 7, 1),
+	PIN_FIELD_BASE(147, 147, 3, 0x0070, 0x10, 19, 1),
+	PIN_FIELD_BASE(148, 148, 3, 0x0070, 0x10, 20, 1),
+	PIN_FIELD_BASE(149, 149, 8, 0x0090, 0x10, 16, 1),
+	PIN_FIELD_BASE(150, 150, 8, 0x0090, 0x10, 17, 1),
+	PIN_FIELD_BASE(151, 151, 8, 0x0090, 0x10, 18, 1),
+	PIN_FIELD_BASE(152, 152, 8, 0x0090, 0x10, 19, 1),
+	PIN_FIELD_BASE(153, 153, 2, 0x0040, 0x10, 6, 1),
+	PIN_FIELD_BASE(154, 154, 2, 0x0040, 0x10, 7, 1),
+	PIN_FIELD_BASE(155, 155, 2, 0x0040, 0x10, 8, 1),
+	PIN_FIELD_BASE(156, 156, 9, 0x0050, 0x10, 15, 1),
+	PIN_FIELD_BASE(157, 157, 9, 0x0050, 0x10, 16, 1),
+	PIN_FIELD_BASE(158, 158, 9, 0x0050, 0x10, 17, 1),
+	PIN_FIELD_BASE(159, 159, 9, 0x0050, 0x10, 18, 1),
+	PIN_FIELD_BASE(160, 160, 4, 0x0050, 0x10, 26, 1),
+	PIN_FIELD_BASE(161, 161, 4, 0x0050, 0x10, 25, 1),
+	PIN_FIELD_BASE(162, 162, 4, 0x0050, 0x10, 28, 1),
+	PIN_FIELD_BASE(163, 163, 4, 0x0050, 0x10, 27, 1),
+	PIN_FIELD_BASE(164, 164, 4, 0x0050, 0x10, 0, 1),
+	PIN_FIELD_BASE(165, 165, 4, 0x0050, 0x10, 7, 1),
+	PIN_FIELD_BASE(166, 166, 4, 0x0050, 0x10, 3, 1),
+	PIN_FIELD_BASE(167, 167, 4, 0x0050, 0x10, 4, 1),
+	PIN_FIELD_BASE(168, 168, 4, 0x0050, 0x10, 5, 1),
+	PIN_FIELD_BASE(169, 169, 4, 0x0050, 0x10, 6, 1),
+	PIN_FIELD_BASE(170, 170, 4, 0x0050, 0x10, 1, 1),
+	PIN_FIELD_BASE(171, 171, 4, 0x0050, 0x10, 2, 1),
+	PIN_FIELD_BASE(172, 172, 9, 0x0050, 0x10, 7, 1),
+	PIN_FIELD_BASE(173, 173, 9, 0x0050, 0x10, 8, 1),
+	PIN_FIELD_BASE(174, 174, 9, 0x0050, 0x10, 3, 1),
+	PIN_FIELD_BASE(175, 175, 9, 0x0050, 0x10, 4, 1),
+	PIN_FIELD_BASE(176, 176, 9, 0x0050, 0x10, 5, 1),
+	PIN_FIELD_BASE(177, 177, 9, 0x0050, 0x10, 9, 1),
+	PIN_FIELD_BASE(178, 178, 9, 0x0050, 0x10, 10, 1),
+	PIN_FIELD_BASE(179, 179, 9, 0x0050, 0x10, 11, 1),
+	PIN_FIELD_BASE(180, 180, 9, 0x0050, 0x10, 12, 1),
+	PIN_FIELD_BASE(181, 181, 9, 0x0050, 0x10, 13, 1),
+	PIN_FIELD_BASE(182, 182, 9, 0x0050, 0x10, 14, 1),
+	PIN_FIELD_BASE(183, 183, 9, 0x0050, 0x10, 6, 1),
+	PIN_FIELD_BASE(184, 184, 7, 0x0040, 0x10, 10, 1),
+	PIN_FIELD_BASE(185, 185, 7, 0x0040, 0x10, 0, 1),
+	PIN_FIELD_BASE(186, 186, 7, 0x0040, 0x10, 1, 1),
+	PIN_FIELD_BASE(187, 187, 7, 0x0040, 0x10, 11, 1),
+	PIN_FIELD_BASE(188, 188, 7, 0x0040, 0x10, 2, 1),
+	PIN_FIELD_BASE(189, 189, 7, 0x0040, 0x10, 3, 1),
+	PIN_FIELD_BASE(190, 190, 7, 0x0040, 0x10, 4, 1),
+	PIN_FIELD_BASE(191, 191, 7, 0x0040, 0x10, 5, 1),
+	PIN_FIELD_BASE(192, 192, 7, 0x0040, 0x10, 6, 1),
+	PIN_FIELD_BASE(193, 193, 7, 0x0040, 0x10, 7, 1),
+	PIN_FIELD_BASE(194, 194, 7, 0x0040, 0x10, 8, 1),
+	PIN_FIELD_BASE(195, 195, 7, 0x0040, 0x10, 9, 1),
+};
+
+static const struct mtk_pin_field_calc mt6878_pin_smt_range[] = {
+	PIN_FIELD_BASE(0, 0, 3, 0x00e0, 0x10, 16, 1),
+	PIN_FIELD_BASE(1, 1, 3, 0x00e0, 0x10, 16, 1),
+	PIN_FIELD_BASE(2, 2, 3, 0x00e0, 0x10, 15, 1),
+	PIN_FIELD_BASE(3, 3, 3, 0x00e0, 0x10, 15, 1),
+	PIN_FIELD_BASE(4, 4, 3, 0x00e0, 0x10, 9, 1),
+	PIN_FIELD_BASE(5, 5, 3, 0x00e0, 0x10, 10, 1),
+	PIN_FIELD_BASE(6, 6, 4, 0x00b0, 0x10, 2, 1),
+	PIN_FIELD_BASE(7, 7, 4, 0x00b0, 0x10, 3, 1),
+	PIN_FIELD_BASE(8, 8, 4, 0x00b0, 0x10, 11, 1),
+	PIN_FIELD_BASE(9, 9, 4, 0x00b0, 0x10, 11, 1),
+	PIN_FIELD_BASE(10, 10, 4, 0x00b0, 0x10, 11, 1),
+	PIN_FIELD_BASE(11, 11, 4, 0x00b0, 0x10, 11, 1),
+	PIN_FIELD_BASE(12, 12, 4, 0x00b0, 0x10, 11, 1),
+	PIN_FIELD_BASE(13, 13, 6, 0x00e0, 0x10, 8, 1),
+	PIN_FIELD_BASE(14, 14, 6, 0x00e0, 0x10, 8, 1),
+	PIN_FIELD_BASE(15, 15, 6, 0x00e0, 0x10, 8, 1),
+	PIN_FIELD_BASE(16, 16, 6, 0x00e0, 0x10, 8, 1),
+	PIN_FIELD_BASE(17, 17, 6, 0x00e0, 0x10, 8, 1),
+	PIN_FIELD_BASE(18, 18, 6, 0x00e0, 0x10, 7, 1),
+	PIN_FIELD_BASE(19, 19, 3, 0x00e0, 0x10, 0, 1),
+	PIN_FIELD_BASE(20, 20, 3, 0x00e0, 0x10, 1, 1),
+	PIN_FIELD_BASE(21, 21, 3, 0x00e0, 0x10, 2, 1),
+	PIN_FIELD_BASE(22, 22, 3, 0x00e0, 0x10, 3, 1),
+	PIN_FIELD_BASE(23, 23, 3, 0x00e0, 0x10, 4, 1),
+	PIN_FIELD_BASE(24, 24, 5, 0x00b0, 0x10, 0, 1),
+	PIN_FIELD_BASE(25, 25, 3, 0x00e0, 0x10, 5, 1),
+	PIN_FIELD_BASE(26, 26, 3, 0x00e0, 0x10, 6, 1),
+	PIN_FIELD_BASE(27, 27, 3, 0x00e0, 0x10, 7, 1),
+	PIN_FIELD_BASE(28, 28, 3, 0x00e0, 0x10, 8, 1),
+	PIN_FIELD_BASE(29, 29, 6, 0x00e0, 0x10, 4, 1),
+	PIN_FIELD_BASE(30, 30, 6, 0x00e0, 0x10, 9, 1),
+	PIN_FIELD_BASE(31, 31, 6, 0x00e0, 0x10, 6, 1),
+	PIN_FIELD_BASE(32, 32, 6, 0x00e0, 0x10, 5, 1),
+	PIN_FIELD_BASE(33, 33, 9, 0x00f0, 0x10, 0, 1),
+	PIN_FIELD_BASE(34, 34, 9, 0x00f0, 0x10, 1, 1),
+	PIN_FIELD_BASE(35, 35, 9, 0x00f0, 0x10, 2, 1),
+	PIN_FIELD_BASE(36, 36, 8, 0x0130, 0x10, 0, 1),
+	PIN_FIELD_BASE(37, 37, 8, 0x0130, 0x10, 1, 1),
+	PIN_FIELD_BASE(38, 38, 8, 0x0130, 0x10, 2, 1),
+	PIN_FIELD_BASE(39, 39, 8, 0x0130, 0x10, 3, 1),
+	PIN_FIELD_BASE(40, 40, 8, 0x0130, 0x10, 4, 1),
+	PIN_FIELD_BASE(41, 41, 4, 0x00b0, 0x10, 7, 1),
+	PIN_FIELD_BASE(42, 42, 4, 0x00b0, 0x10, 4, 1),
+	PIN_FIELD_BASE(43, 43, 4, 0x00b0, 0x10, 6, 1),
+	PIN_FIELD_BASE(44, 44, 4, 0x00b0, 0x10, 8, 1),
+	PIN_FIELD_BASE(45, 45, 4, 0x00b0, 0x10, 5, 1),
+	PIN_FIELD_BASE(46, 46, 4, 0x00b0, 0x10, 12, 1),
+	PIN_FIELD_BASE(47, 47, 4, 0x00b0, 0x10, 12, 1),
+	PIN_FIELD_BASE(48, 48, 3, 0x00e0, 0x10, 16, 1),
+	PIN_FIELD_BASE(49, 49, 3, 0x00e0, 0x10, 16, 1),
+	PIN_FIELD_BASE(50, 50, 3, 0x00e0, 0x10, 14, 1),
+	PIN_FIELD_BASE(51, 51, 3, 0x00e0, 0x10, 14, 1),
+	PIN_FIELD_BASE(52, 52, 3, 0x00e0, 0x10, 12, 1),
+	PIN_FIELD_BASE(53, 53, 3, 0x00e0, 0x10, 13, 1),
+	PIN_FIELD_BASE(54, 54, 3, 0x00e0, 0x10, 17, 1),
+	PIN_FIELD_BASE(55, 55, 3, 0x00e0, 0x10, 11, 1),
+	PIN_FIELD_BASE(56, 56, 5, 0x00b0, 0x10, 8, 1),
+	PIN_FIELD_BASE(57, 57, 5, 0x00b0, 0x10, 9, 1),
+	PIN_FIELD_BASE(58, 58, 3, 0x00e0, 0x10, 21, 1),
+	PIN_FIELD_BASE(59, 59, 3, 0x00e0, 0x10, 20, 1),
+	PIN_FIELD_BASE(60, 60, 8, 0x0130, 0x10, 20, 1),
+	PIN_FIELD_BASE(61, 61, 8, 0x0130, 0x10, 21, 1),
+	PIN_FIELD_BASE(62, 62, 8, 0x0130, 0x10, 23, 1),
+	PIN_FIELD_BASE(63, 63, 8, 0x0130, 0x10, 22, 1),
+	PIN_FIELD_BASE(64, 64, 8, 0x0130, 0x10, 24, 1),
+	PIN_FIELD_BASE(65, 65, 8, 0x0130, 0x10, 25, 1),
+	PIN_FIELD_BASE(66, 66, 8, 0x0130, 0x10, 27, 1),
+	PIN_FIELD_BASE(67, 67, 8, 0x0130, 0x10, 26, 1),
+	PIN_FIELD_BASE(68, 68, 5, 0x00b0, 0x10, 3, 1),
+	PIN_FIELD_BASE(69, 69, 5, 0x00b0, 0x10, 4, 1),
+	PIN_FIELD_BASE(70, 70, 5, 0x00b0, 0x10, 6, 1),
+	PIN_FIELD_BASE(71, 71, 5, 0x00b0, 0x10, 5, 1),
+	PIN_FIELD_BASE(72, 72, 5, 0x00b0, 0x10, 10, 1),
+	PIN_FIELD_BASE(73, 73, 5, 0x00b0, 0x10, 11, 1),
+	PIN_FIELD_BASE(74, 74, 5, 0x00b0, 0x10, 13, 1),
+	PIN_FIELD_BASE(75, 75, 5, 0x00b0, 0x10, 12, 1),
+	PIN_FIELD_BASE(76, 76, 5, 0x00b0, 0x10, 1, 1),
+	PIN_FIELD_BASE(77, 77, 2, 0x00e0, 0x10, 0, 1),
+	PIN_FIELD_BASE(78, 78, 2, 0x00e0, 0x10, 1, 1),
+	PIN_FIELD_BASE(79, 79, 2, 0x00e0, 0x10, 2, 1),
+	PIN_FIELD_BASE(80, 80, 2, 0x00e0, 0x10, 3, 1),
+	PIN_FIELD_BASE(81, 81, 2, 0x00e0, 0x10, 4, 1),
+	PIN_FIELD_BASE(82, 82, 2, 0x00e0, 0x10, 5, 1),
+	PIN_FIELD_BASE(83, 83, 2, 0x00e0, 0x10, 6, 1),
+	PIN_FIELD_BASE(84, 84, 2, 0x00e0, 0x10, 9, 1),
+	PIN_FIELD_BASE(85, 85, 2, 0x00e0, 0x10, 8, 1),
+	PIN_FIELD_BASE(86, 86, 2, 0x00e0, 0x10, 10, 1),
+	PIN_FIELD_BASE(87, 87, 2, 0x00e0, 0x10, 12, 1),
+	PIN_FIELD_BASE(88, 88, 2, 0x00e0, 0x10, 11, 1),
+	PIN_FIELD_BASE(89, 89, 4, 0x00b0, 0x10, 12, 1),
+	PIN_FIELD_BASE(90, 90, 4, 0x00b0, 0x10, 13, 1),
+	PIN_FIELD_BASE(91, 91, 4, 0x00b0, 0x10, 12, 1),
+	PIN_FIELD_BASE(92, 92, 8, 0x0130, 0x10, 5, 1),
+	PIN_FIELD_BASE(93, 93, 8, 0x0130, 0x10, 6, 1),
+	PIN_FIELD_BASE(94, 94, 8, 0x0130, 0x10, 7, 1),
+	PIN_FIELD_BASE(95, 95, 8, 0x0130, 0x10, 8, 1),
+	PIN_FIELD_BASE(96, 96, 8, 0x0130, 0x10, 9, 1),
+	PIN_FIELD_BASE(97, 97, 1, 0x0120, 0x10, 25, 1),
+	PIN_FIELD_BASE(98, 98, 1, 0x0120, 0x10, 25, 1),
+	PIN_FIELD_BASE(99, 99, 1, 0x0120, 0x10, 0, 1),
+	PIN_FIELD_BASE(100, 100, 1, 0x0120, 0x10, 1, 1),
+	PIN_FIELD_BASE(101, 101, 1, 0x0120, 0x10, 10, 1),
+	PIN_FIELD_BASE(102, 102, 1, 0x0120, 0x10, 11, 1),
+	PIN_FIELD_BASE(103, 103, 1, 0x0120, 0x10, 12, 1),
+	PIN_FIELD_BASE(104, 104, 1, 0x0120, 0x10, 13, 1),
+	PIN_FIELD_BASE(105, 105, 1, 0x0120, 0x10, 14, 1),
+	PIN_FIELD_BASE(106, 106, 1, 0x0120, 0x10, 15, 1),
+	PIN_FIELD_BASE(107, 107, 1, 0x0120, 0x10, 16, 1),
+	PIN_FIELD_BASE(108, 108, 1, 0x0120, 0x10, 17, 1),
+	PIN_FIELD_BASE(109, 109, 1, 0x0120, 0x10, 2, 1),
+	PIN_FIELD_BASE(110, 110, 1, 0x0120, 0x10, 3, 1),
+	PIN_FIELD_BASE(111, 111, 1, 0x0120, 0x10, 4, 1),
+	PIN_FIELD_BASE(112, 112, 1, 0x0120, 0x10, 5, 1),
+	PIN_FIELD_BASE(113, 113, 1, 0x0120, 0x10, 6, 1),
+	PIN_FIELD_BASE(114, 114, 1, 0x0120, 0x10, 7, 1),
+	PIN_FIELD_BASE(115, 115, 1, 0x0120, 0x10, 8, 1),
+	PIN_FIELD_BASE(116, 116, 1, 0x0120, 0x10, 9, 1),
+	PIN_FIELD_BASE(117, 117, 1, 0x0120, 0x10, 18, 1),
+	PIN_FIELD_BASE(118, 118, 1, 0x0120, 0x10, 19, 1),
+	PIN_FIELD_BASE(119, 119, 1, 0x0120, 0x10, 20, 1),
+	PIN_FIELD_BASE(120, 120, 1, 0x0120, 0x10, 21, 1),
+	PIN_FIELD_BASE(121, 121, 1, 0x0120, 0x10, 22, 1),
+	PIN_FIELD_BASE(122, 122, 1, 0x0120, 0x10, 23, 1),
+	PIN_FIELD_BASE(123, 123, 1, 0x0120, 0x10, 24, 1),
+	PIN_FIELD_BASE(124, 124, 1, 0x0120, 0x10, 24, 1),
+	PIN_FIELD_BASE(125, 125, 8, 0x0130, 0x10, 19, 1),
+	PIN_FIELD_BASE(126, 126, 8, 0x0130, 0x10, 28, 1),
+	PIN_FIELD_BASE(127, 127, 8, 0x0130, 0x10, 29, 1),
+	PIN_FIELD_BASE(128, 128, 8, 0x0130, 0x10, 30, 1),
+	PIN_FIELD_BASE(129, 129, 8, 0x0130, 0x10, 10, 1),
+	PIN_FIELD_BASE(130, 130, 8, 0x0130, 0x10, 13, 1),
+	PIN_FIELD_BASE(131, 131, 6, 0x00e0, 0x10, 10, 1),
+	PIN_FIELD_BASE(132, 132, 6, 0x00e0, 0x10, 13, 1),
+	PIN_FIELD_BASE(133, 133, 8, 0x0130, 0x10, 11, 1),
+	PIN_FIELD_BASE(134, 134, 8, 0x0130, 0x10, 14, 1),
+	PIN_FIELD_BASE(135, 135, 6, 0x00e0, 0x10, 11, 1),
+	PIN_FIELD_BASE(136, 136, 6, 0x00e0, 0x10, 14, 1),
+	PIN_FIELD_BASE(137, 137, 6, 0x00e0, 0x10, 12, 1),
+	PIN_FIELD_BASE(138, 138, 6, 0x00e0, 0x10, 15, 1),
+	PIN_FIELD_BASE(139, 139, 6, 0x00e0, 0x10, 0, 1),
+	PIN_FIELD_BASE(140, 140, 6, 0x00e0, 0x10, 2, 1),
+	PIN_FIELD_BASE(141, 141, 6, 0x00e0, 0x10, 1, 1),
+	PIN_FIELD_BASE(142, 142, 6, 0x00e0, 0x10, 3, 1),
+	PIN_FIELD_BASE(143, 143, 8, 0x0130, 0x10, 12, 1),
+	PIN_FIELD_BASE(144, 144, 8, 0x0130, 0x10, 15, 1),
+	PIN_FIELD_BASE(145, 145, 5, 0x00b0, 0x10, 2, 1),
+	PIN_FIELD_BASE(146, 146, 5, 0x00b0, 0x10, 7, 1),
+	PIN_FIELD_BASE(147, 147, 3, 0x00e0, 0x10, 18, 1),
+	PIN_FIELD_BASE(148, 148, 3, 0x00e0, 0x10, 19, 1),
+	PIN_FIELD_BASE(149, 149, 8, 0x0130, 0x10, 16, 1),
+	PIN_FIELD_BASE(150, 150, 8, 0x0130, 0x10, 17, 1),
+	PIN_FIELD_BASE(151, 151, 8, 0x0130, 0x10, 18, 1),
+	PIN_FIELD_BASE(152, 152, 8, 0x0130, 0x10, 18, 1),
+	PIN_FIELD_BASE(153, 153, 2, 0x00e0, 0x10, 7, 1),
+	PIN_FIELD_BASE(154, 154, 2, 0x00e0, 0x10, 7, 1),
+	PIN_FIELD_BASE(155, 155, 2, 0x00e0, 0x10, 7, 1),
+	PIN_FIELD_BASE(156, 156, 9, 0x00f0, 0x10, 7, 1),
+	PIN_FIELD_BASE(157, 157, 9, 0x00f0, 0x10, 8, 1),
+	PIN_FIELD_BASE(158, 158, 9, 0x00f0, 0x10, 9, 1),
+	PIN_FIELD_BASE(159, 159, 9, 0x00f0, 0x10, 10, 1),
+	PIN_FIELD_BASE(160, 160, 4, 0x00b0, 0x10, 13, 1),
+	PIN_FIELD_BASE(161, 161, 4, 0x00b0, 0x10, 13, 1),
+	PIN_FIELD_BASE(162, 162, 4, 0x00b0, 0x10, 13, 1),
+	PIN_FIELD_BASE(163, 163, 4, 0x00b0, 0x10, 9, 1),
+	PIN_FIELD_BASE(164, 164, 4, 0x00b0, 0x10, 10, 1),
+	PIN_FIELD_BASE(165, 165, 4, 0x00b0, 0x10, 10, 1),
+	PIN_FIELD_BASE(166, 166, 4, 0x00b0, 0x10, 10, 1),
+	PIN_FIELD_BASE(167, 167, 4, 0x00b0, 0x10, 10, 1),
+	PIN_FIELD_BASE(168, 168, 4, 0x00b0, 0x10, 10, 1),
+	PIN_FIELD_BASE(169, 169, 4, 0x00b0, 0x10, 10, 1),
+	PIN_FIELD_BASE(170, 170, 4, 0x00b0, 0x10, 0, 1),
+	PIN_FIELD_BASE(171, 171, 4, 0x00b0, 0x10, 1, 1),
+	PIN_FIELD_BASE(172, 172, 9, 0x00f0, 0x10, 5, 1),
+	PIN_FIELD_BASE(173, 173, 9, 0x00f0, 0x10, 5, 1),
+	PIN_FIELD_BASE(174, 174, 9, 0x00f0, 0x10, 5, 1),
+	PIN_FIELD_BASE(175, 175, 9, 0x00f0, 0x10, 5, 1),
+	PIN_FIELD_BASE(176, 176, 9, 0x00f0, 0x10, 5, 1),
+	PIN_FIELD_BASE(177, 177, 9, 0x00f0, 0x10, 5, 1),
+	PIN_FIELD_BASE(178, 178, 9, 0x00f0, 0x10, 6, 1),
+	PIN_FIELD_BASE(179, 179, 9, 0x00f0, 0x10, 6, 1),
+	PIN_FIELD_BASE(180, 180, 9, 0x00f0, 0x10, 6, 1),
+	PIN_FIELD_BASE(181, 181, 9, 0x00f0, 0x10, 3, 1),
+	PIN_FIELD_BASE(182, 182, 9, 0x00f0, 0x10, 4, 1),
+	PIN_FIELD_BASE(183, 183, 9, 0x00f0, 0x10, 5, 1),
+	PIN_FIELD_BASE(184, 184, 7, 0x00d0, 0x10, 10, 1),
+	PIN_FIELD_BASE(185, 185, 7, 0x00d0, 0x10, 0, 1),
+	PIN_FIELD_BASE(186, 186, 7, 0x00d0, 0x10, 1, 1),
+	PIN_FIELD_BASE(187, 187, 7, 0x00d0, 0x10, 11, 1),
+	PIN_FIELD_BASE(188, 188, 7, 0x00d0, 0x10, 2, 1),
+	PIN_FIELD_BASE(189, 189, 7, 0x00d0, 0x10, 3, 1),
+	PIN_FIELD_BASE(190, 190, 7, 0x00d0, 0x10, 4, 1),
+	PIN_FIELD_BASE(191, 191, 7, 0x00d0, 0x10, 5, 1),
+	PIN_FIELD_BASE(192, 192, 7, 0x00d0, 0x10, 6, 1),
+	PIN_FIELD_BASE(193, 193, 7, 0x00d0, 0x10, 7, 1),
+	PIN_FIELD_BASE(194, 194, 7, 0x00d0, 0x10, 8, 1),
+	PIN_FIELD_BASE(195, 195, 7, 0x00d0, 0x10, 9, 1),
+};
+
+static const struct mtk_pin_field_calc mt6878_pin_pu_range[] = {
+	PIN_FIELD_BASE(0, 0, 3, 0x00b0, 0x10, 9, 1),
+	PIN_FIELD_BASE(1, 1, 3, 0x00b0, 0x10, 10, 1),
+	PIN_FIELD_BASE(2, 2, 3, 0x00b0, 0x10, 11, 1),
+	PIN_FIELD_BASE(3, 3, 3, 0x00b0, 0x10, 12, 1),
+	PIN_FIELD_BASE(4, 4, 3, 0x00b0, 0x10, 13, 1),
+	PIN_FIELD_BASE(5, 5, 3, 0x00b0, 0x10, 14, 1),
+	PIN_FIELD_BASE(6, 6, 4, 0x0090, 0x10, 13, 1),
+	PIN_FIELD_BASE(7, 7, 4, 0x0090, 0x10, 14, 1),
+	PIN_FIELD_BASE(8, 8, 4, 0x0090, 0x10, 15, 1),
+	PIN_FIELD_BASE(9, 9, 4, 0x0090, 0x10, 16, 1),
+	PIN_FIELD_BASE(10, 10, 4, 0x0090, 0x10, 10, 1),
+	PIN_FIELD_BASE(11, 11, 4, 0x0090, 0x10, 11, 1),
+	PIN_FIELD_BASE(12, 12, 4, 0x0090, 0x10, 12, 1),
+	PIN_FIELD_BASE(13, 13, 6, 0x00b0, 0x10, 4, 1),
+	PIN_FIELD_BASE(14, 14, 6, 0x00b0, 0x10, 5, 1),
+	PIN_FIELD_BASE(15, 15, 6, 0x00b0, 0x10, 6, 1),
+	PIN_FIELD_BASE(16, 16, 6, 0x00b0, 0x10, 7, 1),
+	PIN_FIELD_BASE(17, 17, 6, 0x00b0, 0x10, 8, 1),
+	PIN_FIELD_BASE(18, 18, 6, 0x00b0, 0x10, 9, 1),
+	PIN_FIELD_BASE(19, 19, 3, 0x00b0, 0x10, 0, 1),
+	PIN_FIELD_BASE(20, 20, 3, 0x00b0, 0x10, 1, 1),
+	PIN_FIELD_BASE(21, 21, 3, 0x00b0, 0x10, 2, 1),
+	PIN_FIELD_BASE(22, 22, 3, 0x00b0, 0x10, 3, 1),
+	PIN_FIELD_BASE(23, 23, 3, 0x00b0, 0x10, 4, 1),
+	PIN_FIELD_BASE(24, 24, 5, 0x0080, 0x10, 1, 1),
+	PIN_FIELD_BASE(25, 25, 3, 0x00b0, 0x10, 5, 1),
+	PIN_FIELD_BASE(26, 26, 3, 0x00b0, 0x10, 6, 1),
+	PIN_FIELD_BASE(27, 27, 3, 0x00b0, 0x10, 7, 1),
+	PIN_FIELD_BASE(28, 28, 3, 0x00b0, 0x10, 8, 1),
+	PIN_FIELD_BASE(29, 29, 6, 0x00b0, 0x10, 10, 1),
+	PIN_FIELD_BASE(30, 30, 6, 0x00b0, 0x10, 12, 1),
+	PIN_FIELD_BASE(31, 31, 6, 0x00b0, 0x10, 13, 1),
+	PIN_FIELD_BASE(32, 32, 6, 0x00b0, 0x10, 11, 1),
+	PIN_FIELD_BASE(36, 36, 8, 0x00d0, 0x10, 0, 1),
+	PIN_FIELD_BASE(37, 37, 8, 0x00d0, 0x10, 1, 1),
+	PIN_FIELD_BASE(38, 38, 8, 0x00d0, 0x10, 2, 1),
+	PIN_FIELD_BASE(39, 39, 8, 0x00d0, 0x10, 3, 1),
+	PIN_FIELD_BASE(40, 40, 8, 0x00d0, 0x10, 4, 1),
+	PIN_FIELD_BASE(41, 41, 4, 0x0090, 0x10, 20, 1),
+	PIN_FIELD_BASE(42, 42, 4, 0x0090, 0x10, 17, 1),
+	PIN_FIELD_BASE(43, 43, 4, 0x0090, 0x10, 19, 1),
+	PIN_FIELD_BASE(44, 44, 4, 0x0090, 0x10, 21, 1),
+	PIN_FIELD_BASE(45, 45, 4, 0x0090, 0x10, 18, 1),
+	PIN_FIELD_BASE(46, 46, 4, 0x0090, 0x10, 22, 1),
+	PIN_FIELD_BASE(47, 47, 4, 0x0090, 0x10, 23, 1),
+	PIN_FIELD_BASE(48, 48, 3, 0x00b0, 0x10, 25, 1),
+	PIN_FIELD_BASE(49, 49, 3, 0x00b0, 0x10, 23, 1),
+	PIN_FIELD_BASE(50, 50, 3, 0x00b0, 0x10, 26, 1),
+	PIN_FIELD_BASE(51, 51, 3, 0x00b0, 0x10, 24, 1),
+	PIN_FIELD_BASE(52, 52, 3, 0x00b0, 0x10, 17, 1),
+	PIN_FIELD_BASE(53, 53, 3, 0x00b0, 0x10, 18, 1),
+	PIN_FIELD_BASE(54, 54, 3, 0x00b0, 0x10, 15, 1),
+	PIN_FIELD_BASE(55, 55, 3, 0x00b0, 0x10, 16, 1),
+	PIN_FIELD_BASE(56, 56, 5, 0x0080, 0x10, 8, 1),
+	PIN_FIELD_BASE(57, 57, 5, 0x0080, 0x10, 9, 1),
+	PIN_FIELD_BASE(58, 58, 3, 0x00b0, 0x10, 22, 1),
+	PIN_FIELD_BASE(59, 59, 3, 0x00b0, 0x10, 21, 1),
+	PIN_FIELD_BASE(60, 60, 8, 0x00d0, 0x10, 21, 1),
+	PIN_FIELD_BASE(61, 61, 8, 0x00d0, 0x10, 22, 1),
+	PIN_FIELD_BASE(62, 62, 8, 0x00d0, 0x10, 24, 1),
+	PIN_FIELD_BASE(63, 63, 8, 0x00d0, 0x10, 23, 1),
+	PIN_FIELD_BASE(64, 64, 8, 0x00d0, 0x10, 25, 1),
+	PIN_FIELD_BASE(65, 65, 8, 0x00d0, 0x10, 26, 1),
+	PIN_FIELD_BASE(66, 66, 8, 0x00d0, 0x10, 28, 1),
+	PIN_FIELD_BASE(67, 67, 8, 0x00d0, 0x10, 27, 1),
+	PIN_FIELD_BASE(68, 68, 5, 0x0080, 0x10, 3, 1),
+	PIN_FIELD_BASE(69, 69, 5, 0x0080, 0x10, 4, 1),
+	PIN_FIELD_BASE(70, 70, 5, 0x0080, 0x10, 6, 1),
+	PIN_FIELD_BASE(71, 71, 5, 0x0080, 0x10, 5, 1),
+	PIN_FIELD_BASE(72, 72, 5, 0x0080, 0x10, 10, 1),
+	PIN_FIELD_BASE(73, 73, 5, 0x0080, 0x10, 11, 1),
+	PIN_FIELD_BASE(74, 74, 5, 0x0080, 0x10, 13, 1),
+	PIN_FIELD_BASE(75, 75, 5, 0x0080, 0x10, 12, 1),
+	PIN_FIELD_BASE(76, 76, 5, 0x0080, 0x10, 0, 1),
+	PIN_FIELD_BASE(89, 89, 4, 0x0090, 0x10, 9, 1),
+	PIN_FIELD_BASE(90, 90, 4, 0x0090, 0x10, 24, 1),
+	PIN_FIELD_BASE(91, 91, 4, 0x0090, 0x10, 8, 1),
+	PIN_FIELD_BASE(92, 92, 8, 0x00d0, 0x10, 5, 1),
+	PIN_FIELD_BASE(93, 93, 8, 0x00d0, 0x10, 6, 1),
+	PIN_FIELD_BASE(94, 94, 8, 0x00d0, 0x10, 7, 1),
+	PIN_FIELD_BASE(95, 95, 8, 0x00d0, 0x10, 8, 1),
+	PIN_FIELD_BASE(96, 96, 8, 0x00d0, 0x10, 9, 1),
+	PIN_FIELD_BASE(99, 99, 1, 0x00c0, 0x10, 0, 1),
+	PIN_FIELD_BASE(100, 100, 1, 0x00c0, 0x10, 1, 1),
+	PIN_FIELD_BASE(101, 101, 1, 0x00c0, 0x10, 10, 1),
+	PIN_FIELD_BASE(102, 102, 1, 0x00c0, 0x10, 11, 1),
+	PIN_FIELD_BASE(103, 103, 1, 0x00c0, 0x10, 12, 1),
+	PIN_FIELD_BASE(104, 104, 1, 0x00c0, 0x10, 13, 1),
+	PIN_FIELD_BASE(105, 105, 1, 0x00c0, 0x10, 14, 1),
+	PIN_FIELD_BASE(106, 106, 1, 0x00c0, 0x10, 15, 1),
+	PIN_FIELD_BASE(107, 107, 1, 0x00c0, 0x10, 16, 1),
+	PIN_FIELD_BASE(108, 108, 1, 0x00c0, 0x10, 17, 1),
+	PIN_FIELD_BASE(109, 109, 1, 0x00c0, 0x10, 2, 1),
+	PIN_FIELD_BASE(110, 110, 1, 0x00c0, 0x10, 3, 1),
+	PIN_FIELD_BASE(111, 111, 1, 0x00c0, 0x10, 4, 1),
+	PIN_FIELD_BASE(112, 112, 1, 0x00c0, 0x10, 5, 1),
+	PIN_FIELD_BASE(113, 113, 1, 0x00c0, 0x10, 6, 1),
+	PIN_FIELD_BASE(114, 114, 1, 0x00c0, 0x10, 7, 1),
+	PIN_FIELD_BASE(115, 115, 1, 0x00c0, 0x10, 8, 1),
+	PIN_FIELD_BASE(116, 116, 1, 0x00c0, 0x10, 9, 1),
+	PIN_FIELD_BASE(125, 125, 8, 0x00d0, 0x10, 20, 1),
+	PIN_FIELD_BASE(126, 126, 8, 0x00d0, 0x10, 29, 1),
+	PIN_FIELD_BASE(127, 127, 8, 0x00d0, 0x10, 30, 1),
+	PIN_FIELD_BASE(128, 128, 8, 0x00d0, 0x10, 31, 1),
+	PIN_FIELD_BASE(129, 129, 8, 0x00d0, 0x10, 10, 1),
+	PIN_FIELD_BASE(130, 130, 8, 0x00d0, 0x10, 13, 1),
+	PIN_FIELD_BASE(131, 131, 6, 0x00b0, 0x10, 14, 1),
+	PIN_FIELD_BASE(132, 132, 6, 0x00b0, 0x10, 17, 1),
+	PIN_FIELD_BASE(133, 133, 8, 0x00d0, 0x10, 11, 1),
+	PIN_FIELD_BASE(134, 134, 8, 0x00d0, 0x10, 14, 1),
+	PIN_FIELD_BASE(135, 135, 6, 0x00b0, 0x10, 15, 1),
+	PIN_FIELD_BASE(136, 136, 6, 0x00b0, 0x10, 18, 1),
+	PIN_FIELD_BASE(137, 137, 6, 0x00b0, 0x10, 16, 1),
+	PIN_FIELD_BASE(138, 138, 6, 0x00b0, 0x10, 19, 1),
+	PIN_FIELD_BASE(139, 139, 6, 0x00b0, 0x10, 0, 1),
+	PIN_FIELD_BASE(140, 140, 6, 0x00b0, 0x10, 2, 1),
+	PIN_FIELD_BASE(141, 141, 6, 0x00b0, 0x10, 1, 1),
+	PIN_FIELD_BASE(142, 142, 6, 0x00b0, 0x10, 3, 1),
+	PIN_FIELD_BASE(143, 143, 8, 0x00d0, 0x10, 12, 1),
+	PIN_FIELD_BASE(144, 144, 8, 0x00d0, 0x10, 15, 1),
+	PIN_FIELD_BASE(145, 145, 5, 0x0080, 0x10, 2, 1),
+	PIN_FIELD_BASE(146, 146, 5, 0x0080, 0x10, 7, 1),
+	PIN_FIELD_BASE(147, 147, 3, 0x00b0, 0x10, 19, 1),
+	PIN_FIELD_BASE(148, 148, 3, 0x00b0, 0x10, 20, 1),
+	PIN_FIELD_BASE(149, 149, 8, 0x00d0, 0x10, 16, 1),
+	PIN_FIELD_BASE(150, 150, 8, 0x00d0, 0x10, 17, 1),
+	PIN_FIELD_BASE(151, 151, 8, 0x00d0, 0x10, 18, 1),
+	PIN_FIELD_BASE(152, 152, 8, 0x00d0, 0x10, 19, 1),
+	PIN_FIELD_BASE(156, 156, 9, 0x00a0, 0x10, 0, 1),
+	PIN_FIELD_BASE(157, 157, 9, 0x00a0, 0x10, 1, 1),
+	PIN_FIELD_BASE(158, 158, 9, 0x00a0, 0x10, 2, 1),
+	PIN_FIELD_BASE(159, 159, 9, 0x00a0, 0x10, 3, 1),
+	PIN_FIELD_BASE(160, 160, 4, 0x0090, 0x10, 26, 1),
+	PIN_FIELD_BASE(161, 161, 4, 0x0090, 0x10, 25, 1),
+	PIN_FIELD_BASE(162, 162, 4, 0x0090, 0x10, 30, 1),
+	PIN_FIELD_BASE(163, 163, 4, 0x0090, 0x10, 29, 1),
+	PIN_FIELD_BASE(164, 164, 4, 0x0090, 0x10, 0, 1),
+	PIN_FIELD_BASE(165, 165, 4, 0x0090, 0x10, 7, 1),
+	PIN_FIELD_BASE(166, 166, 4, 0x0090, 0x10, 3, 1),
+	PIN_FIELD_BASE(167, 167, 4, 0x0090, 0x10, 4, 1),
+	PIN_FIELD_BASE(168, 168, 4, 0x0090, 0x10, 5, 1),
+	PIN_FIELD_BASE(169, 169, 4, 0x0090, 0x10, 6, 1),
+	PIN_FIELD_BASE(170, 170, 4, 0x0090, 0x10, 1, 1),
+	PIN_FIELD_BASE(171, 171, 4, 0x0090, 0x10, 2, 1),
+};
+
+static const struct mtk_pin_field_calc mt6878_pin_pd_range[] = {
+	PIN_FIELD_BASE(0, 0, 3, 0x00a0, 0x10, 9, 1),
+	PIN_FIELD_BASE(1, 1, 3, 0x00a0, 0x10, 10, 1),
+	PIN_FIELD_BASE(2, 2, 3, 0x00a0, 0x10, 11, 1),
+	PIN_FIELD_BASE(3, 3, 3, 0x00a0, 0x10, 12, 1),
+	PIN_FIELD_BASE(4, 4, 3, 0x00a0, 0x10, 13, 1),
+	PIN_FIELD_BASE(5, 5, 3, 0x00a0, 0x10, 14, 1),
+	PIN_FIELD_BASE(6, 6, 4, 0x0080, 0x10, 13, 1),
+	PIN_FIELD_BASE(7, 7, 4, 0x0080, 0x10, 14, 1),
+	PIN_FIELD_BASE(8, 8, 4, 0x0080, 0x10, 15, 1),
+	PIN_FIELD_BASE(9, 9, 4, 0x0080, 0x10, 16, 1),
+	PIN_FIELD_BASE(10, 10, 4, 0x0080, 0x10, 10, 1),
+	PIN_FIELD_BASE(11, 11, 4, 0x0080, 0x10, 11, 1),
+	PIN_FIELD_BASE(12, 12, 4, 0x0080, 0x10, 12, 1),
+	PIN_FIELD_BASE(13, 13, 6, 0x00a0, 0x10, 4, 1),
+	PIN_FIELD_BASE(14, 14, 6, 0x00a0, 0x10, 5, 1),
+	PIN_FIELD_BASE(15, 15, 6, 0x00a0, 0x10, 6, 1),
+	PIN_FIELD_BASE(16, 16, 6, 0x00a0, 0x10, 7, 1),
+	PIN_FIELD_BASE(17, 17, 6, 0x00a0, 0x10, 8, 1),
+	PIN_FIELD_BASE(18, 18, 6, 0x00a0, 0x10, 9, 1),
+	PIN_FIELD_BASE(19, 19, 3, 0x00a0, 0x10, 0, 1),
+	PIN_FIELD_BASE(20, 20, 3, 0x00a0, 0x10, 1, 1),
+	PIN_FIELD_BASE(21, 21, 3, 0x00a0, 0x10, 2, 1),
+	PIN_FIELD_BASE(22, 22, 3, 0x00a0, 0x10, 3, 1),
+	PIN_FIELD_BASE(23, 23, 3, 0x00a0, 0x10, 4, 1),
+	PIN_FIELD_BASE(24, 24, 5, 0x0070, 0x10, 1, 1),
+	PIN_FIELD_BASE(25, 25, 3, 0x00a0, 0x10, 5, 1),
+	PIN_FIELD_BASE(26, 26, 3, 0x00a0, 0x10, 6, 1),
+	PIN_FIELD_BASE(27, 27, 3, 0x00a0, 0x10, 7, 1),
+	PIN_FIELD_BASE(28, 28, 3, 0x00a0, 0x10, 8, 1),
+	PIN_FIELD_BASE(29, 29, 6, 0x00a0, 0x10, 10, 1),
+	PIN_FIELD_BASE(30, 30, 6, 0x00a0, 0x10, 12, 1),
+	PIN_FIELD_BASE(31, 31, 6, 0x00a0, 0x10, 13, 1),
+	PIN_FIELD_BASE(32, 32, 6, 0x00a0, 0x10, 11, 1),
+	PIN_FIELD_BASE(36, 36, 8, 0x00c0, 0x10, 0, 1),
+	PIN_FIELD_BASE(37, 37, 8, 0x00c0, 0x10, 1, 1),
+	PIN_FIELD_BASE(38, 38, 8, 0x00c0, 0x10, 2, 1),
+	PIN_FIELD_BASE(39, 39, 8, 0x00c0, 0x10, 3, 1),
+	PIN_FIELD_BASE(40, 40, 8, 0x00c0, 0x10, 4, 1),
+	PIN_FIELD_BASE(41, 41, 4, 0x0080, 0x10, 20, 1),
+	PIN_FIELD_BASE(42, 42, 4, 0x0080, 0x10, 17, 1),
+	PIN_FIELD_BASE(43, 43, 4, 0x0080, 0x10, 19, 1),
+	PIN_FIELD_BASE(44, 44, 4, 0x0080, 0x10, 21, 1),
+	PIN_FIELD_BASE(45, 45, 4, 0x0080, 0x10, 18, 1),
+	PIN_FIELD_BASE(46, 46, 4, 0x0080, 0x10, 22, 1),
+	PIN_FIELD_BASE(47, 47, 4, 0x0080, 0x10, 23, 1),
+	PIN_FIELD_BASE(48, 48, 3, 0x00a0, 0x10, 25, 1),
+	PIN_FIELD_BASE(49, 49, 3, 0x00a0, 0x10, 23, 1),
+	PIN_FIELD_BASE(50, 50, 3, 0x00a0, 0x10, 26, 1),
+	PIN_FIELD_BASE(51, 51, 3, 0x00a0, 0x10, 24, 1),
+	PIN_FIELD_BASE(52, 52, 3, 0x00a0, 0x10, 17, 1),
+	PIN_FIELD_BASE(53, 53, 3, 0x00a0, 0x10, 18, 1),
+	PIN_FIELD_BASE(54, 54, 3, 0x00a0, 0x10, 15, 1),
+	PIN_FIELD_BASE(55, 55, 3, 0x00a0, 0x10, 16, 1),
+	PIN_FIELD_BASE(56, 56, 5, 0x0070, 0x10, 8, 1),
+	PIN_FIELD_BASE(57, 57, 5, 0x0070, 0x10, 9, 1),
+	PIN_FIELD_BASE(58, 58, 3, 0x00a0, 0x10, 22, 1),
+	PIN_FIELD_BASE(59, 59, 3, 0x00a0, 0x10, 21, 1),
+	PIN_FIELD_BASE(60, 60, 8, 0x00c0, 0x10, 21, 1),
+	PIN_FIELD_BASE(61, 61, 8, 0x00c0, 0x10, 22, 1),
+	PIN_FIELD_BASE(62, 62, 8, 0x00c0, 0x10, 24, 1),
+	PIN_FIELD_BASE(63, 63, 8, 0x00c0, 0x10, 23, 1),
+	PIN_FIELD_BASE(64, 64, 8, 0x00c0, 0x10, 25, 1),
+	PIN_FIELD_BASE(65, 65, 8, 0x00c0, 0x10, 26, 1),
+	PIN_FIELD_BASE(66, 66, 8, 0x00c0, 0x10, 28, 1),
+	PIN_FIELD_BASE(67, 67, 8, 0x00c0, 0x10, 27, 1),
+	PIN_FIELD_BASE(68, 68, 5, 0x0070, 0x10, 3, 1),
+	PIN_FIELD_BASE(69, 69, 5, 0x0070, 0x10, 4, 1),
+	PIN_FIELD_BASE(70, 70, 5, 0x0070, 0x10, 6, 1),
+	PIN_FIELD_BASE(71, 71, 5, 0x0070, 0x10, 5, 1),
+	PIN_FIELD_BASE(72, 72, 5, 0x0070, 0x10, 10, 1),
+	PIN_FIELD_BASE(73, 73, 5, 0x0070, 0x10, 11, 1),
+	PIN_FIELD_BASE(74, 74, 5, 0x0070, 0x10, 13, 1),
+	PIN_FIELD_BASE(75, 75, 5, 0x0070, 0x10, 12, 1),
+	PIN_FIELD_BASE(76, 76, 5, 0x0070, 0x10, 0, 1),
+	PIN_FIELD_BASE(89, 89, 4, 0x0080, 0x10, 9, 1),
+	PIN_FIELD_BASE(90, 90, 4, 0x0080, 0x10, 24, 1),
+	PIN_FIELD_BASE(91, 91, 4, 0x0080, 0x10, 8, 1),
+	PIN_FIELD_BASE(92, 92, 8, 0x00c0, 0x10, 5, 1),
+	PIN_FIELD_BASE(93, 93, 8, 0x00c0, 0x10, 6, 1),
+	PIN_FIELD_BASE(94, 94, 8, 0x00c0, 0x10, 7, 1),
+	PIN_FIELD_BASE(95, 95, 8, 0x00c0, 0x10, 8, 1),
+	PIN_FIELD_BASE(96, 96, 8, 0x00c0, 0x10, 9, 1),
+	PIN_FIELD_BASE(99, 99, 1, 0x00a0, 0x10, 0, 1),
+	PIN_FIELD_BASE(100, 100, 1, 0x00a0, 0x10, 1, 1),
+	PIN_FIELD_BASE(101, 101, 1, 0x00a0, 0x10, 10, 1),
+	PIN_FIELD_BASE(102, 102, 1, 0x00a0, 0x10, 11, 1),
+	PIN_FIELD_BASE(103, 103, 1, 0x00a0, 0x10, 12, 1),
+	PIN_FIELD_BASE(104, 104, 1, 0x00a0, 0x10, 13, 1),
+	PIN_FIELD_BASE(105, 105, 1, 0x00a0, 0x10, 14, 1),
+	PIN_FIELD_BASE(106, 106, 1, 0x00a0, 0x10, 15, 1),
+	PIN_FIELD_BASE(107, 107, 1, 0x00a0, 0x10, 16, 1),
+	PIN_FIELD_BASE(108, 108, 1, 0x00a0, 0x10, 17, 1),
+	PIN_FIELD_BASE(109, 109, 1, 0x00a0, 0x10, 2, 1),
+	PIN_FIELD_BASE(110, 110, 1, 0x00a0, 0x10, 3, 1),
+	PIN_FIELD_BASE(111, 111, 1, 0x00a0, 0x10, 4, 1),
+	PIN_FIELD_BASE(112, 112, 1, 0x00a0, 0x10, 5, 1),
+	PIN_FIELD_BASE(113, 113, 1, 0x00a0, 0x10, 6, 1),
+	PIN_FIELD_BASE(114, 114, 1, 0x00a0, 0x10, 7, 1),
+	PIN_FIELD_BASE(115, 115, 1, 0x00a0, 0x10, 8, 1),
+	PIN_FIELD_BASE(116, 116, 1, 0x00a0, 0x10, 9, 1),
+	PIN_FIELD_BASE(125, 125, 8, 0x00c0, 0x10, 20, 1),
+	PIN_FIELD_BASE(126, 126, 8, 0x00c0, 0x10, 29, 1),
+	PIN_FIELD_BASE(127, 127, 8, 0x00c0, 0x10, 30, 1),
+	PIN_FIELD_BASE(128, 128, 8, 0x00c0, 0x10, 31, 1),
+	PIN_FIELD_BASE(129, 129, 8, 0x00c0, 0x10, 10, 1),
+	PIN_FIELD_BASE(130, 130, 8, 0x00c0, 0x10, 13, 1),
+	PIN_FIELD_BASE(131, 131, 6, 0x00a0, 0x10, 14, 1),
+	PIN_FIELD_BASE(132, 132, 6, 0x00a0, 0x10, 17, 1),
+	PIN_FIELD_BASE(133, 133, 8, 0x00c0, 0x10, 11, 1),
+	PIN_FIELD_BASE(134, 134, 8, 0x00c0, 0x10, 14, 1),
+	PIN_FIELD_BASE(135, 135, 6, 0x00a0, 0x10, 15, 1),
+	PIN_FIELD_BASE(136, 136, 6, 0x00a0, 0x10, 18, 1),
+	PIN_FIELD_BASE(137, 137, 6, 0x00a0, 0x10, 16, 1),
+	PIN_FIELD_BASE(138, 138, 6, 0x00a0, 0x10, 19, 1),
+	PIN_FIELD_BASE(139, 139, 6, 0x00a0, 0x10, 0, 1),
+	PIN_FIELD_BASE(140, 140, 6, 0x00a0, 0x10, 2, 1),
+	PIN_FIELD_BASE(141, 141, 6, 0x00a0, 0x10, 1, 1),
+	PIN_FIELD_BASE(142, 142, 6, 0x00a0, 0x10, 3, 1),
+	PIN_FIELD_BASE(143, 143, 8, 0x00c0, 0x10, 12, 1),
+	PIN_FIELD_BASE(144, 144, 8, 0x00c0, 0x10, 15, 1),
+	PIN_FIELD_BASE(145, 145, 5, 0x0070, 0x10, 2, 1),
+	PIN_FIELD_BASE(146, 146, 5, 0x0070, 0x10, 7, 1),
+	PIN_FIELD_BASE(147, 147, 3, 0x00a0, 0x10, 19, 1),
+	PIN_FIELD_BASE(148, 148, 3, 0x00a0, 0x10, 20, 1),
+	PIN_FIELD_BASE(149, 149, 8, 0x00c0, 0x10, 16, 1),
+	PIN_FIELD_BASE(150, 150, 8, 0x00c0, 0x10, 17, 1),
+	PIN_FIELD_BASE(151, 151, 8, 0x00c0, 0x10, 18, 1),
+	PIN_FIELD_BASE(152, 152, 8, 0x00c0, 0x10, 19, 1),
+	PIN_FIELD_BASE(156, 156, 9, 0x0080, 0x10, 0, 1),
+	PIN_FIELD_BASE(157, 157, 9, 0x0080, 0x10, 1, 1),
+	PIN_FIELD_BASE(158, 158, 9, 0x0080, 0x10, 2, 1),
+	PIN_FIELD_BASE(159, 159, 9, 0x0080, 0x10, 3, 1),
+	PIN_FIELD_BASE(160, 160, 4, 0x0080, 0x10, 26, 1),
+	PIN_FIELD_BASE(161, 161, 4, 0x0080, 0x10, 25, 1),
+	PIN_FIELD_BASE(162, 162, 4, 0x0080, 0x10, 30, 1),
+	PIN_FIELD_BASE(163, 163, 4, 0x0080, 0x10, 29, 1),
+	PIN_FIELD_BASE(164, 164, 4, 0x0080, 0x10, 0, 1),
+	PIN_FIELD_BASE(165, 165, 4, 0x0080, 0x10, 7, 1),
+	PIN_FIELD_BASE(166, 166, 4, 0x0080, 0x10, 3, 1),
+	PIN_FIELD_BASE(167, 167, 4, 0x0080, 0x10, 4, 1),
+	PIN_FIELD_BASE(168, 168, 4, 0x0080, 0x10, 5, 1),
+	PIN_FIELD_BASE(169, 169, 4, 0x0080, 0x10, 6, 1),
+	PIN_FIELD_BASE(170, 170, 4, 0x0080, 0x10, 1, 1),
+	PIN_FIELD_BASE(171, 171, 4, 0x0080, 0x10, 2, 1),
+};
+
+static const struct mtk_pin_field_calc mt6878_pin_pupd_range[] = {
+	PIN_FIELD_BASE(33, 33, 9, 0x0090, 0x10, 0, 1),
+	PIN_FIELD_BASE(34, 34, 9, 0x0090, 0x10, 1, 1),
+	PIN_FIELD_BASE(35, 35, 9, 0x0090, 0x10, 2, 1),
+	PIN_FIELD_BASE(77, 77, 2, 0x0070, 0x10, 0, 1),
+	PIN_FIELD_BASE(78, 78, 2, 0x0070, 0x10, 1, 1),
+	PIN_FIELD_BASE(79, 79, 2, 0x0070, 0x10, 2, 1),
+	PIN_FIELD_BASE(80, 80, 2, 0x0070, 0x10, 3, 1),
+	PIN_FIELD_BASE(81, 81, 2, 0x0070, 0x10, 4, 1),
+	PIN_FIELD_BASE(82, 82, 2, 0x0070, 0x10, 5, 1),
+	PIN_FIELD_BASE(83, 83, 2, 0x0070, 0x10, 9, 1),
+	PIN_FIELD_BASE(84, 84, 2, 0x0070, 0x10, 11, 1),
+	PIN_FIELD_BASE(85, 85, 2, 0x0070, 0x10, 10, 1),
+	PIN_FIELD_BASE(86, 86, 2, 0x0070, 0x10, 12, 1),
+	PIN_FIELD_BASE(87, 87, 2, 0x0070, 0x10, 14, 1),
+	PIN_FIELD_BASE(88, 88, 2, 0x0070, 0x10, 13, 1),
+	PIN_FIELD_BASE(97, 97, 1, 0x00b0, 0x10, 1, 1),
+	PIN_FIELD_BASE(98, 98, 1, 0x00b0, 0x10, 0, 1),
+	PIN_FIELD_BASE(117, 117, 1, 0x00b0, 0x10, 2, 1),
+	PIN_FIELD_BASE(118, 118, 1, 0x00b0, 0x10, 3, 1),
+	PIN_FIELD_BASE(119, 119, 1, 0x00b0, 0x10, 4, 1),
+	PIN_FIELD_BASE(120, 120, 1, 0x00b0, 0x10, 5, 1),
+	PIN_FIELD_BASE(121, 121, 1, 0x00b0, 0x10, 6, 1),
+	PIN_FIELD_BASE(122, 122, 1, 0x00b0, 0x10, 7, 1),
+	PIN_FIELD_BASE(123, 123, 1, 0x00b0, 0x10, 8, 1),
+	PIN_FIELD_BASE(124, 124, 1, 0x00b0, 0x10, 9, 1),
+	PIN_FIELD_BASE(153, 153, 2, 0x0070, 0x10, 6, 1),
+	PIN_FIELD_BASE(154, 154, 2, 0x0070, 0x10, 7, 1),
+	PIN_FIELD_BASE(155, 155, 2, 0x0070, 0x10, 8, 1),
+	PIN_FIELD_BASE(172, 172, 9, 0x0090, 0x10, 7, 1),
+	PIN_FIELD_BASE(173, 173, 9, 0x0090, 0x10, 8, 1),
+	PIN_FIELD_BASE(174, 174, 9, 0x0090, 0x10, 3, 1),
+	PIN_FIELD_BASE(175, 175, 9, 0x0090, 0x10, 4, 1),
+	PIN_FIELD_BASE(176, 176, 9, 0x0090, 0x10, 5, 1),
+	PIN_FIELD_BASE(177, 177, 9, 0x0090, 0x10, 9, 1),
+	PIN_FIELD_BASE(178, 178, 9, 0x0090, 0x10, 10, 1),
+	PIN_FIELD_BASE(179, 179, 9, 0x0090, 0x10, 11, 1),
+	PIN_FIELD_BASE(180, 180, 9, 0x0090, 0x10, 12, 1),
+	PIN_FIELD_BASE(181, 181, 9, 0x0090, 0x10, 13, 1),
+	PIN_FIELD_BASE(182, 182, 9, 0x0090, 0x10, 14, 1),
+	PIN_FIELD_BASE(183, 183, 9, 0x0090, 0x10, 6, 1),
+	PIN_FIELD_BASE(184, 184, 7, 0x0070, 0x10, 10, 1),
+	PIN_FIELD_BASE(185, 185, 7, 0x0070, 0x10, 0, 1),
+	PIN_FIELD_BASE(186, 186, 7, 0x0070, 0x10, 1, 1),
+	PIN_FIELD_BASE(187, 187, 7, 0x0070, 0x10, 11, 1),
+	PIN_FIELD_BASE(188, 188, 7, 0x0070, 0x10, 2, 1),
+	PIN_FIELD_BASE(189, 189, 7, 0x0070, 0x10, 3, 1),
+	PIN_FIELD_BASE(190, 190, 7, 0x0070, 0x10, 4, 1),
+	PIN_FIELD_BASE(191, 191, 7, 0x0070, 0x10, 5, 1),
+	PIN_FIELD_BASE(192, 192, 7, 0x0070, 0x10, 6, 1),
+	PIN_FIELD_BASE(193, 193, 7, 0x0070, 0x10, 7, 1),
+	PIN_FIELD_BASE(194, 194, 7, 0x0070, 0x10, 8, 1),
+	PIN_FIELD_BASE(195, 195, 7, 0x0070, 0x10, 9, 1),
+};
+
+static const struct mtk_pin_field_calc mt6878_pin_r0_range[] = {
+	PIN_FIELD_BASE(33, 33, 9, 0x00b0, 0x10, 0, 1),
+	PIN_FIELD_BASE(34, 34, 9, 0x00b0, 0x10, 1, 1),
+	PIN_FIELD_BASE(35, 35, 9, 0x00b0, 0x10, 2, 1),
+	PIN_FIELD_BASE(77, 77, 2, 0x0080, 0x10, 0, 1),
+	PIN_FIELD_BASE(78, 78, 2, 0x0080, 0x10, 1, 1),
+	PIN_FIELD_BASE(79, 79, 2, 0x0080, 0x10, 2, 1),
+	PIN_FIELD_BASE(80, 80, 2, 0x0080, 0x10, 3, 1),
+	PIN_FIELD_BASE(81, 81, 2, 0x0080, 0x10, 4, 1),
+	PIN_FIELD_BASE(82, 82, 2, 0x0080, 0x10, 5, 1),
+	PIN_FIELD_BASE(83, 83, 2, 0x0080, 0x10, 9, 1),
+	PIN_FIELD_BASE(84, 84, 2, 0x0080, 0x10, 11, 1),
+	PIN_FIELD_BASE(85, 85, 2, 0x0080, 0x10, 10, 1),
+	PIN_FIELD_BASE(86, 86, 2, 0x0080, 0x10, 12, 1),
+	PIN_FIELD_BASE(87, 87, 2, 0x0080, 0x10, 14, 1),
+	PIN_FIELD_BASE(88, 88, 2, 0x0080, 0x10, 13, 1),
+	PIN_FIELD_BASE(97, 97, 1, 0x00d0, 0x10, 1, 1),
+	PIN_FIELD_BASE(98, 98, 1, 0x00d0, 0x10, 0, 1),
+	PIN_FIELD_BASE(117, 117, 1, 0x00d0, 0x10, 2, 1),
+	PIN_FIELD_BASE(118, 118, 1, 0x00d0, 0x10, 3, 1),
+	PIN_FIELD_BASE(119, 119, 1, 0x00d0, 0x10, 4, 1),
+	PIN_FIELD_BASE(120, 120, 1, 0x00d0, 0x10, 5, 1),
+	PIN_FIELD_BASE(121, 121, 1, 0x00d0, 0x10, 6, 1),
+	PIN_FIELD_BASE(122, 122, 1, 0x00d0, 0x10, 7, 1),
+	PIN_FIELD_BASE(123, 123, 1, 0x00d0, 0x10, 8, 1),
+	PIN_FIELD_BASE(124, 124, 1, 0x00d0, 0x10, 9, 1),
+	PIN_FIELD_BASE(153, 153, 2, 0x0080, 0x10, 6, 1),
+	PIN_FIELD_BASE(154, 154, 2, 0x0080, 0x10, 7, 1),
+	PIN_FIELD_BASE(155, 155, 2, 0x0080, 0x10, 8, 1),
+	PIN_FIELD_BASE(172, 172, 9, 0x00b0, 0x10, 7, 1),
+	PIN_FIELD_BASE(173, 173, 9, 0x00b0, 0x10, 8, 1),
+	PIN_FIELD_BASE(174, 174, 9, 0x00b0, 0x10, 3, 1),
+	PIN_FIELD_BASE(175, 175, 9, 0x00b0, 0x10, 4, 1),
+	PIN_FIELD_BASE(176, 176, 9, 0x00b0, 0x10, 5, 1),
+	PIN_FIELD_BASE(177, 177, 9, 0x00b0, 0x10, 9, 1),
+	PIN_FIELD_BASE(178, 178, 9, 0x00b0, 0x10, 10, 1),
+	PIN_FIELD_BASE(179, 179, 9, 0x00b0, 0x10, 11, 1),
+	PIN_FIELD_BASE(180, 180, 9, 0x00b0, 0x10, 12, 1),
+	PIN_FIELD_BASE(181, 181, 9, 0x00b0, 0x10, 13, 1),
+	PIN_FIELD_BASE(182, 182, 9, 0x00b0, 0x10, 14, 1),
+	PIN_FIELD_BASE(183, 183, 9, 0x00b0, 0x10, 6, 1),
+	PIN_FIELD_BASE(184, 184, 7, 0x0080, 0x10, 10, 1),
+	PIN_FIELD_BASE(185, 185, 7, 0x0080, 0x10, 0, 1),
+	PIN_FIELD_BASE(186, 186, 7, 0x0080, 0x10, 1, 1),
+	PIN_FIELD_BASE(187, 187, 7, 0x0080, 0x10, 11, 1),
+	PIN_FIELD_BASE(188, 188, 7, 0x0080, 0x10, 2, 1),
+	PIN_FIELD_BASE(189, 189, 7, 0x0080, 0x10, 3, 1),
+	PIN_FIELD_BASE(190, 190, 7, 0x0080, 0x10, 4, 1),
+	PIN_FIELD_BASE(191, 191, 7, 0x0080, 0x10, 5, 1),
+	PIN_FIELD_BASE(192, 192, 7, 0x0080, 0x10, 6, 1),
+	PIN_FIELD_BASE(193, 193, 7, 0x0080, 0x10, 7, 1),
+	PIN_FIELD_BASE(194, 194, 7, 0x0080, 0x10, 8, 1),
+	PIN_FIELD_BASE(195, 195, 7, 0x0080, 0x10, 9, 1),
+};
+
+static const struct mtk_pin_field_calc mt6878_pin_r1_range[] = {
+	PIN_FIELD_BASE(33, 33, 9, 0x00c0, 0x10, 0, 1),
+	PIN_FIELD_BASE(34, 34, 9, 0x00c0, 0x10, 1, 1),
+	PIN_FIELD_BASE(35, 35, 9, 0x00c0, 0x10, 2, 1),
+	PIN_FIELD_BASE(77, 77, 2, 0x0090, 0x10, 0, 1),
+	PIN_FIELD_BASE(78, 78, 2, 0x0090, 0x10, 1, 1),
+	PIN_FIELD_BASE(79, 79, 2, 0x0090, 0x10, 2, 1),
+	PIN_FIELD_BASE(80, 80, 2, 0x0090, 0x10, 3, 1),
+	PIN_FIELD_BASE(81, 81, 2, 0x0090, 0x10, 4, 1),
+	PIN_FIELD_BASE(82, 82, 2, 0x0090, 0x10, 5, 1),
+	PIN_FIELD_BASE(83, 83, 2, 0x0090, 0x10, 9, 1),
+	PIN_FIELD_BASE(84, 84, 2, 0x0090, 0x10, 11, 1),
+	PIN_FIELD_BASE(85, 85, 2, 0x0090, 0x10, 10, 1),
+	PIN_FIELD_BASE(86, 86, 2, 0x0090, 0x10, 12, 1),
+	PIN_FIELD_BASE(87, 87, 2, 0x0090, 0x10, 14, 1),
+	PIN_FIELD_BASE(88, 88, 2, 0x0090, 0x10, 13, 1),
+	PIN_FIELD_BASE(97, 97, 1, 0x00e0, 0x10, 1, 1),
+	PIN_FIELD_BASE(98, 98, 1, 0x00e0, 0x10, 0, 1),
+	PIN_FIELD_BASE(117, 117, 1, 0x00e0, 0x10, 2, 1),
+	PIN_FIELD_BASE(118, 118, 1, 0x00e0, 0x10, 3, 1),
+	PIN_FIELD_BASE(119, 119, 1, 0x00e0, 0x10, 4, 1),
+	PIN_FIELD_BASE(120, 120, 1, 0x00e0, 0x10, 5, 1),
+	PIN_FIELD_BASE(121, 121, 1, 0x00e0, 0x10, 6, 1),
+	PIN_FIELD_BASE(122, 122, 1, 0x00e0, 0x10, 7, 1),
+	PIN_FIELD_BASE(123, 123, 1, 0x00e0, 0x10, 8, 1),
+	PIN_FIELD_BASE(124, 124, 1, 0x00e0, 0x10, 9, 1),
+	PIN_FIELD_BASE(153, 153, 2, 0x0090, 0x10, 6, 1),
+	PIN_FIELD_BASE(154, 154, 2, 0x0090, 0x10, 7, 1),
+	PIN_FIELD_BASE(155, 155, 2, 0x0090, 0x10, 8, 1),
+	PIN_FIELD_BASE(172, 172, 9, 0x00c0, 0x10, 7, 1),
+	PIN_FIELD_BASE(173, 173, 9, 0x00c0, 0x10, 8, 1),
+	PIN_FIELD_BASE(174, 174, 9, 0x00c0, 0x10, 3, 1),
+	PIN_FIELD_BASE(175, 175, 9, 0x00c0, 0x10, 4, 1),
+	PIN_FIELD_BASE(176, 176, 9, 0x00c0, 0x10, 5, 1),
+	PIN_FIELD_BASE(177, 177, 9, 0x00c0, 0x10, 9, 1),
+	PIN_FIELD_BASE(178, 178, 9, 0x00c0, 0x10, 10, 1),
+	PIN_FIELD_BASE(179, 179, 9, 0x00c0, 0x10, 11, 1),
+	PIN_FIELD_BASE(180, 180, 9, 0x00c0, 0x10, 12, 1),
+	PIN_FIELD_BASE(181, 181, 9, 0x00c0, 0x10, 13, 1),
+	PIN_FIELD_BASE(182, 182, 9, 0x00c0, 0x10, 14, 1),
+	PIN_FIELD_BASE(183, 183, 9, 0x00c0, 0x10, 6, 1),
+	PIN_FIELD_BASE(184, 184, 7, 0x0090, 0x10, 10, 1),
+	PIN_FIELD_BASE(185, 185, 7, 0x0090, 0x10, 0, 1),
+	PIN_FIELD_BASE(186, 186, 7, 0x0090, 0x10, 1, 1),
+	PIN_FIELD_BASE(187, 187, 7, 0x0090, 0x10, 11, 1),
+	PIN_FIELD_BASE(188, 188, 7, 0x0090, 0x10, 2, 1),
+	PIN_FIELD_BASE(189, 189, 7, 0x0090, 0x10, 3, 1),
+	PIN_FIELD_BASE(190, 190, 7, 0x0090, 0x10, 4, 1),
+	PIN_FIELD_BASE(191, 191, 7, 0x0090, 0x10, 5, 1),
+	PIN_FIELD_BASE(192, 192, 7, 0x0090, 0x10, 6, 1),
+	PIN_FIELD_BASE(193, 193, 7, 0x0090, 0x10, 7, 1),
+	PIN_FIELD_BASE(194, 194, 7, 0x0090, 0x10, 8, 1),
+	PIN_FIELD_BASE(195, 195, 7, 0x0090, 0x10, 9, 1),
+};
+
+static const struct mtk_pin_field_calc mt6878_pin_drv_range[] = {
+	PIN_FIELD_BASE(0, 0, 3, 0x0010, 0x10, 21, 3),
+	PIN_FIELD_BASE(1, 1, 3, 0x0010, 0x10, 21, 3),
+	PIN_FIELD_BASE(2, 2, 3, 0x0000, 0x10, 27, 3),
+	PIN_FIELD_BASE(3, 3, 3, 0x0010, 0x10, 0, 3),
+	PIN_FIELD_BASE(4, 4, 3, 0x0010, 0x10, 3, 3),
+	PIN_FIELD_BASE(5, 5, 3, 0x0010, 0x10, 6, 3),
+	PIN_FIELD_BASE(6, 6, 4, 0x0000, 0x10, 15, 3),
+	PIN_FIELD_BASE(7, 7, 4, 0x0000, 0x10, 18, 3),
+	PIN_FIELD_BASE(8, 8, 4, 0x0000, 0x10, 21, 3),
+	PIN_FIELD_BASE(9, 9, 4, 0x0000, 0x10, 24, 3),
+	PIN_FIELD_BASE(10, 10, 4, 0x0000, 0x10, 6, 3),
+	PIN_FIELD_BASE(11, 11, 4, 0x0000, 0x10, 9, 3),
+	PIN_FIELD_BASE(12, 12, 4, 0x0000, 0x10, 12, 3),
+	PIN_FIELD_BASE(13, 13, 6, 0x0000, 0x10, 12, 3),
+	PIN_FIELD_BASE(14, 14, 6, 0x0000, 0x10, 15, 3),
+	PIN_FIELD_BASE(15, 15, 6, 0x0000, 0x10, 18, 3),
+	PIN_FIELD_BASE(16, 16, 6, 0x0000, 0x10, 21, 3),
+	PIN_FIELD_BASE(17, 17, 6, 0x0000, 0x10, 24, 3),
+	PIN_FIELD_BASE(18, 18, 6, 0x0010, 0x10, 6, 3),
+	PIN_FIELD_BASE(19, 19, 3, 0x0000, 0x10, 0, 3),
+	PIN_FIELD_BASE(20, 20, 3, 0x0000, 0x10, 3, 3),
+	PIN_FIELD_BASE(21, 21, 3, 0x0000, 0x10, 6, 3),
+	PIN_FIELD_BASE(22, 22, 3, 0x0000, 0x10, 9, 3),
+	PIN_FIELD_BASE(23, 23, 3, 0x0000, 0x10, 12, 3),
+	PIN_FIELD_BASE(24, 24, 5, 0x0000, 0x10, 0, 3),
+	PIN_FIELD_BASE(25, 25, 3, 0x0000, 0x10, 15, 3),
+	PIN_FIELD_BASE(26, 26, 3, 0x0000, 0x10, 18, 3),
+	PIN_FIELD_BASE(27, 27, 3, 0x0000, 0x10, 21, 3),
+	PIN_FIELD_BASE(28, 28, 3, 0x0000, 0x10, 24, 3),
+	PIN_FIELD_BASE(29, 29, 6, 0x0000, 0x10, 27, 3),
+	PIN_FIELD_BASE(30, 30, 6, 0x0010, 0x10, 9, 3),
+	PIN_FIELD_BASE(31, 31, 6, 0x0010, 0x10, 3, 3),
+	PIN_FIELD_BASE(32, 32, 6, 0x0010, 0x10, 0, 3),
+	PIN_FIELD_BASE(33, 33, 9, 0x0000, 0x10, 0, 3),
+	PIN_FIELD_BASE(34, 34, 9, 0x0000, 0x10, 3, 3),
+	PIN_FIELD_BASE(35, 35, 9, 0x0000, 0x10, 6, 3),
+	PIN_FIELD_BASE(36, 36, 8, 0x0000, 0x10, 0, 3),
+	PIN_FIELD_BASE(37, 37, 8, 0x0000, 0x10, 3, 3),
+	PIN_FIELD_BASE(38, 38, 8, 0x0000, 0x10, 6, 3),
+	PIN_FIELD_BASE(39, 39, 8, 0x0000, 0x10, 9, 3),
+	PIN_FIELD_BASE(40, 40, 8, 0x0000, 0x10, 12, 3),
+	PIN_FIELD_BASE(41, 41, 4, 0x0010, 0x10, 6, 3),
+	PIN_FIELD_BASE(42, 42, 4, 0x0000, 0x10, 27, 3),
+	PIN_FIELD_BASE(43, 43, 4, 0x0010, 0x10, 3, 3),
+	PIN_FIELD_BASE(44, 44, 4, 0x0010, 0x10, 9, 3),
+	PIN_FIELD_BASE(45, 45, 4, 0x0010, 0x10, 0, 3),
+	PIN_FIELD_BASE(46, 46, 4, 0x0010, 0x10, 18, 3),
+	PIN_FIELD_BASE(47, 47, 4, 0x0010, 0x10, 18, 3),
+	PIN_FIELD_BASE(48, 48, 3, 0x0010, 0x10, 21, 3),
+	PIN_FIELD_BASE(49, 49, 3, 0x0010, 0x10, 21, 3),
+	PIN_FIELD_BASE(50, 50, 3, 0x0010, 0x10, 18, 3),
+	PIN_FIELD_BASE(51, 51, 3, 0x0010, 0x10, 18, 3),
+	PIN_FIELD_BASE(52, 52, 3, 0x0010, 0x10, 12, 3),
+	PIN_FIELD_BASE(53, 53, 3, 0x0010, 0x10, 15, 3),
+	PIN_FIELD_BASE(54, 54, 3, 0x0010, 0x10, 24, 3),
+	PIN_FIELD_BASE(55, 55, 3, 0x0010, 0x10, 9, 3),
+	PIN_FIELD_BASE(56, 56, 5, 0x0000, 0x10, 24, 3),
+	PIN_FIELD_BASE(57, 57, 5, 0x0000, 0x10, 27, 3),
+	PIN_FIELD_BASE(58, 58, 3, 0x0020, 0x10, 6, 3),
+	PIN_FIELD_BASE(59, 59, 3, 0x0020, 0x10, 3, 3),
+	PIN_FIELD_BASE(60, 60, 8, 0x0020, 0x10, 0, 3),
+	PIN_FIELD_BASE(61, 61, 8, 0x0020, 0x10, 3, 3),
+	PIN_FIELD_BASE(62, 62, 8, 0x0020, 0x10, 9, 3),
+	PIN_FIELD_BASE(63, 63, 8, 0x0020, 0x10, 6, 3),
+	PIN_FIELD_BASE(64, 64, 8, 0x0020, 0x10, 12, 3),
+	PIN_FIELD_BASE(65, 65, 8, 0x0020, 0x10, 15, 3),
+	PIN_FIELD_BASE(66, 66, 8, 0x0020, 0x10, 21, 3),
+	PIN_FIELD_BASE(67, 67, 8, 0x0020, 0x10, 18, 3),
+	PIN_FIELD_BASE(68, 68, 5, 0x0000, 0x10, 9, 3),
+	PIN_FIELD_BASE(69, 69, 5, 0x0000, 0x10, 12, 3),
+	PIN_FIELD_BASE(70, 70, 5, 0x0000, 0x10, 18, 3),
+	PIN_FIELD_BASE(71, 71, 5, 0x0000, 0x10, 15, 3),
+	PIN_FIELD_BASE(72, 72, 5, 0x0010, 0x10, 0, 3),
+	PIN_FIELD_BASE(73, 73, 5, 0x0010, 0x10, 3, 3),
+	PIN_FIELD_BASE(74, 74, 5, 0x0010, 0x10, 9, 3),
+	PIN_FIELD_BASE(75, 75, 5, 0x0010, 0x10, 6, 3),
+	PIN_FIELD_BASE(76, 76, 5, 0x0000, 0x10, 3, 3),
+	PIN_FIELD_BASE(77, 77, 2, 0x0000, 0x10, 0, 3),
+	PIN_FIELD_BASE(78, 78, 2, 0x0000, 0x10, 3, 3),
+	PIN_FIELD_BASE(79, 79, 2, 0x0000, 0x10, 6, 3),
+	PIN_FIELD_BASE(80, 80, 2, 0x0000, 0x10, 9, 3),
+	PIN_FIELD_BASE(81, 81, 2, 0x0000, 0x10, 12, 3),
+	PIN_FIELD_BASE(82, 82, 2, 0x0000, 0x10, 15, 3),
+	PIN_FIELD_BASE(83, 83, 2, 0x0000, 0x10, 18, 3),
+	PIN_FIELD_BASE(84, 84, 2, 0x0000, 0x10, 27, 3),
+	PIN_FIELD_BASE(85, 85, 2, 0x0000, 0x10, 24, 3),
+	PIN_FIELD_BASE(86, 86, 2, 0x0010, 0x10, 0, 3),
+	PIN_FIELD_BASE(87, 87, 2, 0x0010, 0x10, 6, 3),
+	PIN_FIELD_BASE(88, 88, 2, 0x0010, 0x10, 3, 3),
+	PIN_FIELD_BASE(89, 89, 4, 0x0010, 0x10, 18, 3),
+	PIN_FIELD_BASE(90, 90, 4, 0x0010, 0x10, 21, 3),
+	PIN_FIELD_BASE(91, 91, 4, 0x0010, 0x10, 18, 3),
+	PIN_FIELD_BASE(92, 92, 8, 0x0000, 0x10, 15, 3),
+	PIN_FIELD_BASE(93, 93, 8, 0x0000, 0x10, 18, 3),
+	PIN_FIELD_BASE(94, 94, 8, 0x0000, 0x10, 21, 3),
+	PIN_FIELD_BASE(95, 95, 8, 0x0000, 0x10, 24, 3),
+	PIN_FIELD_BASE(96, 96, 8, 0x0000, 0x10, 27, 3),
+	PIN_FIELD_BASE(97, 97, 1, 0x0020, 0x10, 18, 3),
+	PIN_FIELD_BASE(98, 98, 1, 0x0020, 0x10, 15, 3),
+	PIN_FIELD_BASE(99, 99, 1, 0x0000, 0x10, 0, 3),
+	PIN_FIELD_BASE(100, 100, 1, 0x0000, 0x10, 27, 3),
+	PIN_FIELD_BASE(101, 101, 1, 0x0010, 0x10, 0, 3),
+	PIN_FIELD_BASE(102, 102, 1, 0x0010, 0x10, 3, 3),
+	PIN_FIELD_BASE(103, 103, 1, 0x0010, 0x10, 6, 3),
+	PIN_FIELD_BASE(104, 104, 1, 0x0010, 0x10, 9, 3),
+	PIN_FIELD_BASE(105, 105, 1, 0x0010, 0x10, 12, 3),
+	PIN_FIELD_BASE(106, 106, 1, 0x0010, 0x10, 15, 3),
+	PIN_FIELD_BASE(107, 107, 1, 0x0010, 0x10, 18, 3),
+	PIN_FIELD_BASE(108, 108, 1, 0x0010, 0x10, 21, 3),
+	PIN_FIELD_BASE(109, 109, 1, 0x0000, 0x10, 3, 3),
+	PIN_FIELD_BASE(110, 110, 1, 0x0000, 0x10, 6, 3),
+	PIN_FIELD_BASE(111, 111, 1, 0x0000, 0x10, 9, 3),
+	PIN_FIELD_BASE(112, 112, 1, 0x0000, 0x10, 12, 3),
+	PIN_FIELD_BASE(113, 113, 1, 0x0000, 0x10, 15, 3),
+	PIN_FIELD_BASE(114, 114, 1, 0x0000, 0x10, 18, 3),
+	PIN_FIELD_BASE(115, 115, 1, 0x0000, 0x10, 21, 3),
+	PIN_FIELD_BASE(116, 116, 1, 0x0000, 0x10, 24, 3),
+	PIN_FIELD_BASE(117, 117, 1, 0x0010, 0x10, 24, 3),
+	PIN_FIELD_BASE(118, 118, 1, 0x0010, 0x10, 27, 3),
+	PIN_FIELD_BASE(119, 119, 1, 0x0020, 0x10, 0, 3),
+	PIN_FIELD_BASE(120, 120, 1, 0x0020, 0x10, 3, 3),
+	PIN_FIELD_BASE(121, 121, 1, 0x0020, 0x10, 6, 3),
+	PIN_FIELD_BASE(122, 122, 1, 0x0020, 0x10, 9, 3),
+	PIN_FIELD_BASE(123, 123, 1, 0x0020, 0x10, 12, 3),
+	PIN_FIELD_BASE(124, 124, 1, 0x0020, 0x10, 12, 3),
+	PIN_FIELD_BASE(125, 125, 8, 0x0010, 0x10, 27, 3),
+	PIN_FIELD_BASE(126, 126, 8, 0x0020, 0x10, 24, 3),
+	PIN_FIELD_BASE(127, 127, 8, 0x0020, 0x10, 27, 3),
+	PIN_FIELD_BASE(128, 128, 8, 0x0030, 0x10, 0, 3),
+	PIN_FIELD_BASE(129, 129, 8, 0x0010, 0x10, 0, 3),
+	PIN_FIELD_BASE(130, 130, 8, 0x0010, 0x10, 9, 3),
+	PIN_FIELD_BASE(131, 131, 6, 0x0010, 0x10, 12, 3),
+	PIN_FIELD_BASE(132, 132, 6, 0x0010, 0x10, 21, 3),
+	PIN_FIELD_BASE(133, 133, 8, 0x0010, 0x10, 3, 3),
+	PIN_FIELD_BASE(134, 134, 8, 0x0010, 0x10, 12, 3),
+	PIN_FIELD_BASE(135, 135, 6, 0x0010, 0x10, 15, 3),
+	PIN_FIELD_BASE(136, 136, 6, 0x0010, 0x10, 24, 3),
+	PIN_FIELD_BASE(137, 137, 6, 0x0010, 0x10, 18, 3),
+	PIN_FIELD_BASE(138, 138, 6, 0x0010, 0x10, 27, 3),
+	PIN_FIELD_BASE(139, 139, 6, 0x0000, 0x10, 0, 3),
+	PIN_FIELD_BASE(140, 140, 6, 0x0000, 0x10, 6, 3),
+	PIN_FIELD_BASE(141, 141, 6, 0x0000, 0x10, 3, 3),
+	PIN_FIELD_BASE(142, 142, 6, 0x0000, 0x10, 9, 3),
+	PIN_FIELD_BASE(143, 143, 8, 0x0010, 0x10, 6, 3),
+	PIN_FIELD_BASE(144, 144, 8, 0x0010, 0x10, 15, 3),
+	PIN_FIELD_BASE(145, 145, 5, 0x0000, 0x10, 6, 3),
+	PIN_FIELD_BASE(146, 146, 5, 0x0000, 0x10, 21, 3),
+	PIN_FIELD_BASE(147, 147, 3, 0x0010, 0x10, 27, 3),
+	PIN_FIELD_BASE(148, 148, 3, 0x0020, 0x10, 0, 3),
+	PIN_FIELD_BASE(149, 149, 8, 0x0010, 0x10, 18, 3),
+	PIN_FIELD_BASE(150, 150, 8, 0x0010, 0x10, 21, 3),
+	PIN_FIELD_BASE(151, 151, 8, 0x0010, 0x10, 24, 3),
+	PIN_FIELD_BASE(152, 152, 8, 0x0010, 0x10, 24, 3),
+	PIN_FIELD_BASE(153, 153, 2, 0x0000, 0x10, 21, 3),
+	PIN_FIELD_BASE(154, 154, 2, 0x0000, 0x10, 21, 3),
+	PIN_FIELD_BASE(155, 155, 2, 0x0000, 0x10, 21, 3),
+	PIN_FIELD_BASE(156, 156, 9, 0x0000, 0x10, 21, 3),
+	PIN_FIELD_BASE(157, 157, 9, 0x0000, 0x10, 24, 3),
+	PIN_FIELD_BASE(158, 158, 9, 0x0000, 0x10, 27, 3),
+	PIN_FIELD_BASE(159, 159, 9, 0x0010, 0x10, 0, 3),
+	PIN_FIELD_BASE(160, 160, 4, 0x0010, 0x10, 21, 3),
+	PIN_FIELD_BASE(161, 161, 4, 0x0010, 0x10, 21, 3),
+	PIN_FIELD_BASE(162, 162, 4, 0x0010, 0x10, 21, 3),
+	PIN_FIELD_BASE(163, 163, 4, 0x0010, 0x10, 24, 3),
+	PIN_FIELD_BASE(164, 164, 4, 0x0010, 0x10, 15, 3),
+	PIN_FIELD_BASE(165, 165, 4, 0x0010, 0x10, 12, 3),
+	PIN_FIELD_BASE(166, 166, 4, 0x0010, 0x10, 12, 3),
+	PIN_FIELD_BASE(167, 167, 4, 0x0010, 0x10, 12, 3),
+	PIN_FIELD_BASE(168, 168, 4, 0x0010, 0x10, 12, 3),
+	PIN_FIELD_BASE(169, 169, 4, 0x0010, 0x10, 12, 3),
+	PIN_FIELD_BASE(170, 170, 4, 0x0000, 0x10, 0, 3),
+	PIN_FIELD_BASE(171, 171, 4, 0x0000, 0x10, 3, 3),
+	PIN_FIELD_BASE(172, 172, 9, 0x0000, 0x10, 18, 3),
+	PIN_FIELD_BASE(173, 173, 9, 0x0000, 0x10, 18, 3),
+	PIN_FIELD_BASE(174, 174, 9, 0x0000, 0x10, 18, 3),
+	PIN_FIELD_BASE(175, 175, 9, 0x0000, 0x10, 18, 3),
+	PIN_FIELD_BASE(176, 176, 9, 0x0000, 0x10, 18, 3),
+	PIN_FIELD_BASE(177, 177, 9, 0x0000, 0x10, 18, 3),
+	PIN_FIELD_BASE(178, 178, 9, 0x0000, 0x10, 15, 3),
+	PIN_FIELD_BASE(179, 179, 9, 0x0000, 0x10, 15, 3),
+	PIN_FIELD_BASE(180, 180, 9, 0x0000, 0x10, 15, 3),
+	PIN_FIELD_BASE(181, 181, 9, 0x0000, 0x10, 9, 3),
+	PIN_FIELD_BASE(182, 182, 9, 0x0000, 0x10, 12, 3),
+	PIN_FIELD_BASE(183, 183, 9, 0x0000, 0x10, 18, 3),
+	PIN_FIELD_BASE(184, 184, 7, 0x0010, 0x10, 0, 3),
+	PIN_FIELD_BASE(185, 185, 7, 0x0000, 0x10, 0, 3),
+	PIN_FIELD_BASE(186, 186, 7, 0x0000, 0x10, 3, 3),
+	PIN_FIELD_BASE(187, 187, 7, 0x0010, 0x10, 3, 3),
+	PIN_FIELD_BASE(188, 188, 7, 0x0000, 0x10, 6, 3),
+	PIN_FIELD_BASE(189, 189, 7, 0x0000, 0x10, 9, 3),
+	PIN_FIELD_BASE(190, 190, 7, 0x0000, 0x10, 12, 3),
+	PIN_FIELD_BASE(191, 191, 7, 0x0000, 0x10, 15, 3),
+	PIN_FIELD_BASE(192, 192, 7, 0x0000, 0x10, 18, 3),
+	PIN_FIELD_BASE(193, 193, 7, 0x0000, 0x10, 21, 3),
+	PIN_FIELD_BASE(194, 194, 7, 0x0000, 0x10, 24, 3),
+	PIN_FIELD_BASE(195, 195, 7, 0x0000, 0x10, 27, 3),
+};
+
+static const struct mtk_pin_field_calc mt6878_pin_eh_range[] = {
+	PIN_FIELD_BASE(19, 19, 3, 0x0030, 0x10, 0, 3),
+	PIN_FIELD_BASE(24, 24, 5, 0x0020, 0x10, 0, 3),
+	PIN_FIELD_BASE(25, 25, 3, 0x0030, 0x10, 3, 3),
+	PIN_FIELD_BASE(26, 26, 3, 0x0030, 0x10, 6, 3),
+	PIN_FIELD_BASE(52, 52, 3, 0x0030, 0x10, 12, 3),
+	PIN_FIELD_BASE(53, 53, 3, 0x0030, 0x10, 15, 3),
+	PIN_FIELD_BASE(55, 55, 3, 0x0030, 0x10, 9, 3),
+	PIN_FIELD_BASE(60, 60, 8, 0x0050, 0x10, 12, 3),
+	PIN_FIELD_BASE(61, 61, 8, 0x0050, 0x10, 15, 3),
+	PIN_FIELD_BASE(62, 62, 8, 0x0050, 0x10, 21, 3),
+	PIN_FIELD_BASE(63, 63, 8, 0x0050, 0x10, 18, 3),
+	PIN_FIELD_BASE(64, 64, 8, 0x0050, 0x10, 24, 3),
+	PIN_FIELD_BASE(65, 65, 8, 0x0050, 0x10, 27, 3),
+	PIN_FIELD_BASE(66, 66, 8, 0x0060, 0x10, 3, 3),
+	PIN_FIELD_BASE(67, 67, 8, 0x0060, 0x10, 0, 3),
+	PIN_FIELD_BASE(92, 92, 8, 0x0040, 0x10, 0, 3),
+	PIN_FIELD_BASE(93, 93, 8, 0x0040, 0x10, 3, 3),
+	PIN_FIELD_BASE(94, 94, 8, 0x0040, 0x10, 6, 3),
+	PIN_FIELD_BASE(95, 95, 8, 0x0040, 0x10, 9, 3),
+	PIN_FIELD_BASE(96, 96, 8, 0x0040, 0x10, 12, 3),
+	PIN_FIELD_BASE(125, 125, 8, 0x0050, 0x10, 9, 3),
+	PIN_FIELD_BASE(126, 126, 8, 0x0060, 0x10, 6, 3),
+	PIN_FIELD_BASE(127, 127, 8, 0x0060, 0x10, 9, 3),
+	PIN_FIELD_BASE(128, 128, 8, 0x0060, 0x10, 12, 3),
+	PIN_FIELD_BASE(129, 129, 8, 0x0040, 0x10, 15, 3),
+	PIN_FIELD_BASE(130, 130, 8, 0x0040, 0x10, 24, 3),
+	PIN_FIELD_BASE(131, 131, 6, 0x0030, 0x10, 12, 3),
+	PIN_FIELD_BASE(132, 132, 6, 0x0030, 0x10, 21, 3),
+	PIN_FIELD_BASE(133, 133, 8, 0x0040, 0x10, 18, 3),
+	PIN_FIELD_BASE(134, 134, 8, 0x0040, 0x10, 27, 3),
+	PIN_FIELD_BASE(135, 135, 6, 0x0030, 0x10, 15, 3),
+	PIN_FIELD_BASE(136, 136, 6, 0x0030, 0x10, 24, 3),
+	PIN_FIELD_BASE(137, 137, 6, 0x0030, 0x10, 18, 3),
+	PIN_FIELD_BASE(138, 138, 6, 0x0030, 0x10, 27, 3),
+	PIN_FIELD_BASE(139, 139, 6, 0x0030, 0x10, 0, 3),
+	PIN_FIELD_BASE(140, 140, 6, 0x0030, 0x10, 6, 3),
+	PIN_FIELD_BASE(141, 141, 6, 0x0030, 0x10, 3, 3),
+	PIN_FIELD_BASE(142, 142, 6, 0x0030, 0x10, 9, 3),
+	PIN_FIELD_BASE(143, 143, 8, 0x0040, 0x10, 21, 3),
+	PIN_FIELD_BASE(144, 144, 8, 0x0050, 0x10, 0, 3),
+	PIN_FIELD_BASE(145, 145, 5, 0x0020, 0x10, 3, 3),
+	PIN_FIELD_BASE(146, 146, 5, 0x0020, 0x10, 6, 3),
+	PIN_FIELD_BASE(147, 147, 3, 0x0030, 0x10, 18, 3),
+	PIN_FIELD_BASE(148, 148, 3, 0x0030, 0x10, 21, 3),
+	PIN_FIELD_BASE(149, 149, 8, 0x0050, 0x10, 3, 3),
+	PIN_FIELD_BASE(150, 150, 8, 0x0050, 0x10, 6, 3),
+	PIN_FIELD_BASE(156, 156, 9, 0x0020, 0x10, 0, 5),
+	PIN_FIELD_BASE(157, 157, 9, 0x0020, 0x10, 5, 5),
+	PIN_FIELD_BASE(158, 158, 9, 0x0020, 0x10, 10, 5),
+	PIN_FIELD_BASE(159, 159, 9, 0x0020, 0x10, 15, 5),
+};
+
+static const struct mtk_pin_field_calc mt6878_pin_rsel_range[] = {
+	PIN_FIELD_BASE(19, 19, 3, 0x00d0, 0x10, 0, 3),
+	PIN_FIELD_BASE(24, 24, 5, 0x00a0, 0x10, 0, 3),
+	PIN_FIELD_BASE(25, 25, 3, 0x00d0, 0x10, 3, 3),
+	PIN_FIELD_BASE(26, 26, 3, 0x00d0, 0x10, 6, 3),
+	PIN_FIELD_BASE(52, 52, 3, 0x00d0, 0x10, 12, 3),
+	PIN_FIELD_BASE(53, 53, 3, 0x00d0, 0x10, 15, 3),
+	PIN_FIELD_BASE(55, 55, 3, 0x00d0, 0x10, 9, 3),
+	PIN_FIELD_BASE(60, 60, 8, 0x0110, 0x10, 12, 3),
+	PIN_FIELD_BASE(61, 61, 8, 0x0110, 0x10, 15, 3),
+	PIN_FIELD_BASE(62, 62, 8, 0x0110, 0x10, 21, 3),
+	PIN_FIELD_BASE(63, 63, 8, 0x0110, 0x10, 18, 3),
+	PIN_FIELD_BASE(64, 64, 8, 0x0110, 0x10, 24, 3),
+	PIN_FIELD_BASE(65, 65, 8, 0x0110, 0x10, 27, 3),
+	PIN_FIELD_BASE(66, 66, 8, 0x0120, 0x10, 3, 3),
+	PIN_FIELD_BASE(67, 67, 8, 0x0120, 0x10, 0, 3),
+	PIN_FIELD_BASE(92, 92, 8, 0x0100, 0x10, 0, 3),
+	PIN_FIELD_BASE(93, 93, 8, 0x0100, 0x10, 3, 3),
+	PIN_FIELD_BASE(94, 94, 8, 0x0100, 0x10, 6, 3),
+	PIN_FIELD_BASE(95, 95, 8, 0x0100, 0x10, 9, 3),
+	PIN_FIELD_BASE(96, 96, 8, 0x0100, 0x10, 12, 3),
+	PIN_FIELD_BASE(125, 125, 8, 0x0110, 0x10, 9, 3),
+	PIN_FIELD_BASE(126, 126, 8, 0x0120, 0x10, 6, 3),
+	PIN_FIELD_BASE(127, 127, 8, 0x0120, 0x10, 9, 3),
+	PIN_FIELD_BASE(128, 128, 8, 0x0120, 0x10, 12, 3),
+	PIN_FIELD_BASE(129, 129, 8, 0x0100, 0x10, 15, 3),
+	PIN_FIELD_BASE(130, 130, 8, 0x0100, 0x10, 24, 3),
+	PIN_FIELD_BASE(131, 131, 6, 0x00d0, 0x10, 12, 3),
+	PIN_FIELD_BASE(132, 132, 6, 0x00d0, 0x10, 21, 3),
+	PIN_FIELD_BASE(133, 133, 8, 0x0100, 0x10, 18, 3),
+	PIN_FIELD_BASE(134, 134, 8, 0x0100, 0x10, 27, 3),
+	PIN_FIELD_BASE(135, 135, 6, 0x00d0, 0x10, 15, 3),
+	PIN_FIELD_BASE(136, 136, 6, 0x00d0, 0x10, 24, 3),
+	PIN_FIELD_BASE(137, 137, 6, 0x00d0, 0x10, 18, 3),
+	PIN_FIELD_BASE(138, 138, 6, 0x00d0, 0x10, 27, 3),
+	PIN_FIELD_BASE(139, 139, 6, 0x00d0, 0x10, 0, 3),
+	PIN_FIELD_BASE(140, 140, 6, 0x00d0, 0x10, 6, 3),
+	PIN_FIELD_BASE(141, 141, 6, 0x00d0, 0x10, 3, 3),
+	PIN_FIELD_BASE(142, 142, 6, 0x00d0, 0x10, 9, 3),
+	PIN_FIELD_BASE(143, 143, 8, 0x0100, 0x10, 21, 3),
+	PIN_FIELD_BASE(144, 144, 8, 0x0110, 0x10, 0, 3),
+	PIN_FIELD_BASE(145, 145, 5, 0x00a0, 0x10, 3, 3),
+	PIN_FIELD_BASE(146, 146, 5, 0x00a0, 0x10, 6, 3),
+	PIN_FIELD_BASE(147, 147, 3, 0x00d0, 0x10, 18, 3),
+	PIN_FIELD_BASE(148, 148, 3, 0x00d0, 0x10, 21, 3),
+	PIN_FIELD_BASE(149, 149, 8, 0x0110, 0x10, 3, 3),
+	PIN_FIELD_BASE(150, 150, 8, 0x0110, 0x10, 6, 3),
+};
+
+static const unsigned int mt6878_pull_type[] = {
+	MTK_PULL_PU_PD_TYPE /* 0 */,
+	MTK_PULL_PU_PD_TYPE /* 1 */,
+	MTK_PULL_PU_PD_TYPE /* 2 */,
+	MTK_PULL_PU_PD_TYPE /* 3 */,
+	MTK_PULL_PU_PD_TYPE /* 4 */,
+	MTK_PULL_PU_PD_TYPE /* 5 */,
+	MTK_PULL_PU_PD_TYPE /* 6 */,
+	MTK_PULL_PU_PD_TYPE /* 7 */,
+	MTK_PULL_PU_PD_TYPE /* 8 */,
+	MTK_PULL_PU_PD_TYPE /* 9 */,
+	MTK_PULL_PU_PD_TYPE /* 10 */,
+	MTK_PULL_PU_PD_TYPE /* 11 */,
+	MTK_PULL_PU_PD_TYPE /* 12 */,
+	MTK_PULL_PU_PD_TYPE /* 13 */,
+	MTK_PULL_PU_PD_TYPE /* 14 */,
+	MTK_PULL_PU_PD_TYPE /* 15 */,
+	MTK_PULL_PU_PD_TYPE /* 16 */,
+	MTK_PULL_PU_PD_TYPE /* 17 */,
+	MTK_PULL_PU_PD_TYPE /* 18 */,
+	MTK_PULL_PU_PD_RSEL_TYPE /* 19 */,
+	MTK_PULL_PU_PD_TYPE /* 20 */,
+	MTK_PULL_PU_PD_TYPE /* 21 */,
+	MTK_PULL_PU_PD_TYPE /* 22 */,
+	MTK_PULL_PU_PD_TYPE /* 23 */,
+	MTK_PULL_PU_PD_RSEL_TYPE /* 24 */,
+	MTK_PULL_PU_PD_RSEL_TYPE /* 25 */,
+	MTK_PULL_PU_PD_RSEL_TYPE /* 26 */,
+	MTK_PULL_PU_PD_TYPE /* 27 */,
+	MTK_PULL_PU_PD_TYPE /* 28 */,
+	MTK_PULL_PU_PD_TYPE /* 29 */,
+	MTK_PULL_PU_PD_TYPE /* 30 */,
+	MTK_PULL_PU_PD_TYPE /* 31 */,
+	MTK_PULL_PU_PD_TYPE /* 32 */,
+	MTK_PULL_PUPD_R1R0_TYPE /* 33 */,
+	MTK_PULL_PUPD_R1R0_TYPE /* 34 */,
+	MTK_PULL_PUPD_R1R0_TYPE /* 35 */,
+	MTK_PULL_PU_PD_TYPE /* 36 */,
+	MTK_PULL_PU_PD_TYPE /* 37 */,
+	MTK_PULL_PU_PD_TYPE /* 38 */,
+	MTK_PULL_PU_PD_TYPE /* 39 */,
+	MTK_PULL_PU_PD_TYPE /* 40 */,
+	MTK_PULL_PU_PD_TYPE /* 41 */,
+	MTK_PULL_PU_PD_TYPE /* 42 */,
+	MTK_PULL_PU_PD_TYPE /* 43 */,
+	MTK_PULL_PU_PD_TYPE /* 44 */,
+	MTK_PULL_PU_PD_TYPE /* 45 */,
+	MTK_PULL_PU_PD_TYPE /* 46 */,
+	MTK_PULL_PU_PD_TYPE /* 47 */,
+	MTK_PULL_PU_PD_TYPE /* 48 */,
+	MTK_PULL_PU_PD_TYPE /* 49 */,
+	MTK_PULL_PU_PD_TYPE /* 50 */,
+	MTK_PULL_PU_PD_TYPE /* 51 */,
+	MTK_PULL_PU_PD_RSEL_TYPE /* 52 */,
+	MTK_PULL_PU_PD_RSEL_TYPE /* 53 */,
+	MTK_PULL_PU_PD_TYPE /* 54 */,
+	MTK_PULL_PU_PD_RSEL_TYPE /* 55 */,
+	MTK_PULL_PU_PD_TYPE /* 56 */,
+	MTK_PULL_PU_PD_TYPE /* 57 */,
+	MTK_PULL_PU_PD_TYPE /* 58 */,
+	MTK_PULL_PU_PD_TYPE /* 59 */,
+	MTK_PULL_PU_PD_RSEL_TYPE /* 60 */,
+	MTK_PULL_PU_PD_RSEL_TYPE /* 61 */,
+	MTK_PULL_PU_PD_RSEL_TYPE /* 62 */,
+	MTK_PULL_PU_PD_RSEL_TYPE /* 63 */,
+	MTK_PULL_PU_PD_RSEL_TYPE /* 64 */,
+	MTK_PULL_PU_PD_RSEL_TYPE /* 65 */,
+	MTK_PULL_PU_PD_RSEL_TYPE /* 66 */,
+	MTK_PULL_PU_PD_RSEL_TYPE /* 67 */,
+	MTK_PULL_PU_PD_TYPE /* 68 */,
+	MTK_PULL_PU_PD_TYPE /* 69 */,
+	MTK_PULL_PU_PD_TYPE /* 70 */,
+	MTK_PULL_PU_PD_TYPE /* 71 */,
+	MTK_PULL_PU_PD_TYPE /* 72 */,
+	MTK_PULL_PU_PD_TYPE /* 73 */,
+	MTK_PULL_PU_PD_TYPE /* 74 */,
+	MTK_PULL_PU_PD_TYPE /* 75 */,
+	MTK_PULL_PU_PD_TYPE /* 76 */,
+	MTK_PULL_PUPD_R1R0_TYPE /* 77 */,
+	MTK_PULL_PUPD_R1R0_TYPE /* 78 */,
+	MTK_PULL_PUPD_R1R0_TYPE /* 79 */,
+	MTK_PULL_PUPD_R1R0_TYPE /* 80 */,
+	MTK_PULL_PUPD_R1R0_TYPE /* 81 */,
+	MTK_PULL_PUPD_R1R0_TYPE /* 82 */,
+	MTK_PULL_PUPD_R1R0_TYPE /* 83 */,
+	MTK_PULL_PUPD_R1R0_TYPE /* 84 */,
+	MTK_PULL_PUPD_R1R0_TYPE /* 85 */,
+	MTK_PULL_PUPD_R1R0_TYPE /* 86 */,
+	MTK_PULL_PUPD_R1R0_TYPE /* 87 */,
+	MTK_PULL_PUPD_R1R0_TYPE /* 88 */,
+	MTK_PULL_PU_PD_TYPE /* 89 */,
+	MTK_PULL_PU_PD_TYPE /* 90 */,
+	MTK_PULL_PU_PD_TYPE /* 91 */,
+	MTK_PULL_PU_PD_RSEL_TYPE /* 92 */,
+	MTK_PULL_PU_PD_RSEL_TYPE /* 93 */,
+	MTK_PULL_PU_PD_RSEL_TYPE /* 94 */,
+	MTK_PULL_PU_PD_RSEL_TYPE /* 95 */,
+	MTK_PULL_PU_PD_RSEL_TYPE /* 96 */,
+	MTK_PULL_PUPD_R1R0_TYPE /* 97 */,
+	MTK_PULL_PUPD_R1R0_TYPE /* 98 */,
+	MTK_PULL_PU_PD_TYPE /* 99 */,
+	MTK_PULL_PU_PD_TYPE /* 100 */,
+	MTK_PULL_PU_PD_TYPE /* 101 */,
+	MTK_PULL_PU_PD_TYPE /* 102 */,
+	MTK_PULL_PU_PD_TYPE /* 103 */,
+	MTK_PULL_PU_PD_TYPE /* 104 */,
+	MTK_PULL_PU_PD_TYPE /* 105 */,
+	MTK_PULL_PU_PD_TYPE /* 106 */,
+	MTK_PULL_PU_PD_TYPE /* 107 */,
+	MTK_PULL_PU_PD_TYPE /* 108 */,
+	MTK_PULL_PU_PD_TYPE /* 109 */,
+	MTK_PULL_PU_PD_TYPE /* 110 */,
+	MTK_PULL_PU_PD_TYPE /* 111 */,
+	MTK_PULL_PU_PD_TYPE /* 112 */,
+	MTK_PULL_PU_PD_TYPE /* 113 */,
+	MTK_PULL_PU_PD_TYPE /* 114 */,
+	MTK_PULL_PU_PD_TYPE /* 115 */,
+	MTK_PULL_PU_PD_TYPE /* 116 */,
+	MTK_PULL_PUPD_R1R0_TYPE /* 117 */,
+	MTK_PULL_PUPD_R1R0_TYPE /* 118 */,
+	MTK_PULL_PUPD_R1R0_TYPE /* 119 */,
+	MTK_PULL_PUPD_R1R0_TYPE /* 120 */,
+	MTK_PULL_PUPD_R1R0_TYPE /* 121 */,
+	MTK_PULL_PUPD_R1R0_TYPE /* 122 */,
+	MTK_PULL_PUPD_R1R0_TYPE /* 123 */,
+	MTK_PULL_PUPD_R1R0_TYPE /* 124 */,
+	MTK_PULL_PU_PD_RSEL_TYPE /* 125 */,
+	MTK_PULL_PU_PD_RSEL_TYPE /* 126 */,
+	MTK_PULL_PU_PD_RSEL_TYPE /* 127 */,
+	MTK_PULL_PU_PD_RSEL_TYPE /* 128 */,
+	MTK_PULL_PU_PD_RSEL_TYPE /* 129 */,
+	MTK_PULL_PU_PD_RSEL_TYPE /* 130 */,
+	MTK_PULL_PU_PD_RSEL_TYPE /* 131 */,
+	MTK_PULL_PU_PD_RSEL_TYPE /* 132 */,
+	MTK_PULL_PU_PD_RSEL_TYPE /* 133 */,
+	MTK_PULL_PU_PD_RSEL_TYPE /* 134 */,
+	MTK_PULL_PU_PD_RSEL_TYPE /* 135 */,
+	MTK_PULL_PU_PD_RSEL_TYPE /* 136 */,
+	MTK_PULL_PU_PD_RSEL_TYPE /* 137 */,
+	MTK_PULL_PU_PD_RSEL_TYPE /* 138 */,
+	MTK_PULL_PU_PD_RSEL_TYPE /* 139 */,
+	MTK_PULL_PU_PD_RSEL_TYPE /* 140 */,
+	MTK_PULL_PU_PD_RSEL_TYPE /* 141 */,
+	MTK_PULL_PU_PD_RSEL_TYPE /* 142 */,
+	MTK_PULL_PU_PD_RSEL_TYPE /* 143 */,
+	MTK_PULL_PU_PD_RSEL_TYPE /* 144 */,
+	MTK_PULL_PU_PD_RSEL_TYPE /* 145 */,
+	MTK_PULL_PU_PD_RSEL_TYPE /* 146 */,
+	MTK_PULL_PU_PD_RSEL_TYPE /* 147 */,
+	MTK_PULL_PU_PD_RSEL_TYPE /* 148 */,
+	MTK_PULL_PU_PD_RSEL_TYPE /* 149 */,
+	MTK_PULL_PU_PD_RSEL_TYPE /* 150 */,
+	MTK_PULL_PU_PD_TYPE /* 151 */,
+	MTK_PULL_PU_PD_TYPE /* 152 */,
+	MTK_PULL_PUPD_R1R0_TYPE /* 153 */,
+	MTK_PULL_PUPD_R1R0_TYPE /* 154 */,
+	MTK_PULL_PUPD_R1R0_TYPE /* 155 */,
+	MTK_PULL_PU_PD_TYPE /* 156 */,
+	MTK_PULL_PU_PD_TYPE /* 157 */,
+	MTK_PULL_PU_PD_TYPE /* 158 */,
+	MTK_PULL_PU_PD_TYPE /* 159 */,
+	MTK_PULL_PU_PD_TYPE /* 160 */,
+	MTK_PULL_PU_PD_TYPE /* 161 */,
+	MTK_PULL_PU_PD_TYPE /* 162 */,
+	MTK_PULL_PU_PD_TYPE /* 163 */,
+	MTK_PULL_PU_PD_TYPE /* 164 */,
+	MTK_PULL_PU_PD_TYPE /* 165 */,
+	MTK_PULL_PU_PD_TYPE /* 166 */,
+	MTK_PULL_PU_PD_TYPE /* 167 */,
+	MTK_PULL_PU_PD_TYPE /* 168 */,
+	MTK_PULL_PU_PD_TYPE /* 169 */,
+	MTK_PULL_PU_PD_TYPE /* 170 */,
+	MTK_PULL_PU_PD_TYPE /* 171 */,
+	MTK_PULL_PUPD_R1R0_TYPE /* 172 */,
+	MTK_PULL_PUPD_R1R0_TYPE /* 173 */,
+	MTK_PULL_PUPD_R1R0_TYPE /* 174 */,
+	MTK_PULL_PUPD_R1R0_TYPE /* 175 */,
+	MTK_PULL_PUPD_R1R0_TYPE /* 176 */,
+	MTK_PULL_PUPD_R1R0_TYPE /* 177 */,
+	MTK_PULL_PUPD_R1R0_TYPE /* 178 */,
+	MTK_PULL_PUPD_R1R0_TYPE /* 179 */,
+	MTK_PULL_PUPD_R1R0_TYPE /* 180 */,
+	MTK_PULL_PUPD_R1R0_TYPE /* 181 */,
+	MTK_PULL_PUPD_R1R0_TYPE /* 182 */,
+	MTK_PULL_PUPD_R1R0_TYPE /* 183 */,
+	MTK_PULL_PUPD_R1R0_TYPE /* 184 */,
+	MTK_PULL_PUPD_R1R0_TYPE /* 185 */,
+	MTK_PULL_PUPD_R1R0_TYPE /* 186 */,
+	MTK_PULL_PUPD_R1R0_TYPE /* 187 */,
+	MTK_PULL_PUPD_R1R0_TYPE /* 188 */,
+	MTK_PULL_PUPD_R1R0_TYPE /* 189 */,
+	MTK_PULL_PUPD_R1R0_TYPE /* 190 */,
+	MTK_PULL_PUPD_R1R0_TYPE /* 191 */,
+	MTK_PULL_PUPD_R1R0_TYPE /* 192 */,
+	MTK_PULL_PUPD_R1R0_TYPE /* 193 */,
+	MTK_PULL_PUPD_R1R0_TYPE /* 194 */,
+	MTK_PULL_PUPD_R1R0_TYPE /* 195 */,
+};
+
+static const struct mtk_eh_pin_pinmux mt6878_eh_pin_pinmux_list[] = {
+	PIN_MUX_EH(19, 3),
+	PIN_MUX_EH(24, 2),
+	PIN_MUX_EH(24, 3),
+	PIN_MUX_EH(25, 2),
+	PIN_MUX_EH(26, 2),
+	PIN_MUX_EH(52, 3),
+	PIN_MUX_EH(53, 3),
+	PIN_MUX_EH(55, 3),
+	PIN_MUX_EH(125, 1),
+	PIN_MUX_EH(126, 1),
+	PIN_MUX_EH(127, 1),
+	PIN_MUX_EH(128, 1),
+	PIN_MUX_EH(129, 1),
+	PIN_MUX_EH(130, 1),
+	PIN_MUX_EH(131, 1),
+	PIN_MUX_EH(132, 1),
+	PIN_MUX_EH(133, 1),
+	PIN_MUX_EH(134, 1),
+	PIN_MUX_EH(135, 1),
+	PIN_MUX_EH(136, 1),
+	PIN_MUX_EH(137, 1),
+	PIN_MUX_EH(138, 1),
+	PIN_MUX_EH(139, 1),
+	PIN_MUX_EH(140, 1),
+	PIN_MUX_EH(141, 1),
+	PIN_MUX_EH(142, 1),
+	PIN_MUX_EH(143, 1),
+	PIN_MUX_EH(144, 1),
+	PIN_MUX_EH(145, 1),
+	PIN_MUX_EH(146, 1),
+	PIN_MUX_EH(147, 1),
+	PIN_MUX_EH(148, 1),
+	PIN_MUX_EH(149, 6),
+	PIN_MUX_EH(150, 6),
+};
+
+static const char * const mt6878_pinctrl_register_base_names[] = {
+	"gpio", "iocfg_bl", "iocfg_bm", "iocfg_br",
+	"iocfg_bl1", "iocfg_br1", "iocfg_lm", "iocfg_lt",
+	"iocfg_rm", "iocfg_rt",
+};
+
+static const struct mtk_eint_hw mt6878_eint_hw = {
+	.port_mask = 31,
+	.ports     = 1,
+	.ap_num    = 216,
+	.db_cnt    = 36,
+	.db_time   = debounce_time_mt6878,
+};
+
+static const struct mtk_pin_reg_calc mt6878_reg_cals[PINCTRL_PIN_REG_MAX] = {
+	[PINCTRL_PIN_REG_MODE] = MTK_RANGE(mt6878_pin_mode_range),
+	[PINCTRL_PIN_REG_DIR] = MTK_RANGE(mt6878_pin_dir_range),
+	[PINCTRL_PIN_REG_DI] = MTK_RANGE(mt6878_pin_di_range),
+	[PINCTRL_PIN_REG_DO] = MTK_RANGE(mt6878_pin_do_range),
+	[PINCTRL_PIN_REG_SR] = MTK_RANGE(mt6878_pin_dir_range),
+	[PINCTRL_PIN_REG_SMT] = MTK_RANGE(mt6878_pin_smt_range),
+	[PINCTRL_PIN_REG_IES] = MTK_RANGE(mt6878_pin_ies_range),
+	[PINCTRL_PIN_REG_PU] = MTK_RANGE(mt6878_pin_pu_range),
+	[PINCTRL_PIN_REG_PD] = MTK_RANGE(mt6878_pin_pd_range),
+	[PINCTRL_PIN_REG_DRV] = MTK_RANGE(mt6878_pin_drv_range),
+	[PINCTRL_PIN_REG_PUPD] = MTK_RANGE(mt6878_pin_pupd_range),
+	[PINCTRL_PIN_REG_R0] = MTK_RANGE(mt6878_pin_r0_range),
+	[PINCTRL_PIN_REG_R1] = MTK_RANGE(mt6878_pin_r1_range),
+	[PINCTRL_PIN_REG_DRV_EH] = MTK_RANGE(mt6878_pin_eh_range),
+	[PINCTRL_PIN_REG_RSEL] = MTK_RANGE(mt6878_pin_rsel_range),
+};
+
+static const struct mtk_pin_soc mt6878_data = {
+	.reg_cal = mt6878_reg_cals,
+	.pins = mtk_pins_mt6878,
+	.npins = ARRAY_SIZE(mtk_pins_mt6878),
+	.ngrps = ARRAY_SIZE(mtk_pins_mt6878),
+	.eint_pin = eint_pins_mt6878,
+	.eint_hw = &mt6878_eint_hw,
+	.nfuncs = 8,
+	.gpio_m = 0,
+	.base_names = mt6878_pinctrl_register_base_names,
+	.nbase_names = ARRAY_SIZE(mt6878_pinctrl_register_base_names),
+	.bias_set_combo = mtk_pinconf_bias_set_combo,
+	.bias_get_combo = mtk_pinconf_bias_get_combo,
+	.pull_type = mt6878_pull_type,
+	.eh_pin_pinmux = mt6878_eh_pin_pinmux_list,
+	.neh_pins = ARRAY_SIZE(mt6878_eh_pin_pinmux_list),
+	.adv_drive_get = mtk_pinconf_adv_drive_get,
+	.adv_drive_set = mtk_pinconf_adv_drive_set,
+};
+
+static const struct of_device_id mt6878_pinctrl_of_match[] = {
+	{ .compatible = "mediatek,mt6878-pinctrl", .data = &mt6878_data },
+	{ }
+};
+
+static struct platform_driver mt6878_pinctrl_driver = {
+	.driver = {
+		.name = "mt6878-pinctrl",
+		.of_match_table = mt6878_pinctrl_of_match,
+		.pm = pm_sleep_ptr(&mtk_paris_pinctrl_pm_ops),
+	},
+	.probe = mtk_paris_pinctrl_probe,
+};
+
+static int __init mt6878_pinctrl_init(void)
+{
+	return platform_driver_register(&mt6878_pinctrl_driver);
+}
+arch_initcall(mt6878_pinctrl_init);
+
+MODULE_DESCRIPTION("MediaTek MT6878 Pinctrl Driver");
diff --git a/drivers/pinctrl/mediatek/pinctrl-mtk-mt6878.h b/drivers/pinctrl/mediatek/pinctrl-mtk-mt6878.h
new file mode 100644
index 0000000000000000000000000000000000000000..a251af00eff11b52ffe2b8e46b9f632e517cad96
--- /dev/null
+++ b/drivers/pinctrl/mediatek/pinctrl-mtk-mt6878.h
@@ -0,0 +1,2248 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2023 MediaTek Inc.
+ * Author: Light Hsieh <light.hsieh@mediatek.com>
+ *
+ * Copyright (C) 2025 Igor Belwon <igor.belwon@mentallysanemainliners.org>
+ */
+
+#ifndef __PINCTRL_MTK_MT6878_H
+#define __PINCTRL_MTK_MT6878_H
+
+#include "pinctrl-paris.h"
+
+static const struct mtk_pin_desc mtk_pins_mt6878[] = {
+	MTK_PIN(
+		0, "GPIO0",
+		MTK_EINT_FUNCTION(0, 0),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "GPIO0"),
+		MTK_FUNCTION(1, "TP_GPIO0_AO"),
+		MTK_FUNCTION(2, "SRCLKENA1"),
+		MTK_FUNCTION(7, "DBG_MON_A3")
+	),
+	MTK_PIN(
+		1, "GPIO1",
+		MTK_EINT_FUNCTION(0, 1),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "GPIO1"),
+		MTK_FUNCTION(1, "TP_GPIO1_AO"),
+		MTK_FUNCTION(2, "SRCLKENA1"),
+		MTK_FUNCTION(3, "SRCLKENA2"),
+		MTK_FUNCTION(5, "IDDIG"),
+		MTK_FUNCTION(7, "DBG_MON_A4")
+	),
+	MTK_PIN(
+		2, "GPIO2",
+		MTK_EINT_FUNCTION(0, 2),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "GPIO2"),
+		MTK_FUNCTION(1, "TP_GPIO2_AO"),
+		MTK_FUNCTION(2, "SRCLKENAI0"),
+		MTK_FUNCTION(4, "SCP_DMIC_CLK"),
+		MTK_FUNCTION(5, "DMIC_CLK"),
+		MTK_FUNCTION(7, "DBG_MON_A5")
+	),
+	MTK_PIN(
+		3, "GPIO3",
+		MTK_EINT_FUNCTION(0, 3),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "GPIO3"),
+		MTK_FUNCTION(1, "TP_GPIO3_AO"),
+		MTK_FUNCTION(2, "SRCLKENAI1"),
+		MTK_FUNCTION(4, "SCP_DMIC_DAT"),
+		MTK_FUNCTION(5, "DMIC_DAT"),
+		MTK_FUNCTION(7, "DBG_MON_A6")
+	),
+	MTK_PIN(
+		4, "GPIO4",
+		MTK_EINT_FUNCTION(0, 4),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "GPIO4"),
+		MTK_FUNCTION(1, "SPI7_CLK"),
+		MTK_FUNCTION(2, "TP_GPIO4_AO"),
+		MTK_FUNCTION(3, "ANT_SEL0"),
+		MTK_FUNCTION(5, "DMIC1_CLK"),
+		MTK_FUNCTION(6, "MD_INT4"),
+		MTK_FUNCTION(7, "DBG_MON_A7")
+	),
+	MTK_PIN(
+		5, "GPIO5",
+		MTK_EINT_FUNCTION(0, 5),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "GPIO5"),
+		MTK_FUNCTION(1, "SPI7_CSB"),
+		MTK_FUNCTION(2, "TP_GPIO5_AO"),
+		MTK_FUNCTION(3, "ANT_SEL1"),
+		MTK_FUNCTION(5, "DMIC1_DAT"),
+		MTK_FUNCTION(6, "MD_INT0"),
+		MTK_FUNCTION(7, "DBG_MON_A8")
+	),
+	MTK_PIN(
+		6, "GPIO6",
+		MTK_EINT_FUNCTION(0, 6),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "GPIO6"),
+		MTK_FUNCTION(1, "SPI7_MO"),
+		MTK_FUNCTION(2, "TP_GPIO6_AO"),
+		MTK_FUNCTION(3, "ANT_SEL2"),
+		MTK_FUNCTION(4, "MD32_0_GPIO0"),
+		MTK_FUNCTION(6, "MD_INT3"),
+		MTK_FUNCTION(7, "DBG_MON_B0")
+	),
+	MTK_PIN(
+		7, "GPIO7",
+		MTK_EINT_FUNCTION(0, 7),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "GPIO7"),
+		MTK_FUNCTION(1, "SPI7_MI"),
+		MTK_FUNCTION(2, "TP_GPIO7_AO"),
+		MTK_FUNCTION(3, "ANT_SEL3"),
+		MTK_FUNCTION(4, "MD32_1_GPIO0")
+	),
+	MTK_PIN(
+		8, "GPIO8",
+		MTK_EINT_FUNCTION(0, 8),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "GPIO8"),
+		MTK_FUNCTION(2, "SCP_JTAG0_TRSTN_VLP"),
+		MTK_FUNCTION(3, "SPM_JTAG_TRSTN_VLP"),
+		MTK_FUNCTION(4, "SSPM_JTAG_TRSTN_VLP"),
+		MTK_FUNCTION(5, "HFRP_JTAG0_TRSTN"),
+		MTK_FUNCTION(6, "IO_JTAG_TRSTN"),
+		MTK_FUNCTION(7, "CONN_BGF_MCU_TDI")
+	),
+	MTK_PIN(
+		9, "GPIO9",
+		MTK_EINT_FUNCTION(0, 9),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "GPIO9"),
+		MTK_FUNCTION(2, "SCP_JTAG0_TCK_VLP"),
+		MTK_FUNCTION(3, "SPM_JTAG_TCK_VLP"),
+		MTK_FUNCTION(4, "SSPM_JTAG_TCK_VLP"),
+		MTK_FUNCTION(5, "HFRP_JTAG0_TCK"),
+		MTK_FUNCTION(6, "IO_JTAG_TCK"),
+		MTK_FUNCTION(7, "CONN_BGF_MCU_TRST_B")
+	),
+	MTK_PIN(
+		10, "GPIO10",
+		MTK_EINT_FUNCTION(0, 10),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "GPIO10"),
+		MTK_FUNCTION(2, "SCP_JTAG0_TMS_VLP"),
+		MTK_FUNCTION(3, "SPM_JTAG_TMS_VLP"),
+		MTK_FUNCTION(4, "SSPM_JTAG_TMS_VLP"),
+		MTK_FUNCTION(5, "HFRP_JTAG0_TMS"),
+		MTK_FUNCTION(6, "IO_JTAG_TMS"),
+		MTK_FUNCTION(7, "CONN_BGF_MCU_TCK")
+	),
+	MTK_PIN(
+		11, "GPIO11",
+		MTK_EINT_FUNCTION(0, 11),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "GPIO11"),
+		MTK_FUNCTION(2, "SCP_JTAG0_TDI_VLP"),
+		MTK_FUNCTION(3, "SPM_JTAG_TDI_VLP"),
+		MTK_FUNCTION(4, "SSPM_JTAG_TDI_VLP"),
+		MTK_FUNCTION(5, "HFRP_JTAG0_TDI"),
+		MTK_FUNCTION(6, "IO_JTAG_TDI"),
+		MTK_FUNCTION(7, "CONN_BGF_MCU_TDO")
+	),
+	MTK_PIN(
+		12, "GPIO12",
+		MTK_EINT_FUNCTION(0, 12),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "GPIO12"),
+		MTK_FUNCTION(2, "SCP_JTAG0_TDO_VLP"),
+		MTK_FUNCTION(3, "SPM_JTAG_TDO_VLP"),
+		MTK_FUNCTION(4, "SSPM_JTAG_TDO_VLP"),
+		MTK_FUNCTION(5, "HFRP_JTAG0_TDO"),
+		MTK_FUNCTION(6, "IO_JTAG_TDO"),
+		MTK_FUNCTION(7, "CONN_BGF_MCU_TMS")
+	),
+	MTK_PIN(
+		13, "GPIO13",
+		MTK_EINT_FUNCTION(0, 13),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "GPIO13"),
+		MTK_FUNCTION(1, "MFG_EB_JTAG_TDI"),
+		MTK_FUNCTION(2, "CONN_WF_MCU_TDI"),
+		MTK_FUNCTION(3, "SCP_JTAG0_TDI_VCORE"),
+		MTK_FUNCTION(5, "SPM_JTAG_TDI_VCORE"),
+		MTK_FUNCTION(6, "MCUPM_JTAG_TDI")
+	),
+	MTK_PIN(
+		14, "GPIO14",
+		MTK_EINT_FUNCTION(0, 14),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "GPIO14"),
+		MTK_FUNCTION(1, "MFG_EB_JTAG_TRSTN"),
+		MTK_FUNCTION(2, "CONN_WF_MCU_TRST_B"),
+		MTK_FUNCTION(3, "SCP_JTAG0_TRSTN_VCORE"),
+		MTK_FUNCTION(5, "SPM_JTAG_TRSTN_VCORE"),
+		MTK_FUNCTION(6, "MCUPM_JTAG_TRSTN")
+	),
+	MTK_PIN(
+		15, "GPIO15",
+		MTK_EINT_FUNCTION(0, 15),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "GPIO15"),
+		MTK_FUNCTION(1, "MFG_EB_JTAG_TCK"),
+		MTK_FUNCTION(2, "CONN_WF_MCU_TCK"),
+		MTK_FUNCTION(3, "SCP_JTAG0_TCK_VCORE"),
+		MTK_FUNCTION(5, "SPM_JTAG_TCK_VCORE"),
+		MTK_FUNCTION(6, "MCUPM_JTAG_TCK")
+	),
+	MTK_PIN(
+		16, "GPIO16",
+		MTK_EINT_FUNCTION(0, 16),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "GPIO16"),
+		MTK_FUNCTION(1, "MFG_EB_JTAG_TDO"),
+		MTK_FUNCTION(2, "CONN_WF_MCU_TDO"),
+		MTK_FUNCTION(3, "SCP_JTAG0_TDO_VCORE"),
+		MTK_FUNCTION(5, "SPM_JTAG_TDO_VCORE"),
+		MTK_FUNCTION(6, "MCUPM_JTAG_TDO")
+	),
+	MTK_PIN(
+		17, "GPIO17",
+		MTK_EINT_FUNCTION(0, 17),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "GPIO17"),
+		MTK_FUNCTION(1, "MFG_EB_JTAG_TMS"),
+		MTK_FUNCTION(2, "CONN_WF_MCU_TMS"),
+		MTK_FUNCTION(3, "SCP_JTAG0_TMS_VCORE"),
+		MTK_FUNCTION(5, "SPM_JTAG_TMS_VCORE"),
+		MTK_FUNCTION(6, "MCUPM_JTAG_TMS")
+	),
+	MTK_PIN(
+		18, "GPIO18",
+		MTK_EINT_FUNCTION(0, 18),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "GPIO18"),
+		MTK_FUNCTION(2, "CONN_BT_TXD"),
+		MTK_FUNCTION(3, "CONN_TCXOENA_REQ"),
+		MTK_FUNCTION(6, "GPS_L1_ELNA_EN")
+	),
+	MTK_PIN(
+		19, "GPIO19",
+		MTK_EINT_FUNCTION(0, 19),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "GPIO19"),
+		MTK_FUNCTION(1, "PWM_0"),
+		MTK_FUNCTION(3, "SDA10"),
+		MTK_FUNCTION(4, "MD32_0_GPIO0"),
+		MTK_FUNCTION(5, "EXT_FRAME_SYNC"),
+		MTK_FUNCTION(7, "DBG_MON_A9")
+	),
+	MTK_PIN(
+		20, "GPIO20",
+		MTK_EINT_FUNCTION(0, 20),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "GPIO20"),
+		MTK_FUNCTION(1, "PWM_1"),
+		MTK_FUNCTION(2, "SPI4_CLK"),
+		MTK_FUNCTION(4, "GPS_L1_ELNA_EN"),
+		MTK_FUNCTION(6, "DAP_SONIC_SWCK"),
+		MTK_FUNCTION(7, "DBG_MON_A10")
+	),
+	MTK_PIN(
+		21, "GPIO21",
+		MTK_EINT_FUNCTION(0, 21),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "GPIO21"),
+		MTK_FUNCTION(1, "PWM_2"),
+		MTK_FUNCTION(2, "SPI4_CSB"),
+		MTK_FUNCTION(4, "GPS_L5_ELNA_EN"),
+		MTK_FUNCTION(5, "IDDIG"),
+		MTK_FUNCTION(6, "DAP_SONIC_SWD"),
+		MTK_FUNCTION(7, "DBG_MON_A11")
+	),
+	MTK_PIN(
+		22, "GPIO22",
+		MTK_EINT_FUNCTION(0, 22),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "GPIO22"),
+		MTK_FUNCTION(1, "PWM_3"),
+		MTK_FUNCTION(2, "SPI4_MO"),
+		MTK_FUNCTION(4, "EXT_FRAME_SYNC"),
+		MTK_FUNCTION(5, "VBUSVALID"),
+		MTK_FUNCTION(6, "DAP_MD32_SWCK"),
+		MTK_FUNCTION(7, "DBG_MON_A12")
+	),
+	MTK_PIN(
+		23, "GPIO23",
+		MTK_EINT_FUNCTION(0, 23),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "GPIO23"),
+		MTK_FUNCTION(2, "SPI4_MI"),
+		MTK_FUNCTION(4, "MD32_1_GPIO0"),
+		MTK_FUNCTION(5, "USB_DRVVBUS"),
+		MTK_FUNCTION(6, "DAP_MD32_SWD"),
+		MTK_FUNCTION(7, "DBG_MON_A13")
+	),
+	MTK_PIN(
+		24, "GPIO24",
+		MTK_EINT_FUNCTION(0, 24),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "GPIO24"),
+		MTK_FUNCTION(1, "GPS_L5_ELNA_EN"),
+		MTK_FUNCTION(2, "SCL12"),
+		MTK_FUNCTION(3, "SCL10"),
+		MTK_FUNCTION(4, "CMVREF0"),
+		MTK_FUNCTION(5, "CONN_WIFI_TXD"),
+		MTK_FUNCTION(6, "CMFLASH0"),
+		MTK_FUNCTION(7, "DBG_MON_A14")
+	),
+	MTK_PIN(
+		25, "GPIO25",
+		MTK_EINT_FUNCTION(0, 25),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "GPIO25"),
+		MTK_FUNCTION(1, "SPI6_CLK"),
+		MTK_FUNCTION(2, "SCL11"),
+		MTK_FUNCTION(4, "CMVREF1"),
+		MTK_FUNCTION(6, "CMFLASH1"),
+		MTK_FUNCTION(7, "DBG_MON_A15")
+	),
+	MTK_PIN(
+		26, "GPIO26",
+		MTK_EINT_FUNCTION(0, 26),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "GPIO26"),
+		MTK_FUNCTION(1, "SPI6_CSB"),
+		MTK_FUNCTION(2, "SDA11"),
+		MTK_FUNCTION(3, "USB_DRVVBUS"),
+		MTK_FUNCTION(4, "CMVREF2"),
+		MTK_FUNCTION(6, "CMFLASH2"),
+		MTK_FUNCTION(7, "DBG_MON_A16")
+	),
+	MTK_PIN(
+		27, "GPIO27",
+		MTK_EINT_FUNCTION(0, 27),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "GPIO27"),
+		MTK_FUNCTION(1, "SPI6_MO"),
+		MTK_FUNCTION(3, "VBUSVALID"),
+		MTK_FUNCTION(4, "CMVREF3"),
+		MTK_FUNCTION(5, "DMIC1_CLK"),
+		MTK_FUNCTION(6, "CMFLASH3"),
+		MTK_FUNCTION(7, "DBG_MON_A17")
+	),
+	MTK_PIN(
+		28, "GPIO28",
+		MTK_EINT_FUNCTION(0, 28),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "GPIO28"),
+		MTK_FUNCTION(1, "SPI6_MI"),
+		MTK_FUNCTION(3, "IDDIG"),
+		MTK_FUNCTION(5, "DMIC1_DAT"),
+		MTK_FUNCTION(6, "CMFLASH0"),
+		MTK_FUNCTION(7, "DBG_MON_A18")
+	),
+	MTK_PIN(
+		29, "GPIO29",
+		MTK_EINT_FUNCTION(0, 29),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "GPIO29"),
+		MTK_FUNCTION(1, "I2SIN2_BCK"),
+		MTK_FUNCTION(2, "TP_UTXD1_VCORE"),
+		MTK_FUNCTION(3, "MD_UTXD0"),
+		MTK_FUNCTION(4, "SSPM_UTXD_AO_VCORE"),
+		MTK_FUNCTION(5, "MD32_1_TXD"),
+		MTK_FUNCTION(6, "CONN_BT_TXD"),
+		MTK_FUNCTION(7, "PTA_TXD")
+	),
+	MTK_PIN(
+		30, "GPIO30",
+		MTK_EINT_FUNCTION(0, 30),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "GPIO30"),
+		MTK_FUNCTION(1, "I2SIN2_LRCK"),
+		MTK_FUNCTION(2, "TP_URXD1_VCORE"),
+		MTK_FUNCTION(3, "MD_URXD0"),
+		MTK_FUNCTION(4, "SSPM_URXD_AO_VCORE"),
+		MTK_FUNCTION(5, "MD32_1_RXD"),
+		MTK_FUNCTION(7, "PTA_RXD")
+	),
+	MTK_PIN(
+		31, "GPIO31",
+		MTK_EINT_FUNCTION(0, 31),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "GPIO31"),
+		MTK_FUNCTION(1, "I2SOUT2_DO"),
+		MTK_FUNCTION(2, "TP_UTXD2_VCORE"),
+		MTK_FUNCTION(3, "MD_UTXD1"),
+		MTK_FUNCTION(4, "HFRP_UTXD1"),
+		MTK_FUNCTION(5, "MD32_0_TXD"),
+		MTK_FUNCTION(6, "CONN_WIFI_TXD"),
+		MTK_FUNCTION(7, "CONN_BGF_UART0_TXD")
+	),
+	MTK_PIN(
+		32, "GPIO32",
+		MTK_EINT_FUNCTION(0, 32),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "GPIO32"),
+		MTK_FUNCTION(1, "I2SIN2_DI"),
+		MTK_FUNCTION(2, "TP_URXD2_VCORE"),
+		MTK_FUNCTION(3, "MD_URXD1"),
+		MTK_FUNCTION(4, "HFRP_URXD1"),
+		MTK_FUNCTION(5, "MD32_0_RXD"),
+		MTK_FUNCTION(7, "CONN_BGF_UART0_RXD")
+	),
+	MTK_PIN(
+		33, "GPIO33",
+		MTK_EINT_FUNCTION(0, 33),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "GPIO33"),
+		MTK_FUNCTION(1, "ANT_SEL0"),
+		MTK_FUNCTION(3, "GPS_L1_ELNA_EN"),
+		MTK_FUNCTION(4, "SCL1"),
+		MTK_FUNCTION(5, "CONN_BPI_BUS18_ANT1"),
+		MTK_FUNCTION(6, "MD_UCTS0")
+	),
+	MTK_PIN(
+		34, "GPIO34",
+		MTK_EINT_FUNCTION(0, 34),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "GPIO34"),
+		MTK_FUNCTION(1, "ANT_SEL1"),
+		MTK_FUNCTION(3, "GPS_L5_ELNA_EN"),
+		MTK_FUNCTION(4, "SDA1"),
+		MTK_FUNCTION(5, "CONN_BPI_BUS19_ANT2"),
+		MTK_FUNCTION(6, "MD_URTS0")
+	),
+	MTK_PIN(
+		35, "GPIO35",
+		MTK_EINT_FUNCTION(0, 35),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "GPIO35"),
+		MTK_FUNCTION(1, "ANT_SEL2"),
+		MTK_FUNCTION(2, "SSPM_JTAG_TCK_VCORE"),
+		MTK_FUNCTION(3, "UDI_TCK"),
+		MTK_FUNCTION(5, "CONN_BPI_BUS20_ANT3"),
+		MTK_FUNCTION(6, "MD_UCTS1")
+	),
+	MTK_PIN(
+		36, "GPIO36",
+		MTK_EINT_FUNCTION(0, 36),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "GPIO36"),
+		MTK_FUNCTION(1, "ANT_SEL3"),
+		MTK_FUNCTION(2, "SSPM_JTAG_TRSTN_VCORE"),
+		MTK_FUNCTION(3, "UDI_NTRST"),
+		MTK_FUNCTION(5, "CONN_BPI_BUS21_ANT4"),
+		MTK_FUNCTION(6, "MD_URTS1")
+	),
+	MTK_PIN(
+		37, "GPIO37",
+		MTK_EINT_FUNCTION(0, 37),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "GPIO37"),
+		MTK_FUNCTION(1, "ANT_SEL4"),
+		MTK_FUNCTION(2, "SSPM_JTAG_TDI_VCORE"),
+		MTK_FUNCTION(3, "UDI_TDI"),
+		MTK_FUNCTION(6, "TP_UCTS1_VCORE")
+	),
+	MTK_PIN(
+		38, "GPIO38",
+		MTK_EINT_FUNCTION(0, 38),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "GPIO38"),
+		MTK_FUNCTION(1, "ANT_SEL5"),
+		MTK_FUNCTION(2, "SSPM_JTAG_TMS_VCORE"),
+		MTK_FUNCTION(3, "UDI_TMS"),
+		MTK_FUNCTION(6, "TP_URTS1_VCORE")
+	),
+	MTK_PIN(
+		39, "GPIO39",
+		MTK_EINT_FUNCTION(0, 39),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "GPIO39"),
+		MTK_FUNCTION(1, "ANT_SEL6"),
+		MTK_FUNCTION(2, "SSPM_JTAG_TDO_VCORE"),
+		MTK_FUNCTION(3, "UDI_TDO"),
+		MTK_FUNCTION(5, "CLKM3")
+	),
+	MTK_PIN(
+		40, "GPIO40",
+		MTK_EINT_FUNCTION(0, 40),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "GPIO40"),
+		MTK_FUNCTION(1, "ANT_SEL7"),
+		MTK_FUNCTION(2, "PMSR_SMAP"),
+		MTK_FUNCTION(3, "CONN_TCXOENA_REQ"),
+		MTK_FUNCTION(4, "CONN_WIFI_TXD"),
+		MTK_FUNCTION(5, "GPS_PPS")
+	),
+	MTK_PIN(
+		41, "GPIO41",
+		MTK_EINT_FUNCTION(0, 41),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "GPIO41"),
+		MTK_FUNCTION(1, "I2SIN1_MCK"),
+		MTK_FUNCTION(2, "IDDIG"),
+		MTK_FUNCTION(3, "GPS_PPS"),
+		MTK_FUNCTION(4, "HFRP_UCTS1"),
+		MTK_FUNCTION(5, "TP_UCTS2_VCORE"),
+		MTK_FUNCTION(6, "ANT_SEL8"),
+		MTK_FUNCTION(7, "DBG_MON_B1")
+	),
+	MTK_PIN(
+		42, "GPIO42",
+		MTK_EINT_FUNCTION(0, 42),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "GPIO42"),
+		MTK_FUNCTION(1, "I2SIN1_BCK"),
+		MTK_FUNCTION(2, "I2SIN4_BCK"),
+		MTK_FUNCTION(4, "HFRP_URTS1"),
+		MTK_FUNCTION(5, "TP_URTS2_VCORE"),
+		MTK_FUNCTION(6, "ANT_SEL9"),
+		MTK_FUNCTION(7, "DBG_MON_B2")
+	),
+	MTK_PIN(
+		43, "GPIO43",
+		MTK_EINT_FUNCTION(0, 43),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "GPIO43"),
+		MTK_FUNCTION(1, "I2SIN1_LRCK"),
+		MTK_FUNCTION(2, "I2SIN4_LRCK"),
+		MTK_FUNCTION(6, "ANT_SEL10"),
+		MTK_FUNCTION(7, "DBG_MON_B3")
+	),
+	MTK_PIN(
+		44, "GPIO44",
+		MTK_EINT_FUNCTION(0, 44),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "GPIO44"),
+		MTK_FUNCTION(1, "I2SOUT1_DO"),
+		MTK_FUNCTION(2, "I2SOUT4_DATA0"),
+		MTK_FUNCTION(6, "ANT_SEL11"),
+		MTK_FUNCTION(7, "DBG_MON_B4")
+	),
+	MTK_PIN(
+		45, "GPIO45",
+		MTK_EINT_FUNCTION(0, 45),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "GPIO45"),
+		MTK_FUNCTION(1, "I2SIN1_DI"),
+		MTK_FUNCTION(2, "I2SIN4_DATA0"),
+		MTK_FUNCTION(5, "AGPS_SYNC"),
+		MTK_FUNCTION(6, "ANT_SEL12"),
+		MTK_FUNCTION(7, "DBG_MON_B5")
+	),
+	MTK_PIN(
+		46, "GPIO46",
+		MTK_EINT_FUNCTION(0, 46),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "GPIO46"),
+		MTK_FUNCTION(1, "MD_INT1_C2K_UIM0_HOT_PLUG"),
+		MTK_FUNCTION(2, "MD_INT2_C2K_UIM1_HOT_PLUG"),
+		MTK_FUNCTION(3, "SRCLKENAI0"),
+		MTK_FUNCTION(5, "SSPM_UTXD_AO_VLP"),
+		MTK_FUNCTION(6, "MD_MCIF_UTXD0"),
+		MTK_FUNCTION(7, "DBG_MON_B6")
+	),
+	MTK_PIN(
+		47, "GPIO47",
+		MTK_EINT_FUNCTION(0, 47),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "GPIO47"),
+		MTK_FUNCTION(1, "MD_INT2_C2K_UIM1_HOT_PLUG"),
+		MTK_FUNCTION(2, "MD_INT1_C2K_UIM0_HOT_PLUG"),
+		MTK_FUNCTION(3, "SRCLKENAI1"),
+		MTK_FUNCTION(4, "SRCLKENA1"),
+		MTK_FUNCTION(5, "SSPM_URXD_AO_VLP"),
+		MTK_FUNCTION(6, "MD_MCIF_URXD0"),
+		MTK_FUNCTION(7, "DBG_MON_B7")
+	),
+	MTK_PIN(
+		48, "GPIO48",
+		MTK_EINT_FUNCTION(0, 48),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "GPIO48"),
+		MTK_FUNCTION(1, "UTXD0"),
+		MTK_FUNCTION(3, "MD_UTXD1"),
+		MTK_FUNCTION(4, "HFRP_UTXD1"),
+		MTK_FUNCTION(5, "MD32_0_TXD")
+	),
+	MTK_PIN(
+		49, "GPIO49",
+		MTK_EINT_FUNCTION(0, 49),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "GPIO49"),
+		MTK_FUNCTION(1, "URXD0"),
+		MTK_FUNCTION(3, "MD_URXD1"),
+		MTK_FUNCTION(4, "HFRP_URXD1"),
+		MTK_FUNCTION(5, "MD32_0_RXD")
+	),
+	MTK_PIN(
+		50, "GPIO50",
+		MTK_EINT_FUNCTION(0, 50),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "GPIO50"),
+		MTK_FUNCTION(1, "MD_UTXD0"),
+		MTK_FUNCTION(2, "TP_UTXD1_VLP"),
+		MTK_FUNCTION(3, "CONN_BGF_UART0_TXD"),
+		MTK_FUNCTION(4, "SSPM_UTXD_AO_VLP"),
+		MTK_FUNCTION(5, "MD_MCIF_UTXD0"),
+		MTK_FUNCTION(6, "TP_UTXD2_VLP"),
+		MTK_FUNCTION(7, "UTXD1")
+	),
+	MTK_PIN(
+		51, "GPIO51",
+		MTK_EINT_FUNCTION(0, 51),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "GPIO51"),
+		MTK_FUNCTION(1, "MD_URXD0"),
+		MTK_FUNCTION(2, "TP_URXD1_VLP"),
+		MTK_FUNCTION(3, "CONN_BGF_UART0_RXD"),
+		MTK_FUNCTION(4, "SSPM_URXD_AO_VLP"),
+		MTK_FUNCTION(5, "MD_MCIF_URXD0"),
+		MTK_FUNCTION(6, "TP_URXD2_VLP"),
+		MTK_FUNCTION(7, "URXD1")
+	),
+	MTK_PIN(
+		52, "GPIO52",
+		MTK_EINT_FUNCTION(0, 52),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "GPIO52"),
+		MTK_FUNCTION(1, "KPROW0"),
+		MTK_FUNCTION(2, "CMFLASH0"),
+		MTK_FUNCTION(3, "SDA12"),
+		MTK_FUNCTION(4, "DSI_TE1")
+	),
+	MTK_PIN(
+		53, "GPIO53",
+		MTK_EINT_FUNCTION(0, 53),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "GPIO53"),
+		MTK_FUNCTION(1, "KPROW1"),
+		MTK_FUNCTION(2, "CMFLASH1"),
+		MTK_FUNCTION(3, "SCL12"),
+		MTK_FUNCTION(4, "LCM_RST1"),
+		MTK_FUNCTION(6, "EXTIF0_ACT")
+	),
+	MTK_PIN(
+		54, "GPIO54",
+		MTK_EINT_FUNCTION(0, 54),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "GPIO54"),
+		MTK_FUNCTION(1, "KPCOL0_VLP"),
+		MTK_FUNCTION(7, "KPCOL0_VLP")
+	),
+	MTK_PIN(
+		55, "GPIO55",
+		MTK_EINT_FUNCTION(0, 55),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "GPIO55"),
+		MTK_FUNCTION(1, "KPCOL1"),
+		MTK_FUNCTION(3, "SDA12"),
+		MTK_FUNCTION(4, "DISP_PWM1"),
+		MTK_FUNCTION(7, "JTRSTN_SEL1_VCORE")
+	),
+	MTK_PIN(
+		56, "GPIO56",
+		MTK_EINT_FUNCTION(0, 56),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "GPIO56"),
+		MTK_FUNCTION(1, "SPI0_CLK"),
+		MTK_FUNCTION(7, "JTCK_SEL1_VCORE")
+	),
+	MTK_PIN(
+		57, "GPIO57",
+		MTK_EINT_FUNCTION(0, 57),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "GPIO57"),
+		MTK_FUNCTION(1, "SPI0_CSB"),
+		MTK_FUNCTION(7, "JTMS_SEL1_VCORE")
+	),
+	MTK_PIN(
+		58, "GPIO58",
+		MTK_EINT_FUNCTION(0, 58),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "GPIO58"),
+		MTK_FUNCTION(1, "SPI0_MO"),
+		MTK_FUNCTION(7, "JTDO_SEL1_VCORE")
+	),
+	MTK_PIN(
+		59, "GPIO59",
+		MTK_EINT_FUNCTION(0, 59),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "GPIO59"),
+		MTK_FUNCTION(1, "SPI0_MI"),
+		MTK_FUNCTION(7, "JTDI_SEL1_VCORE")
+	),
+	MTK_PIN(
+		60, "GPIO60",
+		MTK_EINT_FUNCTION(0, 60),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "GPIO60"),
+		MTK_FUNCTION(1, "SCP_SPI1_CK"),
+		MTK_FUNCTION(2, "SPI1_CLK"),
+		MTK_FUNCTION(4, "SCP_SCL3"),
+		MTK_FUNCTION(5, "TP_GPIO0_AO"),
+		MTK_FUNCTION(6, "UTXD0"),
+		MTK_FUNCTION(7, "TP_UTXD2_VLP")
+	),
+	MTK_PIN(
+		61, "GPIO61",
+		MTK_EINT_FUNCTION(0, 61),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "GPIO61"),
+		MTK_FUNCTION(1, "SCP_SPI1_CS"),
+		MTK_FUNCTION(2, "SPI1_CSB"),
+		MTK_FUNCTION(5, "TP_GPIO1_AO"),
+		MTK_FUNCTION(6, "URXD0"),
+		MTK_FUNCTION(7, "TP_URXD2_VLP")
+	),
+	MTK_PIN(
+		62, "GPIO62",
+		MTK_EINT_FUNCTION(0, 62),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "GPIO62"),
+		MTK_FUNCTION(1, "SCP_SPI1_MO"),
+		MTK_FUNCTION(2, "SPI1_MO"),
+		MTK_FUNCTION(3, "SCP_SCL3"),
+		MTK_FUNCTION(4, "SCP_SDA3"),
+		MTK_FUNCTION(5, "TP_GPIO2_AO"),
+		MTK_FUNCTION(7, "DBG_MON_B29")
+	),
+	MTK_PIN(
+		63, "GPIO63",
+		MTK_EINT_FUNCTION(0, 63),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "GPIO63"),
+		MTK_FUNCTION(1, "SCP_SPI1_MI"),
+		MTK_FUNCTION(2, "SPI1_MI"),
+		MTK_FUNCTION(3, "SCP_SDA3"),
+		MTK_FUNCTION(5, "TP_GPIO3_AO"),
+		MTK_FUNCTION(7, "DBG_MON_B30")
+	),
+	MTK_PIN(
+		64, "GPIO64",
+		MTK_EINT_FUNCTION(0, 64),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "GPIO64"),
+		MTK_FUNCTION(1, "SCP_SPI2_CK"),
+		MTK_FUNCTION(2, "SPI2_CLK"),
+		MTK_FUNCTION(4, "SCP_SCL2"),
+		MTK_FUNCTION(5, "TP_GPIO4_AO")
+	),
+	MTK_PIN(
+		65, "GPIO65",
+		MTK_EINT_FUNCTION(0, 65),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "GPIO65"),
+		MTK_FUNCTION(1, "SCP_SPI2_CS"),
+		MTK_FUNCTION(2, "SPI2_CSB"),
+		MTK_FUNCTION(5, "TP_GPIO5_AO"),
+		MTK_FUNCTION(7, "DBG_MON_B31")
+	),
+	MTK_PIN(
+		66, "GPIO66",
+		MTK_EINT_FUNCTION(0, 66),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "GPIO66"),
+		MTK_FUNCTION(1, "SCP_SPI2_MO"),
+		MTK_FUNCTION(2, "SPI2_MO"),
+		MTK_FUNCTION(3, "SCP_SCL2"),
+		MTK_FUNCTION(4, "SCP_SDA2"),
+		MTK_FUNCTION(5, "TP_GPIO6_AO")
+	),
+	MTK_PIN(
+		67, "GPIO67",
+		MTK_EINT_FUNCTION(0, 67),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "GPIO67"),
+		MTK_FUNCTION(1, "SCP_SPI2_MI"),
+		MTK_FUNCTION(2, "SPI2_MI"),
+		MTK_FUNCTION(3, "SCP_SDA2"),
+		MTK_FUNCTION(5, "TP_GPIO7_AO")
+	),
+	MTK_PIN(
+		68, "GPIO68",
+		MTK_EINT_FUNCTION(0, 68),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "GPIO68"),
+		MTK_FUNCTION(1, "SCP_SPI3_CK"),
+		MTK_FUNCTION(2, "SPI3_CLK"),
+		MTK_FUNCTION(3, "MD_INT4"),
+		MTK_FUNCTION(4, "SCP_SCL4"),
+		MTK_FUNCTION(5, "TP_GPIO8_AO"),
+		MTK_FUNCTION(7, "DBG_MON_A19")
+	),
+	MTK_PIN(
+		69, "GPIO69",
+		MTK_EINT_FUNCTION(0, 69),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "GPIO69"),
+		MTK_FUNCTION(1, "SCP_SPI3_CS"),
+		MTK_FUNCTION(2, "SPI3_CSB"),
+		MTK_FUNCTION(3, "MD_INT3"),
+		MTK_FUNCTION(5, "TP_GPIO9_AO"),
+		MTK_FUNCTION(7, "DBG_MON_A20")
+	),
+	MTK_PIN(
+		70, "GPIO70",
+		MTK_EINT_FUNCTION(0, 70),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "GPIO70"),
+		MTK_FUNCTION(1, "SCP_SPI3_MO"),
+		MTK_FUNCTION(2, "SPI3_MO"),
+		MTK_FUNCTION(3, "SCP_SCL4"),
+		MTK_FUNCTION(4, "SCP_SDA4"),
+		MTK_FUNCTION(5, "TP_GPIO10_AO"),
+		MTK_FUNCTION(7, "DBG_MON_A21")
+	),
+	MTK_PIN(
+		71, "GPIO71",
+		MTK_EINT_FUNCTION(0, 71),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "GPIO71"),
+		MTK_FUNCTION(1, "SCP_SPI3_MI"),
+		MTK_FUNCTION(2, "SPI3_MI"),
+		MTK_FUNCTION(3, "SCP_SDA4"),
+		MTK_FUNCTION(4, "MD_INT0"),
+		MTK_FUNCTION(5, "TP_GPIO11_AO"),
+		MTK_FUNCTION(7, "DBG_MON_A22")
+	),
+	MTK_PIN(
+		72, "GPIO72",
+		MTK_EINT_FUNCTION(0, 72),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "GPIO72"),
+		MTK_FUNCTION(1, "SPI5_CLK"),
+		MTK_FUNCTION(2, "SCP_SPI0_CK"),
+		MTK_FUNCTION(3, "UCTS2"),
+		MTK_FUNCTION(4, "MBISTREADEN_TRIGGER"),
+		MTK_FUNCTION(5, "TP_GPIO12_AO"),
+		MTK_FUNCTION(6, "EXTIF0_ACT"),
+		MTK_FUNCTION(7, "DAP_SONIC_SWCK")
+	),
+	MTK_PIN(
+		73, "GPIO73",
+		MTK_EINT_FUNCTION(0, 73),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "GPIO73"),
+		MTK_FUNCTION(1, "SPI5_CSB"),
+		MTK_FUNCTION(2, "SCP_SPI0_CS"),
+		MTK_FUNCTION(3, "URTS2"),
+		MTK_FUNCTION(4, "MBISTWRITEEN_TRIGGER"),
+		MTK_FUNCTION(5, "TP_GPIO13_AO"),
+		MTK_FUNCTION(6, "EXTIF0_PRI"),
+		MTK_FUNCTION(7, "DAP_SONIC_SWD")
+	),
+	MTK_PIN(
+		74, "GPIO74",
+		MTK_EINT_FUNCTION(0, 74),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "GPIO74"),
+		MTK_FUNCTION(1, "SPI5_MO"),
+		MTK_FUNCTION(2, "SCP_SPI0_MO"),
+		MTK_FUNCTION(3, "UTXD2"),
+		MTK_FUNCTION(4, "TP_UTXD2_VCORE"),
+		MTK_FUNCTION(5, "TP_GPIO14_AO"),
+		MTK_FUNCTION(6, "EXTIF0_GNT_B"),
+		MTK_FUNCTION(7, "DAP_MD32_SWCK")
+	),
+	MTK_PIN(
+		75, "GPIO75",
+		MTK_EINT_FUNCTION(0, 75),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "GPIO75"),
+		MTK_FUNCTION(1, "SPI5_MI"),
+		MTK_FUNCTION(2, "SCP_SPI0_MI"),
+		MTK_FUNCTION(3, "URXD2"),
+		MTK_FUNCTION(4, "TP_URXD2_VCORE"),
+		MTK_FUNCTION(5, "TP_GPIO15_AO"),
+		MTK_FUNCTION(7, "DAP_MD32_SWD")
+	),
+	MTK_PIN(
+		76, "GPIO76",
+		MTK_EINT_FUNCTION(0, 76),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "GPIO76"),
+		MTK_FUNCTION(1, "AP_GOOD"),
+		MTK_FUNCTION(3, "CONN_WIFI_TXD"),
+		MTK_FUNCTION(4, "GPS_PPS"),
+		MTK_FUNCTION(5, "PMSR_SMAP"),
+		MTK_FUNCTION(6, "AGPS_SYNC")
+	),
+	MTK_PIN(
+		77, "GPIO77",
+		MTK_EINT_FUNCTION(0, 77),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "GPIO77"),
+		MTK_FUNCTION(1, "MSDC1_CLK"),
+		MTK_FUNCTION(2, "MD1_SIM2_SCLK"),
+		MTK_FUNCTION(3, "UDI_TCK"),
+		MTK_FUNCTION(4, "CONN_DSP_JCK"),
+		MTK_FUNCTION(6, "TSFDC_EN"),
+		MTK_FUNCTION(7, "SSPM_JTAG_TCK_VCORE")
+	),
+	MTK_PIN(
+		78, "GPIO78",
+		MTK_EINT_FUNCTION(0, 78),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "GPIO78"),
+		MTK_FUNCTION(1, "MSDC1_CMD"),
+		MTK_FUNCTION(2, "CONN_WF_MCU_AICE_TMSC"),
+		MTK_FUNCTION(3, "UDI_TMS"),
+		MTK_FUNCTION(4, "CONN_DSP_JMS"),
+		MTK_FUNCTION(6, "TSFDC_VCO_RST"),
+		MTK_FUNCTION(7, "SSPM_JTAG_TMS_VCORE")
+	),
+	MTK_PIN(
+		79, "GPIO79",
+		MTK_EINT_FUNCTION(0, 79),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "GPIO79"),
+		MTK_FUNCTION(1, "MSDC1_DAT0"),
+		MTK_FUNCTION(2, "MD1_SIM2_SRST"),
+		MTK_FUNCTION(3, "UDI_TDI"),
+		MTK_FUNCTION(4, "CONN_DSP_JDI"),
+		MTK_FUNCTION(6, "TSFDC_TSSEL2"),
+		MTK_FUNCTION(7, "SSPM_JTAG_TDI_VCORE")
+	),
+	MTK_PIN(
+		80, "GPIO80",
+		MTK_EINT_FUNCTION(0, 80),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "GPIO80"),
+		MTK_FUNCTION(1, "MSDC1_DAT1"),
+		MTK_FUNCTION(2, "MD1_SIM2_SIO"),
+		MTK_FUNCTION(3, "UDI_TDO"),
+		MTK_FUNCTION(4, "CONN_DSP_JDO"),
+		MTK_FUNCTION(6, "TSFDC_TSSEL1"),
+		MTK_FUNCTION(7, "SSPM_JTAG_TDO_VCORE")
+	),
+	MTK_PIN(
+		81, "GPIO81",
+		MTK_EINT_FUNCTION(0, 81),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "GPIO81"),
+		MTK_FUNCTION(1, "MSDC1_DAT2"),
+		MTK_FUNCTION(2, "CONN_WF_MCU_AICE_TCKC"),
+		MTK_FUNCTION(3, "UDI_NTRST"),
+		MTK_FUNCTION(4, "CONN_BGF_MCU_AICE_TCKC"),
+		MTK_FUNCTION(5, "MIPI3_D_SDATA"),
+		MTK_FUNCTION(6, "TSFDC_TSSEL0"),
+		MTK_FUNCTION(7, "SSPM_JTAG_TRSTN_VCORE")
+	),
+	MTK_PIN(
+		82, "GPIO82",
+		MTK_EINT_FUNCTION(0, 82),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "GPIO82"),
+		MTK_FUNCTION(1, "MSDC1_DAT3"),
+		MTK_FUNCTION(3, "CONN_BGF_MCU_AICE_TMSC"),
+		MTK_FUNCTION(4, "CONN_DSP_JINTP"),
+		MTK_FUNCTION(5, "MIPI3_D_SCLK"),
+		MTK_FUNCTION(6, "TSFDC_RCK_SELB")
+	),
+	MTK_PIN(
+		83, "GPIO83",
+		MTK_EINT_FUNCTION(0, 83),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "GPIO83"),
+		MTK_FUNCTION(1, "MD1_SIM1_SCLK"),
+		MTK_FUNCTION(6, "TSFDC_26M")
+	),
+	MTK_PIN(
+		84, "GPIO84",
+		MTK_EINT_FUNCTION(0, 84),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "GPIO84"),
+		MTK_FUNCTION(1, "MD1_SIM1_SRST"),
+		MTK_FUNCTION(3, "SPM_JTAG_TCK_VCORE"),
+		MTK_FUNCTION(4, "APU_JTAG_TCK"),
+		MTK_FUNCTION(6, "TSFDC_SDO"),
+		MTK_FUNCTION(7, "CONN_DSP_L5_JCK")
+	),
+	MTK_PIN(
+		85, "GPIO85",
+		MTK_EINT_FUNCTION(0, 85),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "GPIO85"),
+		MTK_FUNCTION(1, "MD1_SIM1_SIO"),
+		MTK_FUNCTION(3, "SPM_JTAG_TRSTN_VCORE"),
+		MTK_FUNCTION(4, "APU_JTAG_TRST"),
+		MTK_FUNCTION(6, "TSFDC_FOUT"),
+		MTK_FUNCTION(7, "CONN_DSP_L5_JINTP")
+	),
+	MTK_PIN(
+		86, "GPIO86",
+		MTK_EINT_FUNCTION(0, 86),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "GPIO86"),
+		MTK_FUNCTION(1, "MD1_SIM2_SCLK"),
+		MTK_FUNCTION(3, "SPM_JTAG_TDI_VCORE"),
+		MTK_FUNCTION(4, "APU_JTAG_TDI"),
+		MTK_FUNCTION(6, "TSFDC_SCK"),
+		MTK_FUNCTION(7, "CONN_DSP_L5_JDI")
+	),
+	MTK_PIN(
+		87, "GPIO87",
+		MTK_EINT_FUNCTION(0, 87),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "GPIO87"),
+		MTK_FUNCTION(1, "MD1_SIM2_SRST"),
+		MTK_FUNCTION(3, "SPM_JTAG_TMS_VCORE"),
+		MTK_FUNCTION(4, "APU_JTAG_TMS"),
+		MTK_FUNCTION(6, "TSFDC_SDI"),
+		MTK_FUNCTION(7, "CONN_DSP_L5_JMS")
+	),
+	MTK_PIN(
+		88, "GPIO88",
+		MTK_EINT_FUNCTION(0, 88),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "GPIO88"),
+		MTK_FUNCTION(1, "MD1_SIM2_SIO"),
+		MTK_FUNCTION(3, "SPM_JTAG_TDO_VCORE"),
+		MTK_FUNCTION(4, "APU_JTAG_TDO"),
+		MTK_FUNCTION(6, "TSFDC_SCF"),
+		MTK_FUNCTION(7, "CONN_DSP_L5_JDO")
+	),
+	MTK_PIN(
+		89, "GPIO89",
+		MTK_EINT_FUNCTION(0, 89),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "GPIO89"),
+		MTK_FUNCTION(1, "DSI_TE"),
+		MTK_FUNCTION(7, "DBG_MON_B8")
+	),
+	MTK_PIN(
+		90, "GPIO90",
+		MTK_EINT_FUNCTION(0, 90),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "GPIO90"),
+		MTK_FUNCTION(1, "LCM_RST"),
+		MTK_FUNCTION(7, "DBG_MON_B9")
+	),
+	MTK_PIN(
+		91, "GPIO91",
+		MTK_EINT_FUNCTION(0, 91),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "GPIO91"),
+		MTK_FUNCTION(1, "DISP_PWM"),
+		MTK_FUNCTION(7, "DBG_MON_B10")
+	),
+	MTK_PIN(
+		92, "GPIO92",
+		MTK_EINT_FUNCTION(0, 92),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "GPIO92"),
+		MTK_FUNCTION(1, "CMMCLK0"),
+		MTK_FUNCTION(7, "DBG_MON_A23")
+	),
+	MTK_PIN(
+		93, "GPIO93",
+		MTK_EINT_FUNCTION(0, 93),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "GPIO93"),
+		MTK_FUNCTION(1, "CMMCLK1"),
+		MTK_FUNCTION(7, "DBG_MON_A24")
+	),
+	MTK_PIN(
+		94, "GPIO94",
+		MTK_EINT_FUNCTION(0, 94),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "GPIO94"),
+		MTK_FUNCTION(1, "CMMCLK2"),
+		MTK_FUNCTION(7, "DBG_MON_A25")
+	),
+	MTK_PIN(
+		95, "GPIO95",
+		MTK_EINT_FUNCTION(0, 95),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "GPIO95"),
+		MTK_FUNCTION(1, "CMMCLK3"),
+		MTK_FUNCTION(5, "MD32_1_TXD"),
+		MTK_FUNCTION(6, "PTA_TXD"),
+		MTK_FUNCTION(7, "DBG_MON_A26")
+	),
+	MTK_PIN(
+		96, "GPIO96",
+		MTK_EINT_FUNCTION(0, 96),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "GPIO96"),
+		MTK_FUNCTION(1, "CMMCLK4"),
+		MTK_FUNCTION(5, "MD32_1_RXD"),
+		MTK_FUNCTION(6, "PTA_RXD"),
+		MTK_FUNCTION(7, "DBG_MON_A27")
+	),
+	MTK_PIN(
+		97, "GPIO97",
+		MTK_EINT_FUNCTION(0, 97),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "GPIO97"),
+		MTK_FUNCTION(1, "MD_UCNT_A_TGL")
+	),
+	MTK_PIN(
+		98, "GPIO98",
+		MTK_EINT_FUNCTION(0, 98),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "GPIO98"),
+		MTK_FUNCTION(1, "DIGRF_IRQ")
+	),
+	MTK_PIN(
+		99, "GPIO99",
+		MTK_EINT_FUNCTION(0, 99),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "GPIO99"),
+		MTK_FUNCTION(1, "BPI_BUS0"),
+		MTK_FUNCTION(4, "MFG_TSFDC_EN"),
+		MTK_FUNCTION(6, "ANT_SEL0"),
+		MTK_FUNCTION(7, "DBG_MON_B11")
+	),
+	MTK_PIN(
+		100, "GPIO100",
+		MTK_EINT_FUNCTION(0, 100),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "GPIO100"),
+		MTK_FUNCTION(1, "BPI_BUS1"),
+		MTK_FUNCTION(4, "MFG_TSFDC_VCO_RST"),
+		MTK_FUNCTION(6, "ANT_SEL1"),
+		MTK_FUNCTION(7, "DBG_MON_B12")
+	),
+	MTK_PIN(
+		101, "GPIO101",
+		MTK_EINT_FUNCTION(0, 101),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "GPIO101"),
+		MTK_FUNCTION(1, "BPI_BUS2"),
+		MTK_FUNCTION(3, "DMIC1_CLK"),
+		MTK_FUNCTION(4, "MFG_TSFDC_TSSEL2"),
+		MTK_FUNCTION(6, "ANT_SEL2"),
+		MTK_FUNCTION(7, "DBG_MON_B13")
+	),
+	MTK_PIN(
+		102, "GPIO102",
+		MTK_EINT_FUNCTION(0, 102),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "GPIO102"),
+		MTK_FUNCTION(1, "BPI_BUS3"),
+		MTK_FUNCTION(3, "DMIC1_DAT"),
+		MTK_FUNCTION(4, "MFG_TSFDC_TSSEL1"),
+		MTK_FUNCTION(6, "ANT_SEL3"),
+		MTK_FUNCTION(7, "DBG_MON_B14")
+	),
+	MTK_PIN(
+		103, "GPIO103",
+		MTK_EINT_FUNCTION(0, 103),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "GPIO103"),
+		MTK_FUNCTION(1, "BPI_BUS4"),
+		MTK_FUNCTION(4, "MFG_TSFDC_TSSEL0"),
+		MTK_FUNCTION(6, "ANT_SEL4"),
+		MTK_FUNCTION(7, "DBG_MON_B15")
+	),
+	MTK_PIN(
+		104, "GPIO104",
+		MTK_EINT_FUNCTION(0, 104),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "GPIO104"),
+		MTK_FUNCTION(1, "BPI_BUS5"),
+		MTK_FUNCTION(4, "MFG_TSFDC_RCK_SELB"),
+		MTK_FUNCTION(6, "ANT_SEL5"),
+		MTK_FUNCTION(7, "DBG_MON_B16")
+	),
+	MTK_PIN(
+		105, "GPIO105",
+		MTK_EINT_FUNCTION(0, 105),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "GPIO105"),
+		MTK_FUNCTION(1, "BPI_BUS6"),
+		MTK_FUNCTION(2, "CONN_BPI_BUS6"),
+		MTK_FUNCTION(6, "ANT_SEL6"),
+		MTK_FUNCTION(7, "DBG_MON_B17")
+	),
+	MTK_PIN(
+		106, "GPIO106",
+		MTK_EINT_FUNCTION(0, 106),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "GPIO106"),
+		MTK_FUNCTION(1, "BPI_BUS7"),
+		MTK_FUNCTION(2, "CONN_BPI_BUS7"),
+		MTK_FUNCTION(4, "MFG_TSFDC_SDO"),
+		MTK_FUNCTION(5, "AUD_DAC_26M_CLK"),
+		MTK_FUNCTION(6, "ANT_SEL7"),
+		MTK_FUNCTION(7, "DBG_MON_B18")
+	),
+	MTK_PIN(
+		107, "GPIO107",
+		MTK_EINT_FUNCTION(0, 107),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "GPIO107"),
+		MTK_FUNCTION(1, "BPI_BUS8"),
+		MTK_FUNCTION(2, "CONN_BPI_BUS8"),
+		MTK_FUNCTION(4, "MFG_TSFDC_FOUT"),
+		MTK_FUNCTION(5, "I2SOUT4_DATA0"),
+		MTK_FUNCTION(6, "ANT_SEL8"),
+		MTK_FUNCTION(7, "DBG_MON_B19")
+	),
+	MTK_PIN(
+		108, "GPIO108",
+		MTK_EINT_FUNCTION(0, 108),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "GPIO108"),
+		MTK_FUNCTION(1, "BPI_BUS9"),
+		MTK_FUNCTION(2, "CONN_BPI_BUS9"),
+		MTK_FUNCTION(5, "I2SOUT4_DATA1"),
+		MTK_FUNCTION(6, "ANT_SEL9"),
+		MTK_FUNCTION(7, "DBG_MON_B20")
+	),
+	MTK_PIN(
+		109, "GPIO109",
+		MTK_EINT_FUNCTION(0, 109),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "GPIO109"),
+		MTK_FUNCTION(1, "BPI_BUS10"),
+		MTK_FUNCTION(2, "CONN_BPI_BUS10"),
+		MTK_FUNCTION(5, "I2SOUT4_DATA2"),
+		MTK_FUNCTION(6, "ANT_SEL10"),
+		MTK_FUNCTION(7, "DBG_MON_B21")
+	),
+	MTK_PIN(
+		110, "GPIO110",
+		MTK_EINT_FUNCTION(0, 110),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "GPIO110"),
+		MTK_FUNCTION(1, "BPI_BUS11"),
+		MTK_FUNCTION(2, "CONN_BPI_BUS11_OLAT0"),
+		MTK_FUNCTION(5, "I2SOUT4_DATA3"),
+		MTK_FUNCTION(6, "ANT_SEL11"),
+		MTK_FUNCTION(7, "DBG_MON_B22")
+	),
+	MTK_PIN(
+		111, "GPIO111",
+		MTK_EINT_FUNCTION(0, 111),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "GPIO111"),
+		MTK_FUNCTION(1, "BPI_BUS12"),
+		MTK_FUNCTION(2, "CONN_BPI_BUS12_OLAT1"),
+		MTK_FUNCTION(3, "CLKM0"),
+		MTK_FUNCTION(5, "I2SIN4_BCK"),
+		MTK_FUNCTION(6, "ANT_SEL12"),
+		MTK_FUNCTION(7, "DBG_MON_B23")
+	),
+	MTK_PIN(
+		112, "GPIO112",
+		MTK_EINT_FUNCTION(0, 112),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "GPIO112"),
+		MTK_FUNCTION(1, "BPI_BUS13"),
+		MTK_FUNCTION(2, "CONN_BPI_BUS13_OLAT2"),
+		MTK_FUNCTION(3, "CLKM1"),
+		MTK_FUNCTION(5, "I2SIN4_DATA0"),
+		MTK_FUNCTION(6, "ANT_SEL13"),
+		MTK_FUNCTION(7, "DBG_MON_B24")
+	),
+	MTK_PIN(
+		113, "GPIO113",
+		MTK_EINT_FUNCTION(0, 113),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "GPIO113"),
+		MTK_FUNCTION(1, "BPI_BUS14"),
+		MTK_FUNCTION(2, "CONN_BPI_BUS14_OLAT3"),
+		MTK_FUNCTION(3, "CLKM2"),
+		MTK_FUNCTION(5, "I2SIN4_DATA1"),
+		MTK_FUNCTION(6, "ANT_SEL14"),
+		MTK_FUNCTION(7, "DBG_MON_B25")
+	),
+	MTK_PIN(
+		114, "GPIO114",
+		MTK_EINT_FUNCTION(0, 114),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "GPIO114"),
+		MTK_FUNCTION(1, "BPI_BUS15"),
+		MTK_FUNCTION(2, "CONN_BPI_BUS15_OLAT4"),
+		MTK_FUNCTION(3, "CLKM3"),
+		MTK_FUNCTION(5, "I2SIN4_DATA2"),
+		MTK_FUNCTION(6, "ANT_SEL15"),
+		MTK_FUNCTION(7, "DBG_MON_B26")
+	),
+	MTK_PIN(
+		115, "GPIO115",
+		MTK_EINT_FUNCTION(0, 115),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "GPIO115"),
+		MTK_FUNCTION(1, "BPI_BUS16"),
+		MTK_FUNCTION(2, "CONN_BPI_BUS16_OLAT5"),
+		MTK_FUNCTION(5, "I2SIN4_DATA3"),
+		MTK_FUNCTION(6, "ANT_SEL16"),
+		MTK_FUNCTION(7, "DBG_MON_B27")
+	),
+	MTK_PIN(
+		116, "GPIO116",
+		MTK_EINT_FUNCTION(0, 116),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "GPIO116"),
+		MTK_FUNCTION(1, "BPI_BUS17"),
+		MTK_FUNCTION(2, "CONN_BPI_BUS17_ANT0"),
+		MTK_FUNCTION(5, "I2SIN4_LRCK"),
+		MTK_FUNCTION(6, "ANT_SEL17"),
+		MTK_FUNCTION(7, "DBG_MON_B28")
+	),
+	MTK_PIN(
+		117, "GPIO117",
+		MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "GPIO117"),
+		MTK_FUNCTION(1, "MIPI0_D_SCLK"),
+		MTK_FUNCTION(2, "CONN_MIPI0_SCLK"),
+		MTK_FUNCTION(3, "BPI_BUS18"),
+		MTK_FUNCTION(6, "ANT_SEL18")
+	),
+	MTK_PIN(
+		118, "GPIO118",
+		MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "GPIO118"),
+		MTK_FUNCTION(1, "MIPI0_D_SDATA"),
+		MTK_FUNCTION(2, "CONN_MIPI0_SDATA"),
+		MTK_FUNCTION(3, "BPI_BUS19"),
+		MTK_FUNCTION(6, "ANT_SEL19")
+	),
+	MTK_PIN(
+		119, "GPIO119",
+		MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "GPIO119"),
+		MTK_FUNCTION(1, "MIPI1_D_SCLK"),
+		MTK_FUNCTION(2, "CONN_MIPI1_SCLK"),
+		MTK_FUNCTION(3, "BPI_BUS20"),
+		MTK_FUNCTION(6, "ANT_SEL20")
+	),
+	MTK_PIN(
+		120, "GPIO120",
+		MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "GPIO120"),
+		MTK_FUNCTION(1, "MIPI1_D_SDATA"),
+		MTK_FUNCTION(2, "CONN_MIPI1_SDATA"),
+		MTK_FUNCTION(3, "BPI_BUS21"),
+		MTK_FUNCTION(6, "ANT_SEL21")
+	),
+	MTK_PIN(
+		121, "GPIO121",
+		MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "GPIO121"),
+		MTK_FUNCTION(1, "MIPI2_D_SCLK"),
+		MTK_FUNCTION(2, "MIPI4_D_SCLK"),
+		MTK_FUNCTION(3, "BPI_BUS22"),
+		MTK_FUNCTION(6, "MD_GPS_L1_BLANK")
+	),
+	MTK_PIN(
+		122, "GPIO122",
+		MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "GPIO122"),
+		MTK_FUNCTION(1, "MIPI2_D_SDATA"),
+		MTK_FUNCTION(2, "MIPI4_D_SDATA"),
+		MTK_FUNCTION(3, "BPI_BUS23"),
+		MTK_FUNCTION(6, "MD_GPS_L5_BLANK")
+	),
+	MTK_PIN(
+		123, "GPIO123",
+		MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "GPIO123"),
+		MTK_FUNCTION(1, "MIPI_M_SCLK")
+	),
+	MTK_PIN(
+		124, "GPIO124",
+		MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "GPIO124"),
+		MTK_FUNCTION(1, "MIPI_M_SDATA")
+	),
+	MTK_PIN(
+		125, "GPIO125",
+		MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "GPIO125"),
+		MTK_FUNCTION(1, "SCL0"),
+		MTK_FUNCTION(2, "SCP_SCL4"),
+		MTK_FUNCTION(3, "TP_UTXD2_VLP"),
+		MTK_FUNCTION(4, "TP_UCTS1_VLP"),
+		MTK_FUNCTION(5, "TP_GPIO4_AO"),
+		MTK_FUNCTION(6, "UTXD2")
+	),
+	MTK_PIN(
+		126, "GPIO126",
+		MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "GPIO126"),
+		MTK_FUNCTION(1, "SDA0"),
+		MTK_FUNCTION(2, "SCP_SDA4"),
+		MTK_FUNCTION(3, "TP_URXD2_VLP"),
+		MTK_FUNCTION(4, "TP_URTS1_VLP"),
+		MTK_FUNCTION(5, "TP_GPIO5_AO"),
+		MTK_FUNCTION(6, "URXD2")
+	),
+	MTK_PIN(
+		127, "GPIO127",
+		MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "GPIO127"),
+		MTK_FUNCTION(1, "SCL1"),
+		MTK_FUNCTION(2, "SCP_SCL5"),
+		MTK_FUNCTION(3, "TP_UCTS2_VLP"),
+		MTK_FUNCTION(4, "TP_UTXD1_VLP"),
+		MTK_FUNCTION(5, "TP_GPIO6_AO"),
+		MTK_FUNCTION(6, "MD_MCIF_UTXD0")
+	),
+	MTK_PIN(
+		128, "GPIO128",
+		MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "GPIO128"),
+		MTK_FUNCTION(1, "SDA1"),
+		MTK_FUNCTION(2, "SCP_SDA5"),
+		MTK_FUNCTION(3, "TP_URTS2_VLP"),
+		MTK_FUNCTION(4, "TP_URXD1_VLP"),
+		MTK_FUNCTION(5, "TP_GPIO7_AO"),
+		MTK_FUNCTION(6, "MD_MCIF_URXD0")
+	),
+	MTK_PIN(
+		129, "GPIO129",
+		MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "GPIO129"),
+		MTK_FUNCTION(1, "SCL2")
+	),
+	MTK_PIN(
+		130, "GPIO130",
+		MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "GPIO130"),
+		MTK_FUNCTION(1, "SDA2")
+	),
+	MTK_PIN(
+		131, "GPIO131",
+		MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "GPIO131"),
+		MTK_FUNCTION(1, "SCL3"),
+		MTK_FUNCTION(3, "TP_UTXD2_VCORE"),
+		MTK_FUNCTION(6, "SSPM_UTXD_AO_VCORE")
+	),
+	MTK_PIN(
+		132, "GPIO132",
+		MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "GPIO132"),
+		MTK_FUNCTION(1, "SDA3"),
+		MTK_FUNCTION(3, "TP_URXD2_VCORE"),
+		MTK_FUNCTION(6, "SSPM_URXD_AO_VCORE")
+	),
+	MTK_PIN(
+		133, "GPIO133",
+		MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "GPIO133"),
+		MTK_FUNCTION(1, "SCL4")
+	),
+	MTK_PIN(
+		134, "GPIO134",
+		MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "GPIO134"),
+		MTK_FUNCTION(1, "SDA4")
+	),
+	MTK_PIN(
+		135, "GPIO135",
+		MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "GPIO135"),
+		MTK_FUNCTION(1, "SCL5")
+	),
+	MTK_PIN(
+		136, "GPIO136",
+		MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "GPIO136"),
+		MTK_FUNCTION(1, "SDA5")
+	),
+	MTK_PIN(
+		137, "GPIO137",
+		MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "GPIO137"),
+		MTK_FUNCTION(1, "SCL6")
+	),
+	MTK_PIN(
+		138, "GPIO138",
+		MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "GPIO138"),
+		MTK_FUNCTION(1, "SDA6")
+	),
+	MTK_PIN(
+		139, "GPIO139",
+		MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "GPIO139"),
+		MTK_FUNCTION(1, "SCL7"),
+		MTK_FUNCTION(3, "TP_UTXD1_VCORE"),
+		MTK_FUNCTION(4, "MD_UTXD0"),
+		MTK_FUNCTION(6, "UTXD1")
+	),
+	MTK_PIN(
+		140, "GPIO140",
+		MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "GPIO140"),
+		MTK_FUNCTION(1, "SDA7"),
+		MTK_FUNCTION(3, "TP_URXD1_VCORE"),
+		MTK_FUNCTION(4, "MD_URXD0"),
+		MTK_FUNCTION(6, "URXD1")
+	),
+	MTK_PIN(
+		141, "GPIO141",
+		MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "GPIO141"),
+		MTK_FUNCTION(1, "SCL8")
+	),
+	MTK_PIN(
+		142, "GPIO142",
+		MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "GPIO142"),
+		MTK_FUNCTION(1, "SDA8")
+	),
+	MTK_PIN(
+		143, "GPIO143",
+		MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "GPIO143"),
+		MTK_FUNCTION(1, "SCL9"),
+		MTK_FUNCTION(2, "GPS_L1_ELNA_EN"),
+		MTK_FUNCTION(3, "HFRP_UTXD1"),
+		MTK_FUNCTION(4, "CONN_BGF_MCU_AICE_TMSC"),
+		MTK_FUNCTION(5, "CONN_WF_MCU_AICE_TMSC"),
+		MTK_FUNCTION(7, "MBISTREADEN_TRIGGER")
+	),
+	MTK_PIN(
+		144, "GPIO144",
+		MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "GPIO144"),
+		MTK_FUNCTION(1, "SDA9"),
+		MTK_FUNCTION(2, "GPS_L5_ELNA_EN"),
+		MTK_FUNCTION(3, "HFRP_URXD1"),
+		MTK_FUNCTION(4, "CONN_BGF_MCU_AICE_TCKC"),
+		MTK_FUNCTION(5, "CONN_WF_MCU_AICE_TCKC"),
+		MTK_FUNCTION(7, "MBISTWRITEEN_TRIGGER")
+	),
+	MTK_PIN(
+		145, "GPIO145",
+		MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "GPIO145"),
+		MTK_FUNCTION(1, "SCL10"),
+		MTK_FUNCTION(2, "SCP_SCL0"),
+		MTK_FUNCTION(5, "TP_GPIO8_AO")
+	),
+	MTK_PIN(
+		146, "GPIO146",
+		MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "GPIO146"),
+		MTK_FUNCTION(1, "SDA10"),
+		MTK_FUNCTION(2, "SCP_SDA0"),
+		MTK_FUNCTION(5, "TP_GPIO9_AO")
+	),
+	MTK_PIN(
+		147, "GPIO147",
+		MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "GPIO147"),
+		MTK_FUNCTION(1, "SCL11"),
+		MTK_FUNCTION(2, "SCP_SCL1"),
+		MTK_FUNCTION(3, "SCP_DMIC_CLK"),
+		MTK_FUNCTION(4, "DMIC_CLK"),
+		MTK_FUNCTION(5, "TP_GPIO10_AO"),
+		MTK_FUNCTION(6, "EXTIF0_PRI")
+	),
+	MTK_PIN(
+		148, "GPIO148",
+		MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "GPIO148"),
+		MTK_FUNCTION(1, "SDA11"),
+		MTK_FUNCTION(2, "SCP_SDA1"),
+		MTK_FUNCTION(3, "SCP_DMIC_DAT"),
+		MTK_FUNCTION(4, "DMIC_DAT"),
+		MTK_FUNCTION(5, "TP_GPIO11_AO"),
+		MTK_FUNCTION(6, "EXTIF0_GNT_B")
+	),
+	MTK_PIN(
+		149, "GPIO149",
+		MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "GPIO149"),
+		MTK_FUNCTION(1, "KPROW2"),
+		MTK_FUNCTION(2, "PWM_VLP"),
+		MTK_FUNCTION(4, "MD_INT0"),
+		MTK_FUNCTION(5, "TP_GPIO12_AO"),
+		MTK_FUNCTION(6, "SCL0"),
+		MTK_FUNCTION(7, "DBG_MON_A28")
+	),
+	MTK_PIN(
+		150, "GPIO150",
+		MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "GPIO150"),
+		MTK_FUNCTION(1, "KPCOL2"),
+		MTK_FUNCTION(2, "PWM_VLP"),
+		MTK_FUNCTION(3, "CMMCLK5"),
+		MTK_FUNCTION(4, "MD_INT3"),
+		MTK_FUNCTION(5, "TP_GPIO13_AO"),
+		MTK_FUNCTION(6, "SDA0")
+	),
+	MTK_PIN(
+		151, "GPIO151",
+		MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "GPIO151"),
+		MTK_FUNCTION(1, "SRCLKENAI0"),
+		MTK_FUNCTION(4, "MD_INT4"),
+		MTK_FUNCTION(5, "TP_GPIO14_AO"),
+		MTK_FUNCTION(7, "DBG_MON_A29")
+	),
+	MTK_PIN(
+		152, "GPIO152",
+		MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "GPIO152"),
+		MTK_FUNCTION(1, "SRCLKENAI1"),
+		MTK_FUNCTION(4, "SPMI_M_TRIG_FLAG"),
+		MTK_FUNCTION(5, "TP_GPIO15_AO"),
+		MTK_FUNCTION(7, "DBG_MON_A30")
+	),
+	MTK_PIN(
+		153, "GPIO153",
+		MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "GPIO153"),
+		MTK_FUNCTION(1, "MD1_SIM2_SCLK"),
+		MTK_FUNCTION(2, "DISP_PWM1"),
+		MTK_FUNCTION(4, "SPMI_P_TRIG_FLAG"),
+		MTK_FUNCTION(7, "DBG_MON_A0")
+	),
+	MTK_PIN(
+		154, "GPIO154",
+		MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "GPIO154"),
+		MTK_FUNCTION(1, "MD1_SIM2_SRST"),
+		MTK_FUNCTION(2, "LCM_RST1"),
+		MTK_FUNCTION(3, "GPS_L1_ELNA_EN"),
+		MTK_FUNCTION(4, "CMFLASH2"),
+		MTK_FUNCTION(5, "MBISTREADEN_TRIGGER"),
+		MTK_FUNCTION(7, "DBG_MON_A1")
+	),
+	MTK_PIN(
+		155, "GPIO155",
+		MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "GPIO155"),
+		MTK_FUNCTION(1, "MD1_SIM2_SIO"),
+		MTK_FUNCTION(2, "DSI_TE1"),
+		MTK_FUNCTION(3, "GPS_L5_ELNA_EN"),
+		MTK_FUNCTION(4, "CMFLASH3"),
+		MTK_FUNCTION(5, "MBISTWRITEEN_TRIGGER"),
+		MTK_FUNCTION(7, "DBG_MON_A2")
+	),
+	MTK_PIN(
+		156, "GPIO156",
+		MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "GPIO156"),
+		MTK_FUNCTION(1, "SPMI_M_SCL")
+	),
+	MTK_PIN(
+		157, "GPIO157",
+		MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "GPIO157"),
+		MTK_FUNCTION(1, "SPMI_M_SDA")
+	),
+	MTK_PIN(
+		158, "GPIO158",
+		MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "GPIO158"),
+		MTK_FUNCTION(1, "SPMI_P_SCL")
+	),
+	MTK_PIN(
+		159, "GPIO159",
+		MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "GPIO159"),
+		MTK_FUNCTION(1, "SPMI_P_SDA")
+	),
+	MTK_PIN(
+		160, "GPIO160",
+		MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "GPIO160"),
+		MTK_FUNCTION(1, "SRCLKENA0")
+	),
+	MTK_PIN(
+		161, "GPIO161",
+		MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "GPIO161"),
+		MTK_FUNCTION(1, "SCP_VREQ_VAO")
+	),
+	MTK_PIN(
+		162, "GPIO162",
+		MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "GPIO162"),
+		MTK_FUNCTION(1, "RTC32K_CK")
+	),
+	MTK_PIN(
+		163, "GPIO163",
+		MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "GPIO163"),
+		MTK_FUNCTION(1, "WATCHDOG")
+	),
+	MTK_PIN(
+		164, "GPIO164",
+		MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "GPIO164"),
+		MTK_FUNCTION(1, "AUD_CLK_MOSI"),
+		MTK_FUNCTION(3, "AUD_CLK_MOSI")
+	),
+	MTK_PIN(
+		165, "GPIO165",
+		MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "GPIO165"),
+		MTK_FUNCTION(1, "AUD_SYNC_MOSI")
+	),
+	MTK_PIN(
+		166, "GPIO166",
+		MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "GPIO166"),
+		MTK_FUNCTION(1, "AUD_DAT_MOSI0"),
+		MTK_FUNCTION(3, "AUD_DAT_MOSI0")
+	),
+	MTK_PIN(
+		167, "GPIO167",
+		MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "GPIO167"),
+		MTK_FUNCTION(1, "AUD_DAT_MOSI1"),
+		MTK_FUNCTION(3, "AUD_DAT_MOSI1")
+	),
+	MTK_PIN(
+		168, "GPIO168",
+		MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "GPIO168"),
+		MTK_FUNCTION(1, "AUD_NLE_MOSI0"),
+		MTK_FUNCTION(2, "AUD_SYNC_MISO")
+	),
+	MTK_PIN(
+		169, "GPIO169",
+		MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "GPIO169"),
+		MTK_FUNCTION(1, "AUD_NLE_MOSI1"),
+		MTK_FUNCTION(2, "AUD_CLK_MISO"),
+		MTK_FUNCTION(3, "AUD_CLK_MISO")
+	),
+	MTK_PIN(
+		170, "GPIO170",
+		MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "GPIO170"),
+		MTK_FUNCTION(1, "AUD_DAT_MISO0"),
+		MTK_FUNCTION(2, "VOW_DAT_MISO"),
+		MTK_FUNCTION(3, "AUD_DAT_MISO0")
+	),
+	MTK_PIN(
+		171, "GPIO171",
+		MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "GPIO171"),
+		MTK_FUNCTION(1, "AUD_DAT_MISO1"),
+		MTK_FUNCTION(2, "VOW_CLK_MISO"),
+		MTK_FUNCTION(3, "AUD_DAT_MISO1")
+	),
+	MTK_PIN(
+		172, "GPIO172",
+		MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "GPIO172"),
+		MTK_FUNCTION(1, "CONN_TOP_CLK"),
+		MTK_FUNCTION(7, "DBG_MON_A31")
+	),
+	MTK_PIN(
+		173, "GPIO173",
+		MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "GPIO173"),
+		MTK_FUNCTION(1, "CONN_TOP_DATA")
+	),
+	MTK_PIN(
+		174, "GPIO174",
+		MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "GPIO174"),
+		MTK_FUNCTION(1, "CONN_BT_CLK")
+	),
+	MTK_PIN(
+		175, "GPIO175",
+		MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "GPIO175"),
+		MTK_FUNCTION(1, "CONN_BT_DATA")
+	),
+	MTK_PIN(
+		176, "GPIO176",
+		MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "GPIO176"),
+		MTK_FUNCTION(1, "CONN_HRST_B")
+	),
+	MTK_PIN(
+		177, "GPIO177",
+		MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "GPIO177"),
+		MTK_FUNCTION(1, "CONN_WB_PTA")
+	),
+	MTK_PIN(
+		178, "GPIO178",
+		MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "GPIO178"),
+		MTK_FUNCTION(1, "CONN_WF_CTRL0")
+	),
+	MTK_PIN(
+		179, "GPIO179",
+		MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "GPIO179"),
+		MTK_FUNCTION(1, "CONN_WF_CTRL1")
+	),
+	MTK_PIN(
+		180, "GPIO180",
+		MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "GPIO180"),
+		MTK_FUNCTION(1, "CONN_WF_CTRL2")
+	),
+	MTK_PIN(
+		181, "GPIO181",
+		MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "GPIO181"),
+		MTK_FUNCTION(1, "CONN_WF_CTRL3"),
+		MTK_FUNCTION(2, "CONN_TOP_CLK_2"),
+		MTK_FUNCTION(3, "GPS_L1_ELNA_EN")
+	),
+	MTK_PIN(
+		182, "GPIO182",
+		MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "GPIO182"),
+		MTK_FUNCTION(1, "CONN_WF_CTRL4"),
+		MTK_FUNCTION(2, "CONN_TOP_DATA_2"),
+		MTK_FUNCTION(3, "GPS_L5_ELNA_EN")
+	),
+	MTK_PIN(
+		183, "GPIO183",
+		MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "GPIO183"),
+		MTK_FUNCTION(1, "CONN_HRST_B_2")
+	),
+	MTK_PIN(
+		184, "GPIO184",
+		MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "GPIO184"),
+		MTK_FUNCTION(1, "MSDC0_DSL"),
+		MTK_FUNCTION(3, "ANT_SEL13")
+	),
+	MTK_PIN(
+		185, "GPIO185",
+		MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "GPIO185"),
+		MTK_FUNCTION(1, "MSDC0_CLK"),
+		MTK_FUNCTION(2, "CONN_TCXOENA_REQ"),
+		MTK_FUNCTION(3, "ANT_SEL14")
+	),
+	MTK_PIN(
+		186, "GPIO186",
+		MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "GPIO186"),
+		MTK_FUNCTION(1, "MSDC0_CMD"),
+		MTK_FUNCTION(2, "GPS_L1_ELNA_EN"),
+		MTK_FUNCTION(3, "ANT_SEL15"),
+		MTK_FUNCTION(5, "I2SOUT4_DATA0")
+	),
+	MTK_PIN(
+		187, "GPIO187",
+		MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "GPIO187"),
+		MTK_FUNCTION(1, "MSDC0_RSTB"),
+		MTK_FUNCTION(2, "GPS_L5_ELNA_EN"),
+		MTK_FUNCTION(3, "ANT_SEL16"),
+		MTK_FUNCTION(5, "I2SOUT4_DATA1")
+	),
+	MTK_PIN(
+		188, "GPIO188",
+		MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "GPIO188"),
+		MTK_FUNCTION(1, "MSDC0_DAT0"),
+		MTK_FUNCTION(3, "ANT_SEL17"),
+		MTK_FUNCTION(5, "I2SOUT4_DATA2")
+	),
+	MTK_PIN(
+		189, "GPIO189",
+		MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "GPIO189"),
+		MTK_FUNCTION(1, "MSDC0_DAT1"),
+		MTK_FUNCTION(3, "ANT_SEL18"),
+		MTK_FUNCTION(5, "I2SOUT4_DATA3")
+	),
+	MTK_PIN(
+		190, "GPIO190",
+		MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "GPIO190"),
+		MTK_FUNCTION(1, "MSDC0_DAT2"),
+		MTK_FUNCTION(2, "DMIC1_CLK"),
+		MTK_FUNCTION(3, "ANT_SEL19"),
+		MTK_FUNCTION(5, "I2SIN4_BCK")
+	),
+	MTK_PIN(
+		191, "GPIO191",
+		MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "GPIO191"),
+		MTK_FUNCTION(1, "MSDC0_DAT3"),
+		MTK_FUNCTION(2, "DMIC1_DAT"),
+		MTK_FUNCTION(3, "ANT_SEL20"),
+		MTK_FUNCTION(5, "I2SIN4_DATA0")
+	),
+	MTK_PIN(
+		192, "GPIO192",
+		MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "GPIO192"),
+		MTK_FUNCTION(1, "MSDC0_DAT4"),
+		MTK_FUNCTION(2, "IDDIG"),
+		MTK_FUNCTION(3, "ANT_SEL21"),
+		MTK_FUNCTION(4, "UFS_MPHY_SCL"),
+		MTK_FUNCTION(5, "I2SIN4_DATA1")
+	),
+	MTK_PIN(
+		193, "GPIO193",
+		MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "GPIO193"),
+		MTK_FUNCTION(1, "MSDC0_DAT5"),
+		MTK_FUNCTION(2, "USB_DRVVBUS"),
+		MTK_FUNCTION(4, "UFS_MPHY_SDA"),
+		MTK_FUNCTION(5, "I2SIN4_DATA2")
+	),
+	MTK_PIN(
+		194, "GPIO194",
+		MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "GPIO194"),
+		MTK_FUNCTION(1, "MSDC0_DAT6"),
+		MTK_FUNCTION(2, "VBUSVALID"),
+		MTK_FUNCTION(5, "I2SIN4_DATA3")
+	),
+	MTK_PIN(
+		195, "GPIO195",
+		MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "GPIO195"),
+		MTK_FUNCTION(1, "MSDC0_DAT7"),
+		MTK_FUNCTION(5, "I2SIN4_LRCK")
+	),
+	MTK_PIN(
+		196, "GPIO196",
+		MTK_EINT_FUNCTION(0, 196),
+		DRV_GRP4,
+		MTK_FUNCTION(0, NULL)
+	),
+	MTK_PIN(
+		197, "GPIO197",
+		MTK_EINT_FUNCTION(0, 197),
+		DRV_GRP4,
+		MTK_FUNCTION(0, NULL)
+	),
+	MTK_PIN(
+		198, "GPIO198",
+		MTK_EINT_FUNCTION(0, 198),
+		DRV_GRP4,
+		MTK_FUNCTION(0, NULL)
+	),
+	MTK_PIN(
+		199, "GPIO199",
+		MTK_EINT_FUNCTION(0, 199),
+		DRV_GRP4,
+		MTK_FUNCTION(0, NULL)
+	),
+	MTK_PIN(
+		200, "GPIO200",
+		MTK_EINT_FUNCTION(0, 200),
+		DRV_GRP4,
+		MTK_FUNCTION(0, NULL)
+	),
+	MTK_PIN(
+		201, "GPIO201",
+		MTK_EINT_FUNCTION(0, 201),
+		DRV_GRP4,
+		MTK_FUNCTION(0, NULL)
+	),
+	MTK_PIN(
+		202, "GPIO202",
+		MTK_EINT_FUNCTION(0, 202),
+		DRV_GRP4,
+		MTK_FUNCTION(0, NULL)
+	),
+	MTK_PIN(
+		203, "GPIO203",
+		MTK_EINT_FUNCTION(0, 203),
+		DRV_GRP4,
+		MTK_FUNCTION(0, NULL)
+	),
+	MTK_PIN(
+		204, "GPIO204",
+		MTK_EINT_FUNCTION(0, 204),
+		DRV_GRP4,
+		MTK_FUNCTION(0, NULL)
+	),
+	MTK_PIN(
+		205, "GPIO205",
+		MTK_EINT_FUNCTION(0, 205),
+		DRV_GRP4,
+		MTK_FUNCTION(0, NULL)
+	),
+	MTK_PIN(
+		206, "GPIO206",
+		MTK_EINT_FUNCTION(0, 206),
+		DRV_GRP4,
+		MTK_FUNCTION(0, NULL)
+	),
+	MTK_PIN(
+		207, "GPIO207",
+		MTK_EINT_FUNCTION(0, 207),
+		DRV_GRP4,
+		MTK_FUNCTION(0, NULL)
+	),
+	MTK_PIN(
+		208, "GPIO208",
+		MTK_EINT_FUNCTION(0, 208),
+		DRV_GRP4,
+		MTK_FUNCTION(0, NULL)
+	),
+	MTK_PIN(
+		209, "GPIO209",
+		MTK_EINT_FUNCTION(0, 209),
+		DRV_GRP4,
+		MTK_FUNCTION(0, NULL)
+	),
+	MTK_PIN(
+		210, "GPIO210",
+		MTK_EINT_FUNCTION(0, 210),
+		DRV_GRP4,
+		MTK_FUNCTION(0, NULL)
+	),
+	MTK_PIN(
+		211, "GPIO211",
+		MTK_EINT_FUNCTION(0, 211),
+		DRV_GRP4,
+		MTK_FUNCTION(0, NULL)
+	),
+	MTK_PIN(
+		212, "GPIO212",
+		MTK_EINT_FUNCTION(0, 212),
+		DRV_GRP4,
+		MTK_FUNCTION(0, NULL)
+	),
+	MTK_PIN(
+		213, "GPIO213",
+		MTK_EINT_FUNCTION(0, 213),
+		DRV_GRP4,
+		MTK_FUNCTION(0, NULL)
+	),
+	MTK_PIN(
+		214, "GPIO214",
+		MTK_EINT_FUNCTION(0, 214),
+		DRV_GRP4,
+		MTK_FUNCTION(0, NULL)
+	),
+	MTK_PIN(
+		215, "GPIO215",
+		MTK_EINT_FUNCTION(0, 215),
+		DRV_GRP4,
+		MTK_FUNCTION(0, NULL)
+	),
+};
+
+static struct mtk_eint_pin eint_pins_mt6878[] = {
+	MTK_EINT_PIN(0, 0, 0, 1),
+	MTK_EINT_PIN(1, 0, 1, 1),
+	MTK_EINT_PIN(2, 0, 2, 1),
+	MTK_EINT_PIN(3, 0, 3, 1),
+	MTK_EINT_PIN(4, 0, 4, 1),
+	MTK_EINT_PIN(5, 0, 5, 1),
+	MTK_EINT_PIN(6, 1, 0, 1),
+	MTK_EINT_PIN(7, 1, 1, 1),
+	MTK_EINT_PIN(8, 1, 2, 1),
+	MTK_EINT_PIN(9, 1, 3, 1),
+	MTK_EINT_PIN(10, 1, 4, 1),
+	MTK_EINT_PIN(11, 1, 5, 1),
+	MTK_EINT_PIN(12, 1, 6, 1),
+	MTK_EINT_PIN(13, 2, 0, 1),
+	MTK_EINT_PIN(14, 2, 1, 1),
+	MTK_EINT_PIN(15, 2, 2, 1),
+	MTK_EINT_PIN(16, 2, 3, 1),
+	MTK_EINT_PIN(17, 2, 4, 1),
+	MTK_EINT_PIN(18, 2, 5, 1),
+	MTK_EINT_PIN(19, 0, 6, 1),
+	MTK_EINT_PIN(20, 0, 7, 1),
+	MTK_EINT_PIN(21, 0, 8, 1),
+	MTK_EINT_PIN(22, 0, 9, 1),
+	MTK_EINT_PIN(23, 0, 10, 1),
+	MTK_EINT_PIN(24, 0, 11, 1),
+	MTK_EINT_PIN(25, 0, 12, 1),
+	MTK_EINT_PIN(26, 0, 13, 1),
+	MTK_EINT_PIN(27, 0, 14, 1),
+	MTK_EINT_PIN(28, 0, 15, 1),
+	MTK_EINT_PIN(29, 2, 6, 1),
+	MTK_EINT_PIN(30, 2, 7, 1),
+	MTK_EINT_PIN(31, 2, 8, 1),
+	MTK_EINT_PIN(32, 2, 9, 1),
+	MTK_EINT_PIN(33, 0, 16, 1),
+	MTK_EINT_PIN(34, 0, 17, 1),
+	MTK_EINT_PIN(35, 0, 18, 1),
+	MTK_EINT_PIN(36, 0, 19, 0),
+	MTK_EINT_PIN(37, 0, 20, 0),
+	MTK_EINT_PIN(38, 0, 21, 0),
+	MTK_EINT_PIN(39, 0, 22, 0),
+	MTK_EINT_PIN(40, 0, 23, 0),
+	MTK_EINT_PIN(41, 1, 7, 0),
+	MTK_EINT_PIN(42, 1, 8, 0),
+	MTK_EINT_PIN(43, 1, 9, 0),
+	MTK_EINT_PIN(44, 1, 10, 0),
+	MTK_EINT_PIN(45, 1, 11, 0),
+	MTK_EINT_PIN(46, 1, 12, 0),
+	MTK_EINT_PIN(47, 1, 13, 0),
+	MTK_EINT_PIN(48, 0, 24, 0),
+	MTK_EINT_PIN(49, 0, 25, 0),
+	MTK_EINT_PIN(50, 0, 26, 0),
+	MTK_EINT_PIN(51, 0, 27, 0),
+	MTK_EINT_PIN(52, 0, 28, 0),
+	MTK_EINT_PIN(53, 0, 29, 0),
+	MTK_EINT_PIN(54, 0, 30, 0),
+	MTK_EINT_PIN(55, 0, 31, 0),
+	MTK_EINT_PIN(56, 0, 32, 0),
+	MTK_EINT_PIN(57, 0, 33, 0),
+	MTK_EINT_PIN(58, 0, 34, 0),
+	MTK_EINT_PIN(59, 0, 35, 0),
+	MTK_EINT_PIN(60, 0, 36, 0),
+	MTK_EINT_PIN(61, 0, 37, 0),
+	MTK_EINT_PIN(62, 0, 38, 0),
+	MTK_EINT_PIN(63, 0, 39, 0),
+	MTK_EINT_PIN(64, 0, 40, 0),
+	MTK_EINT_PIN(65, 0, 41, 0),
+	MTK_EINT_PIN(66, 0, 42, 0),
+	MTK_EINT_PIN(67, 0, 43, 0),
+	MTK_EINT_PIN(68, 0, 44, 0),
+	MTK_EINT_PIN(69, 0, 45, 0),
+	MTK_EINT_PIN(70, 0, 46, 0),
+	MTK_EINT_PIN(71, 0, 47, 0),
+	MTK_EINT_PIN(72, 0, 48, 0),
+	MTK_EINT_PIN(73, 0, 49, 0),
+	MTK_EINT_PIN(74, 0, 50, 0),
+	MTK_EINT_PIN(75, 0, 51, 0),
+	MTK_EINT_PIN(76, 0, 52, 0),
+	MTK_EINT_PIN(77, 1, 14, 0),
+	MTK_EINT_PIN(78, 1, 15, 0),
+	MTK_EINT_PIN(79, 1, 16, 0),
+	MTK_EINT_PIN(80, 1, 17, 0),
+	MTK_EINT_PIN(81, 1, 18, 0),
+	MTK_EINT_PIN(82, 1, 19, 0),
+	MTK_EINT_PIN(83, 1, 20, 0),
+	MTK_EINT_PIN(84, 1, 21, 0),
+	MTK_EINT_PIN(85, 1, 22, 0),
+	MTK_EINT_PIN(86, 1, 23, 0),
+	MTK_EINT_PIN(87, 1, 24, 0),
+	MTK_EINT_PIN(88, 1, 25, 0),
+	MTK_EINT_PIN(89, 1, 26, 0),
+	MTK_EINT_PIN(90, 1, 27, 0),
+	MTK_EINT_PIN(91, 1, 28, 0),
+	MTK_EINT_PIN(92, 0, 53, 0),
+	MTK_EINT_PIN(93, 0, 54, 0),
+	MTK_EINT_PIN(94, 0, 55, 0),
+	MTK_EINT_PIN(95, 0, 56, 0),
+	MTK_EINT_PIN(96, 0, 57, 0),
+	MTK_EINT_PIN(97, 2, 10, 0),
+	MTK_EINT_PIN(98, 2, 11, 0),
+	MTK_EINT_PIN(99, 1, 29, 0),
+	MTK_EINT_PIN(100, 1, 30, 0),
+	MTK_EINT_PIN(101, 1, 31, 0),
+	MTK_EINT_PIN(102, 1, 32, 0),
+	MTK_EINT_PIN(103, 1, 33, 0),
+	MTK_EINT_PIN(104, 1, 34, 0),
+	MTK_EINT_PIN(105, 1, 35, 0),
+	MTK_EINT_PIN(106, 1, 36, 0),
+	MTK_EINT_PIN(107, 1, 37, 0),
+	MTK_EINT_PIN(108, 1, 38, 0),
+	MTK_EINT_PIN(109, 1, 39, 0),
+	MTK_EINT_PIN(110, 1, 40, 0),
+	MTK_EINT_PIN(111, 1, 41, 0),
+	MTK_EINT_PIN(112, 1, 42, 0),
+	MTK_EINT_PIN(113, 1, 43, 0),
+	MTK_EINT_PIN(114, 1, 44, 0),
+	MTK_EINT_PIN(115, 1, 45, 0),
+	MTK_EINT_PIN(116, 1, 46, 0),
+	MTK_EINT_PIN(196, 3, 0, 0),
+	MTK_EINT_PIN(197, 3, 1, 0),
+	MTK_EINT_PIN(198, 3, 2, 0),
+	MTK_EINT_PIN(199, 3, 3, 0),
+	MTK_EINT_PIN(200, 3, 4, 0),
+	MTK_EINT_PIN(201, 3, 5, 0),
+	MTK_EINT_PIN(202, 3, 6, 0),
+	MTK_EINT_PIN(203, 3, 7, 0),
+	MTK_EINT_PIN(204, 3, 8, 0),
+	MTK_EINT_PIN(205, 3, 9, 0),
+	MTK_EINT_PIN(206, 3, 10, 0),
+	MTK_EINT_PIN(207, 3, 11, 0),
+	MTK_EINT_PIN(208, 3, 12, 0),
+	MTK_EINT_PIN(209, 3, 13, 0),
+	MTK_EINT_PIN(210, 3, 14, 0),
+	MTK_EINT_PIN(211, 3, 15, 0),
+	MTK_EINT_PIN(212, 3, 16, 0),
+	MTK_EINT_PIN(213, 3, 17, 0),
+	MTK_EINT_PIN(214, 3, 18, 0),
+	MTK_EINT_PIN(215, 3, 19, 0),
+};
+
+#endif /* __PINCTRL_MTK_MT6878_H */

-- 
2.51.0


^ permalink raw reply	[flat|nested] 12+ messages in thread

* Re: [PATCH 4/4] pinctrl: mediatek: Add support for MT6878 pinctrl
  2025-09-08 19:17 ` [PATCH 4/4] pinctrl: mediatek: Add support for MT6878 pinctrl Igor Belwon
@ 2025-09-09  7:59   ` AngeloGioacchino Del Regno
  0 siblings, 0 replies; 12+ messages in thread
From: AngeloGioacchino Del Regno @ 2025-09-09  7:59 UTC (permalink / raw)
  To: Igor Belwon, Linus Walleij, Rob Herring, Krzysztof Kozlowski,
	Conor Dooley, Matthias Brugger, Sean Wang
  Cc: linux-gpio, devicetree, linux-kernel, linux-arm-kernel, linux-mediatek

Il 08/09/25 21:17, Igor Belwon ha scritto:
> Add driver support for the pin controller found in the MediaTek
> Dimensity 7300 (MT6878) SoC.
> 
> Signed-off-by: Igor Belwon <igor.belwon@mentallysanemainliners.org>
> ---
>   drivers/pinctrl/mediatek/Kconfig              |   10 +
>   drivers/pinctrl/mediatek/Makefile             |    1 +
>   drivers/pinctrl/mediatek/pinctrl-mt6878.c     | 1559 +++++++++++++++++
>   drivers/pinctrl/mediatek/pinctrl-mtk-mt6878.h | 2248 +++++++++++++++++++++++++
>   4 files changed, 3818 insertions(+)
> 
> diff --git a/drivers/pinctrl/mediatek/Kconfig b/drivers/pinctrl/mediatek/Kconfig
> index 5b191e12a8aa9d19f05bfbc51037aa788e9a3c36..4819617d936836eca59e8cc8c4ee8323ba92604f 100644
> --- a/drivers/pinctrl/mediatek/Kconfig
> +++ b/drivers/pinctrl/mediatek/Kconfig
> @@ -181,6 +181,16 @@ config PINCTRL_MT6797
>   	default ARM64 && ARCH_MEDIATEK
>   	select PINCTRL_MTK_PARIS
>   
> +config PINCTRL_MT6878
> +	bool "MediaTek MT6878 pin control"
> +	depends on OF
> +	depends on ARM64 || COMPILE_TEST
> +	default ARM64 && ARCH_MEDIATEK
> +	select PINCTRL_MTK_PARIS
> +	help
> +	  Say yes here to support pin controller and gpio driver
> +	  on the MediaTek MT6878 SoC.
> +
>   config PINCTRL_MT6893
>   	bool "MediaTek Dimensity MT6893 pin control"
>   	depends on OF
> diff --git a/drivers/pinctrl/mediatek/Makefile b/drivers/pinctrl/mediatek/Makefile
> index 5d4646939ba3ab3586483d36acf5cd701b3bf0dc..ae765bd999657cd887b605e201290c041efd020e 100644
> --- a/drivers/pinctrl/mediatek/Makefile
> +++ b/drivers/pinctrl/mediatek/Makefile
> @@ -23,6 +23,7 @@ obj-$(CONFIG_PINCTRL_MT6765)		+= pinctrl-mt6765.o
>   obj-$(CONFIG_PINCTRL_MT6779)		+= pinctrl-mt6779.o
>   obj-$(CONFIG_PINCTRL_MT6795)		+= pinctrl-mt6795.o
>   obj-$(CONFIG_PINCTRL_MT6797)		+= pinctrl-mt6797.o
> +obj-$(CONFIG_PINCTRL_MT6878)		+= pinctrl-mt6878.o
>   obj-$(CONFIG_PINCTRL_MT6893)		+= pinctrl-mt6893.o
>   obj-$(CONFIG_PINCTRL_MT7622)		+= pinctrl-mt7622.o
>   obj-$(CONFIG_PINCTRL_MT7623)		+= pinctrl-mt7623.o
> diff --git a/drivers/pinctrl/mediatek/pinctrl-mt6878.c b/drivers/pinctrl/mediatek/pinctrl-mt6878.c
> new file mode 100644
> index 0000000000000000000000000000000000000000..679f8cff1c516565daf9cd85f7b5036b0bcbd159
> --- /dev/null
> +++ b/drivers/pinctrl/mediatek/pinctrl-mt6878.c
> @@ -0,0 +1,1559 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Copyright (C) 2023 MediaTek Inc.
> + * Author: Light Hsieh <light.hsieh@mediatek.com>
> + *
> + * Copyright (C) 2025 Igor Belwon <igor.belwon@mentallysanemainliners.org>
> + */
> +
> +#include <linux/module.h>
> +#include "pinctrl-mtk-mt6878.h"
> +#include "pinctrl-paris.h"
> +
> +/* MT6878 have multiple bases to program pin configuration listed as the below:
> + * GPIO_BASE: 0x10005000
> + * IOCFG_BL_BASE: 0x11D10000
> + * IOCFG_BM_BASE: 0x11D30000
> + * IOCFG_BR_BASE: 0x11D40000
> + * IOCFG_BL1_BASE: 0x11D50000
> + * IOCFG_BR1_BASE: 0x11D60000
> + * IOCFG_LM_BASE: 0x11E20000
> + * IOCFG_LT_BASE: 0x11E30000
> + * IOCFG_RM_BASE: 0x11EB0000
> + * IOCFG_RT_BASE: 0x11EC0000
> + * _i_based could be used to indicate what base the pin should be mapped into.
> + */
> +
> +#define PIN_FIELD_BASE(s_pin, e_pin, i_base, s_addr, x_addrs, s_bit, x_bits) \
> +	PIN_FIELD_CALC(s_pin, e_pin, i_base, s_addr, x_addrs, s_bit, x_bits, \
> +			32, 0)
> +
> +#define PINS_FIELD_BASE(s_pin, e_pin, i_base, s_addr, x_addrs, s_bit, x_bits) \
> +	PIN_FIELD_CALC(s_pin, e_pin, i_base, s_addr, x_addrs, s_bit, x_bits,  \
> +			32, 1)
> +
> +static const struct mtk_pin_field_calc mt6878_pin_mode_range[] = {

The mode range can be also written simply as:


static const struct mtk_pin_field_calc mt6878_pin_mode_range[] = {
	PIN_FIELD(0, 195, 0x0300, 0x10, 0, 4),
};


> +	PIN_FIELD_BASE(0, 7, 0, 0x0300, 0x10, 0, 4),
> +	PIN_FIELD_BASE(8, 15, 0, 0x0310, 0x10, 0, 4),
> +	PIN_FIELD_BASE(16, 23, 0, 0x0320, 0x10, 0, 4),
> +	PIN_FIELD_BASE(24, 31, 0, 0x0330, 0x10, 0, 4),
> +	PIN_FIELD_BASE(32, 39, 0, 0x0340, 0x10, 0, 4),
> +	PIN_FIELD_BASE(40, 47, 0, 0x0350, 0x10, 0, 4),
> +	PIN_FIELD_BASE(48, 55, 0, 0x0360, 0x10, 0, 4),
> +	PIN_FIELD_BASE(56, 63, 0, 0x0370, 0x10, 0, 4),
> +	PIN_FIELD_BASE(64, 71, 0, 0x0380, 0x10, 0, 4),
> +	PIN_FIELD_BASE(72, 79, 0, 0x0390, 0x10, 0, 4),
> +	PIN_FIELD_BASE(80, 87, 0, 0x03a0, 0x10, 0, 4),
> +	PIN_FIELD_BASE(88, 95, 0, 0x03b0, 0x10, 0, 4),
> +	PIN_FIELD_BASE(96, 103, 0, 0x03c0, 0x10, 0, 4),
> +	PIN_FIELD_BASE(104, 111, 0, 0x03d0, 0x10, 0, 4),
> +	PIN_FIELD_BASE(112, 119, 0, 0x03e0, 0x10, 0, 4),
> +	PIN_FIELD_BASE(120, 127, 0, 0x03f0, 0x10, 0, 4),
> +	PIN_FIELD_BASE(128, 135, 0, 0x0400, 0x10, 0, 4),
> +	PIN_FIELD_BASE(136, 143, 0, 0x0410, 0x10, 0, 4),
> +	PIN_FIELD_BASE(144, 151, 0, 0x0420, 0x10, 0, 4),
> +	PIN_FIELD_BASE(152, 159, 0, 0x0430, 0x10, 0, 4),
> +	PIN_FIELD_BASE(160, 167, 0, 0x0440, 0x10, 0, 4),
> +	PIN_FIELD_BASE(168, 175, 0, 0x0450, 0x10, 0, 4),
> +	PIN_FIELD_BASE(176, 183, 0, 0x0460, 0x10, 0, 4),
> +	PIN_FIELD_BASE(184, 191, 0, 0x0470, 0x10, 0, 4),
> +	PIN_FIELD_BASE(192, 195, 0, 0x0480, 0x10, 0, 4),
> +};
> +
> +static const struct mtk_pin_field_calc mt6878_pin_dir_range[] = {

Same for direction
> +	PIN_FIELD_BASE(0, 31, 0, 0x0000, 0x10, 0, 1),
> +	PIN_FIELD_BASE(32, 63, 0, 0x0010, 0x10, 0, 1),
> +	PIN_FIELD_BASE(64, 95, 0, 0x0020, 0x10, 0, 1),
> +	PIN_FIELD_BASE(96, 127, 0, 0x0030, 0x10, 0, 1),
> +	PIN_FIELD_BASE(128, 159, 0, 0x0040, 0x10, 0, 1),
> +	PIN_FIELD_BASE(160, 191, 0, 0x0050, 0x10, 0, 1),
> +	PIN_FIELD_BASE(192, 195, 0, 0x0060, 0x10, 0, 1),
> +};
> +
> +static const struct mtk_pin_field_calc mt6878_pin_di_range[] = {

Same here again

> +	PIN_FIELD_BASE(0, 31, 0, 0x0200, 0x10, 0, 1),
> +	PIN_FIELD_BASE(32, 63, 0, 0x0210, 0x10, 0, 1),
> +	PIN_FIELD_BASE(64, 95, 0, 0x0220, 0x10, 0, 1),
> +	PIN_FIELD_BASE(96, 127, 0, 0x0230, 0x10, 0, 1),
> +	PIN_FIELD_BASE(128, 159, 0, 0x0240, 0x10, 0, 1),
> +	PIN_FIELD_BASE(160, 191, 0, 0x0250, 0x10, 0, 1),
> +	PIN_FIELD_BASE(192, 195, 0, 0x0260, 0x10, 0, 1),
> +};
> +
> +static const struct mtk_pin_field_calc mt6878_pin_do_range[] = {

And here.

> +	PIN_FIELD_BASE(0, 31, 0, 0x0100, 0x10, 0, 1),
> +	PIN_FIELD_BASE(32, 63, 0, 0x0110, 0x10, 0, 1),
> +	PIN_FIELD_BASE(64, 95, 0, 0x0120, 0x10, 0, 1),
> +	PIN_FIELD_BASE(96, 127, 0, 0x0130, 0x10, 0, 1),
> +	PIN_FIELD_BASE(128, 159, 0, 0x0140, 0x10, 0, 1),
> +	PIN_FIELD_BASE(160, 191, 0, 0x0150, 0x10, 0, 1),
> +	PIN_FIELD_BASE(192, 195, 0, 0x0160, 0x10, 0, 1),
> +};
> +
> +static const struct mtk_pin_field_calc mt6878_pin_ies_range[] = {

..snip..

> +};
> +
> +static const struct mtk_pin_field_calc mt6878_pin_smt_range[] = {

..snip..

> +static const struct mtk_pin_field_calc mt6878_pin_eh_range[] = {

This is mt6878_pin_drv_adv_range[]

> +	PIN_FIELD_BASE(19, 19, 3, 0x0030, 0x10, 0, 3),
> +	PIN_FIELD_BASE(24, 24, 5, 0x0020, 0x10, 0, 3),
> +	PIN_FIELD_BASE(25, 25, 3, 0x0030, 0x10, 3, 3),
> +	PIN_FIELD_BASE(26, 26, 3, 0x0030, 0x10, 6, 3),
> +	PIN_FIELD_BASE(52, 52, 3, 0x0030, 0x10, 12, 3),
> +	PIN_FIELD_BASE(53, 53, 3, 0x0030, 0x10, 15, 3),
> +	PIN_FIELD_BASE(55, 55, 3, 0x0030, 0x10, 9, 3),
> +	PIN_FIELD_BASE(60, 60, 8, 0x0050, 0x10, 12, 3),
> +	PIN_FIELD_BASE(61, 61, 8, 0x0050, 0x10, 15, 3),
> +	PIN_FIELD_BASE(62, 62, 8, 0x0050, 0x10, 21, 3),
> +	PIN_FIELD_BASE(63, 63, 8, 0x0050, 0x10, 18, 3),
> +	PIN_FIELD_BASE(64, 64, 8, 0x0050, 0x10, 24, 3),
> +	PIN_FIELD_BASE(65, 65, 8, 0x0050, 0x10, 27, 3),
> +	PIN_FIELD_BASE(66, 66, 8, 0x0060, 0x10, 3, 3),
> +	PIN_FIELD_BASE(67, 67, 8, 0x0060, 0x10, 0, 3),
> +	PIN_FIELD_BASE(92, 92, 8, 0x0040, 0x10, 0, 3),
> +	PIN_FIELD_BASE(93, 93, 8, 0x0040, 0x10, 3, 3),
> +	PIN_FIELD_BASE(94, 94, 8, 0x0040, 0x10, 6, 3),
> +	PIN_FIELD_BASE(95, 95, 8, 0x0040, 0x10, 9, 3),
> +	PIN_FIELD_BASE(96, 96, 8, 0x0040, 0x10, 12, 3),
> +	PIN_FIELD_BASE(125, 125, 8, 0x0050, 0x10, 9, 3),
> +	PIN_FIELD_BASE(126, 126, 8, 0x0060, 0x10, 6, 3),
> +	PIN_FIELD_BASE(127, 127, 8, 0x0060, 0x10, 9, 3),
> +	PIN_FIELD_BASE(128, 128, 8, 0x0060, 0x10, 12, 3),
> +	PIN_FIELD_BASE(129, 129, 8, 0x0040, 0x10, 15, 3),
> +	PIN_FIELD_BASE(130, 130, 8, 0x0040, 0x10, 24, 3),
> +	PIN_FIELD_BASE(131, 131, 6, 0x0030, 0x10, 12, 3),
> +	PIN_FIELD_BASE(132, 132, 6, 0x0030, 0x10, 21, 3),
> +	PIN_FIELD_BASE(133, 133, 8, 0x0040, 0x10, 18, 3),
> +	PIN_FIELD_BASE(134, 134, 8, 0x0040, 0x10, 27, 3),
> +	PIN_FIELD_BASE(135, 135, 6, 0x0030, 0x10, 15, 3),
> +	PIN_FIELD_BASE(136, 136, 6, 0x0030, 0x10, 24, 3),
> +	PIN_FIELD_BASE(137, 137, 6, 0x0030, 0x10, 18, 3),
> +	PIN_FIELD_BASE(138, 138, 6, 0x0030, 0x10, 27, 3),
> +	PIN_FIELD_BASE(139, 139, 6, 0x0030, 0x10, 0, 3),
> +	PIN_FIELD_BASE(140, 140, 6, 0x0030, 0x10, 6, 3),
> +	PIN_FIELD_BASE(141, 141, 6, 0x0030, 0x10, 3, 3),
> +	PIN_FIELD_BASE(142, 142, 6, 0x0030, 0x10, 9, 3),
> +	PIN_FIELD_BASE(143, 143, 8, 0x0040, 0x10, 21, 3),
> +	PIN_FIELD_BASE(144, 144, 8, 0x0050, 0x10, 0, 3),
> +	PIN_FIELD_BASE(145, 145, 5, 0x0020, 0x10, 3, 3),
> +	PIN_FIELD_BASE(146, 146, 5, 0x0020, 0x10, 6, 3),
> +	PIN_FIELD_BASE(147, 147, 3, 0x0030, 0x10, 18, 3),
> +	PIN_FIELD_BASE(148, 148, 3, 0x0030, 0x10, 21, 3),
> +	PIN_FIELD_BASE(149, 149, 8, 0x0050, 0x10, 3, 3),
> +	PIN_FIELD_BASE(150, 150, 8, 0x0050, 0x10, 6, 3),
> +	PIN_FIELD_BASE(156, 156, 9, 0x0020, 0x10, 0, 5),
> +	PIN_FIELD_BASE(157, 157, 9, 0x0020, 0x10, 5, 5),
> +	PIN_FIELD_BASE(158, 158, 9, 0x0020, 0x10, 10, 5),
> +	PIN_FIELD_BASE(159, 159, 9, 0x0020, 0x10, 15, 5),
> +};
> +

> +
> +static const struct mtk_eh_pin_pinmux mt6878_eh_pin_pinmux_list[] = {

This can be removed entirely

> +	PIN_MUX_EH(19, 3),
> +	PIN_MUX_EH(24, 2),
> +	PIN_MUX_EH(24, 3),
> +	PIN_MUX_EH(25, 2),
> +	PIN_MUX_EH(26, 2),
> +	PIN_MUX_EH(52, 3),
> +	PIN_MUX_EH(53, 3),
> +	PIN_MUX_EH(55, 3),
> +	PIN_MUX_EH(125, 1),
> +	PIN_MUX_EH(126, 1),
> +	PIN_MUX_EH(127, 1),
> +	PIN_MUX_EH(128, 1),
> +	PIN_MUX_EH(129, 1),
> +	PIN_MUX_EH(130, 1),
> +	PIN_MUX_EH(131, 1),
> +	PIN_MUX_EH(132, 1),
> +	PIN_MUX_EH(133, 1),
> +	PIN_MUX_EH(134, 1),
> +	PIN_MUX_EH(135, 1),
> +	PIN_MUX_EH(136, 1),
> +	PIN_MUX_EH(137, 1),
> +	PIN_MUX_EH(138, 1),
> +	PIN_MUX_EH(139, 1),
> +	PIN_MUX_EH(140, 1),
> +	PIN_MUX_EH(141, 1),
> +	PIN_MUX_EH(142, 1),
> +	PIN_MUX_EH(143, 1),
> +	PIN_MUX_EH(144, 1),
> +	PIN_MUX_EH(145, 1),
> +	PIN_MUX_EH(146, 1),
> +	PIN_MUX_EH(147, 1),
> +	PIN_MUX_EH(148, 1),
> +	PIN_MUX_EH(149, 6),
> +	PIN_MUX_EH(150, 6),
> +};
> +
> +static const char * const mt6878_pinctrl_register_base_names[] = {
> +	"gpio", "iocfg_bl", "iocfg_bm", "iocfg_br",
> +	"iocfg_bl1", "iocfg_br1", "iocfg_lm", "iocfg_lt",
> +	"iocfg_rm", "iocfg_rt",
> +};
> +
> +static const struct mtk_eint_hw mt6878_eint_hw = {
> +	.port_mask = 31,
> +	.ports     = 1,
> +	.ap_num    = 216,
> +	.db_cnt    = 36,
> +	.db_time   = debounce_time_mt6878,
> +};
> +
> +static const struct mtk_pin_reg_calc mt6878_reg_cals[PINCTRL_PIN_REG_MAX] = {
> +	[PINCTRL_PIN_REG_MODE] = MTK_RANGE(mt6878_pin_mode_range),
> +	[PINCTRL_PIN_REG_DIR] = MTK_RANGE(mt6878_pin_dir_range),
> +	[PINCTRL_PIN_REG_DI] = MTK_RANGE(mt6878_pin_di_range),
> +	[PINCTRL_PIN_REG_DO] = MTK_RANGE(mt6878_pin_do_range),
> +	[PINCTRL_PIN_REG_SR] = MTK_RANGE(mt6878_pin_dir_range),
> +	[PINCTRL_PIN_REG_SMT] = MTK_RANGE(mt6878_pin_smt_range),
> +	[PINCTRL_PIN_REG_IES] = MTK_RANGE(mt6878_pin_ies_range),
> +	[PINCTRL_PIN_REG_PU] = MTK_RANGE(mt6878_pin_pu_range),
> +	[PINCTRL_PIN_REG_PD] = MTK_RANGE(mt6878_pin_pd_range),
> +	[PINCTRL_PIN_REG_DRV] = MTK_RANGE(mt6878_pin_drv_range),
> +	[PINCTRL_PIN_REG_PUPD] = MTK_RANGE(mt6878_pin_pupd_range),
> +	[PINCTRL_PIN_REG_R0] = MTK_RANGE(mt6878_pin_r0_range),
> +	[PINCTRL_PIN_REG_R1] = MTK_RANGE(mt6878_pin_r1_range),
> +	[PINCTRL_PIN_REG_DRV_EH] = MTK_RANGE(mt6878_pin_eh_range),

[PINCTRL_PIN_REG_DRV_ADV] = MTK_RANGE(mt6878_pin_drv_adv_range),

> +	[PINCTRL_PIN_REG_RSEL] = MTK_RANGE(mt6878_pin_rsel_range),
> +};
> +
> +static const struct mtk_pin_soc mt6878_data = {
> +	.reg_cal = mt6878_reg_cals,
> +	.pins = mtk_pins_mt6878,
> +	.npins = ARRAY_SIZE(mtk_pins_mt6878),
> +	.ngrps = ARRAY_SIZE(mtk_pins_mt6878),
> +	.eint_pin = eint_pins_mt6878,
> +	.eint_hw = &mt6878_eint_hw,
> +	.nfuncs = 8,
> +	.gpio_m = 0,
> +	.base_names = mt6878_pinctrl_register_base_names,
> +	.nbase_names = ARRAY_SIZE(mt6878_pinctrl_register_base_names),
> +	.bias_set_combo = mtk_pinconf_bias_set_combo,
> +	.bias_get_combo = mtk_pinconf_bias_get_combo,
> +	.pull_type = mt6878_pull_type,

vvvvvvvvvvvvvvvvvvvvvvvvvv

> +	.eh_pin_pinmux = mt6878_eh_pin_pinmux_list,
> +	.neh_pins = ARRAY_SIZE(mt6878_eh_pin_pinmux_list),

...and this can be removed as well.

> +	.adv_drive_get = mtk_pinconf_adv_drive_get,
> +	.adv_drive_set = mtk_pinconf_adv_drive_set,
> +};

Cheers,
Angelo


^ permalink raw reply	[flat|nested] 12+ messages in thread

end of thread, other threads:[~2025-09-09 12:14 UTC | newest]

Thread overview: 12+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2025-09-08 19:17 [PATCH 0/4] Add support for mt6878 pinctrl Igor Belwon
2025-09-08 19:17 ` [PATCH 1/4] dt-bindings: pinctrl: mediatek: Document MT6878 pin controller bindings Igor Belwon
2025-09-09  7:37   ` Krzysztof Kozlowski
2025-09-09 12:14     ` Igor Belwon
2025-09-08 19:17 ` [PATCH 2/4] pinctrl: mediatek: Add support for eh bit Igor Belwon
2025-09-09  7:57   ` AngeloGioacchino Del Regno
2025-09-09 11:53     ` Igor Belwon
2025-09-08 19:17 ` [PATCH 3/4] pinctrl: mediatek: Add debounce times for MT6878 Igor Belwon
2025-09-09  8:00   ` AngeloGioacchino Del Regno
2025-09-09 11:54     ` Igor Belwon
2025-09-08 19:17 ` [PATCH 4/4] pinctrl: mediatek: Add support for MT6878 pinctrl Igor Belwon
2025-09-09  7:59   ` AngeloGioacchino Del Regno

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