Re: [PATCH v3 16/30] gpu: nova-core: Hopper/Blackwell: add FSP falcon EMEM operations

[John Hubbard <jhubbard@nvidia.com>]

On 2/6/26 10:07 AM, Timur Tabi wrote:
> On Thu, 2026-02-05 at 20:21 -0800, John Hubbard wrote:
>> +/// EMEM control register bit 24: write mode.
>> +const EMEM_CTL_WRITE: u32 = 1 << 24;
>> +/// EMEM control register bit 25: read mode.
>> +const EMEM_CTL_READ: u32 = 1 << 25;
>> +
> 
> Shouldn't these be bits in the NV_PFALCON_FALCON_EMEM_CTL register instead?

Yes you are right. I've fixed it up for v3 like this:

diff --git a/drivers/gpu/nova-core/falcon/fsp.rs b/drivers/gpu/nova-core/falcon/fsp.rs
index 5152c2f1ed26..fb1c8c89d2ff 100644
--- a/drivers/gpu/nova-core/falcon/fsp.rs
+++ b/drivers/gpu/nova-core/falcon/fsp.rs
@@ -21,11 +21,6 @@
      },
  };
  
-/// EMEM control register bit 24: write mode.
-const EMEM_CTL_WRITE: u32 = 1 << 24;
-/// EMEM control register bit 25: read mode.
-const EMEM_CTL_READ: u32 = 1 << 25;
-
  /// Type specifying the `Fsp` falcon engine. Cannot be instantiated.
  pub(crate) struct Fsp(());
  
@@ -54,7 +49,8 @@ pub(crate) fn write_emem(&self, bar: &Bar0, offset: u32, data: &[u8]) -> Result
          }
  
          regs::NV_PFALCON_FALCON_EMEM_CTL::default()
-            .set_value(EMEM_CTL_WRITE | offset)
+            .set_wr_mode(true)
+            .set_offset(offset)
              .write(bar, &Fsp::ID);
  
          for chunk in data.chunks_exact(4) {
@@ -78,7 +74,8 @@ pub(crate) fn read_emem(&self, bar: &Bar0, offset: u32, data: &mut [u8]) -> Resu
          }
  
          regs::NV_PFALCON_FALCON_EMEM_CTL::default()
-            .set_value(EMEM_CTL_READ | offset)
+            .set_rd_mode(true)
+            .set_offset(offset)
              .write(bar, &Fsp::ID);
  
          for chunk in data.chunks_exact_mut(4) {
diff --git a/drivers/gpu/nova-core/regs.rs b/drivers/gpu/nova-core/regs.rs
index 30a5a49edeab..a9a65f98d8a3 100644
--- a/drivers/gpu/nova-core/regs.rs
+++ b/drivers/gpu/nova-core/regs.rs
@@ -434,7 +434,9 @@ pub(crate) fn reset_engine<E: FalconEngine>(bar: &Bar0) {
  // GP102 EMEM PIO registers (used by FSP for Hopper/Blackwell)
  // These registers provide falcon external memory communication interface
  register!(NV_PFALCON_FALCON_EMEM_CTL @ PFalconBase[0x00000ac0] {
-    31:0    value as u32;       // EMEM control register
+    23:0    offset as u32;      // EMEM byte offset (must be 4-byte aligned)
+    24:24   wr_mode as bool;    // Write mode
+    25:25   rd_mode as bool;    // Read mode
  });


thanks,
-- 
John Hubbard