mirror of https://lore.kernel.org/lkml/
 help / color / mirror / Atom feed
From: Niklas Cassel <niklas.cassel@axis.com>
To: Kishon Vijay Abraham I <kishon@ti.com>,
	Jingoo Han <jingoohan1@gmail.com>,
	Joao Pinto <Joao.Pinto@synopsys.com>,
	Bjorn Helgaas <bhelgaas@google.com>
Cc: <linux-pci@vger.kernel.org>, <linux-kernel@vger.kernel.org>
Subject: Re: [PATCH v2 04/17] PCI: designware-ep: Pre-allocate memory for MSI in dw_pcie_ep_init
Date: Tue, 31 Oct 2017 21:57:11 +0100	[thread overview]
Message-ID: <e26e36c8-8442-dd23-67e3-fe90d9b89c15@axis.com> (raw)
In-Reply-To: <9d4c17b7-94ec-fd79-4bd8-8165019f04ce@ti.com>

On 10/31/2017 07:01 AM, Kishon Vijay Abraham I wrote:
> Hi Niklas,
> 
> On Monday 30 October 2017 06:12 PM, Niklas Cassel wrote:
>> Certain SoCs need to map the MSI address in raise_irq.
>> To map an address, you first need to call pci_epc_mem_alloc_addr,
>> however, pci_epc_mem_alloc_addr calls ioremap (which can sleep).
>>
>> Since raise_irq is only called from atomic context, we can't call
>> pci_epc_mem_alloc_addr from raise_irq, instead we pre-allocate
>> a page in dw_pcie_ep_init, so this page can later be used to map/unmap
>> the MSI address in raise_irq.
>>
>> Signed-off-by: Niklas Cassel <niklas.cassel@axis.com>
>> ---
>> V2:
>> * No change.
>>
>>  drivers/pci/dwc/pcie-designware-ep.c | 8 ++++++++
>>  drivers/pci/dwc/pcie-designware.h    | 2 ++
>>  2 files changed, 10 insertions(+)
>>
>> diff --git a/drivers/pci/dwc/pcie-designware-ep.c b/drivers/pci/dwc/pcie-designware-ep.c
>> index 3fb34be99715..c291da2a10ba 100644
>> --- a/drivers/pci/dwc/pcie-designware-ep.c
>> +++ b/drivers/pci/dwc/pcie-designware-ep.c
>> @@ -286,6 +286,8 @@ void dw_pcie_ep_exit(struct dw_pcie_ep *ep)
>>  {
>>  	struct pci_epc *epc = ep->epc;
>>  
>> +	pci_epc_mem_free_addr(epc, ep->msi_mem_phys, ep->msi_mem, PAGE_SIZE);
>> +
>>  	pci_epc_mem_exit(epc);
>>  }
>>  
>> @@ -341,6 +343,12 @@ int dw_pcie_ep_init(struct dw_pcie_ep *ep)
>>  		return ret;
>>  	}
>>  
>> +	ep->msi_mem = pci_epc_mem_alloc_addr(epc, &ep->msi_mem_phys, PAGE_SIZE);
> 
> ep->page_size instead of PAGE_SIZE?

Hello Kishon,

Sure thing, will fix in V3.

Regards,
Niklas

  reply	other threads:[~2017-10-31 20:57 UTC|newest]

Thread overview: 30+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2017-10-30 12:42 [PATCH v2 00/17] dwc MSI fixes, ARTPEC-6 EP mode support, ARTPEC-7 SoC support Niklas Cassel
2017-10-30 12:42 ` [PATCH v2 01/17] PCI: dwc: Use DMA-API for allocating MSI data Niklas Cassel
2017-10-30 12:42 ` [PATCH v2 02/17] PCI: designware-ep: dw_pcie_ep_set_msi() should only set MMC bits Niklas Cassel
2017-10-30 12:42 ` [PATCH v2 03/17] PCI: designware-ep: Read-only registers need DBI_RO_WR_EN to be writable Niklas Cassel
2017-10-30 12:42 ` [PATCH v2 04/17] PCI: designware-ep: Pre-allocate memory for MSI in dw_pcie_ep_init Niklas Cassel
2017-10-31  6:01   ` Kishon Vijay Abraham I
2017-10-31 20:57     ` Niklas Cassel [this message]
2017-11-16 17:16     ` Niklas Cassel
2017-10-30 12:42 ` [PATCH v2 05/17] PCI: designware-ep: Remove static keyword from dw_pcie_ep_reset_bar() Niklas Cassel
2017-10-31  5:09   ` Kishon Vijay Abraham I
2017-10-30 12:42 ` [PATCH v2 06/17] PCI: designware-ep: Add generic function for raising MSI irq Niklas Cassel
2017-10-31  6:22   ` Kishon Vijay Abraham I
2017-10-31 21:06     ` Niklas Cassel
2017-10-30 12:42 ` [PATCH v2 07/17] PCI: dwc: dra7xx: Refactor Kconfig and Makefile handling for host/ep mode Niklas Cassel
2017-10-31  6:23   ` Kishon Vijay Abraham I
2017-10-30 12:42 ` [PATCH v2 08/17] PCI: dwc: dra7xx: Assign pp->ops in dra7xx_add_pcie_port() rather than in probe Niklas Cassel
2017-10-31  8:14   ` Kishon Vijay Abraham I
2017-10-30 12:42 ` [PATCH v2 09/17] PCI: dwc: dra7xx: Add ifdefs for host/ep specific code Niklas Cassel
2017-10-31  8:29   ` Kishon Vijay Abraham I
2017-10-31 21:27     ` Niklas Cassel
2017-10-31 21:38       ` Niklas Cassel
2017-10-31 22:51         ` Niklas Cassel
2017-10-30 12:42 ` [PATCH v2 10/17] PCI: dwc: artpec6: Remove unused defines Niklas Cassel
2017-10-30 12:42 ` [PATCH v2 11/17] PCI: dwc: artpec6: Use BIT and GENMASK macros Niklas Cassel
2017-10-30 12:42 ` [PATCH v2 12/17] PCI: dwc: artpec6: Split artpec6_pcie_establish_link to smaller functions Niklas Cassel
2017-10-30 12:42 ` [PATCH v2 13/17] bindings: PCI: artpec: Add support for endpoint mode Niklas Cassel
2017-10-30 12:42 ` [PATCH v2 14/17] PCI: dwc: artpec6: " Niklas Cassel
2017-10-30 12:42 ` [PATCH v2 15/17] PCI: dwc: Make cpu_addr_fixup take struct dw_pcie as argument Niklas Cassel
2017-10-30 12:42 ` [PATCH v2 16/17] bindings: PCI: artpec: Add support for the ARTPEC-7 SoC Niklas Cassel
2017-10-30 12:42 ` [PATCH v2 17/17] PCI: dwc: artpec6: " Niklas Cassel

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=e26e36c8-8442-dd23-67e3-fe90d9b89c15@axis.com \
    --to=niklas.cassel@axis.com \
    --cc=Joao.Pinto@synopsys.com \
    --cc=bhelgaas@google.com \
    --cc=jingoohan1@gmail.com \
    --cc=kishon@ti.com \
    --cc=linux-kernel@vger.kernel.org \
    --cc=linux-pci@vger.kernel.org \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox

all inboxes | Powered by JetHome®