mirror of https://lore.kernel.org/lkml/
 help / color / mirror / Atom feed
From: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
To: Anusha Arun Nandi <anusha.nandi@oss.qualcomm.com>,
	david@ixit.cz, andersson@kernel.org, konradybcio@kernel.org,
	robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org,
	bod@kernel.org, vladimir.zapolskiy@linaro.org,
	loic.poulain@oss.qualcomm.com, mchehab@kernel.org
Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org,
	linux-kernel@vger.kernel.org,
	gjorgji.rosikopulos@oss.qualcomm.com,
	jigarkumar.zala@oss.qualcomm.com,
	hariram.purushothaman@oss.qualcomm.com, akapatra@quicinc.com,
	linux-media@vger.kernel.org,
	krzysztof.kozlowski@oss.qualcomm.com, daniel@quora.org,
	konrad.dybcio@oss.qualcomm.com, christopher.obbard@linaro.org,
	alex.vinarskis@gmail.com
Subject: Re: [PATCH 1/3] phy: core: add generic MIPI C-PHY configuration API
Date: Fri, 23 Oct 2026 03:15:48 +0100	[thread overview]
Message-ID: <e3d322a0-43d5-4369-bd09-128152f4b233@linaro.org> (raw)
In-Reply-To: <f689ccfe-4adb-41f6-b492-97a48090413d@oss.qualcomm.com>

On 23/10/2026 01:33, Anusha Arun Nandi wrote:
>>> +    if (!cfg || !lanes)
>>> +        return -EINVAL;
>> Lanes must be a multiple of three to be valid, at least for your three
>> submissions to be logically consistent, this statement must be so.
>>
> I will update the name of lanes to data_lanes in
> phy_configure_opts_mipi_cphy struct.
> I will add more sanity checks for data_lanes > 3, as C-PHY supports 3
> data lanes only.

Sorry the only thing weirder than arguing with other people on the 
internet is arguing with yourself.

I argued myself down from this.

=>

One CPHY lane is 3 three wires. So data-lanes = <1> means three wire 
that only the PHY driver understands.

We communicate in lanes not in pads. There is no meaningful way to 
specify pads in DT - only lanes.

Which means lanes - I think we should follow what struct phy_mipi_dphy 
already models for us:

/**
  * struct phy_configure_opts_mipi_dphy - MIPI D-PHY configuration set
  *
  * This structure is used to represent the configuration state of a
  * MIPI D-PHY phy.
  */
struct phy_configure_opts_mipi_dphy {

         /**
          * @lanes:
          *
          * Number of active, consecutive, data lanes, starting from
          * lane 0, used for the transmissions.
          */
         unsigned char           lanes;
};

For example in DPHY lane == "two pads on the SoC" so for us in CPHY mode 
lane == "three pads on the SoC", there's no need to deviate from that.

The CSID needs to know the symbol rate - so that it can vote on the 
appropriate NOC/CamNOC clocks/rails but... does the PHY driver itself 
need to know that ? It does not, symbol_rate is not required in this 
struct no more than it is in DPHY.

Sample principle.

So _really_ thinking about this I suggest

- Following the DPHY example
- Including all of the CPHY specific timings
   The ones you posted, plus the few I found missing
   Any other relevant CPHY timings we may have missed
- Include the helper functions in drivers/phy/phy-core-mipi-cphy.c
   IMO we should use defines not hard-coded constants for the
   specification of the timings here, unlike the DPHY code

---
bod

  reply	other threads:[~2026-10-23  2:15 UTC|newest]

Thread overview: 13+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-10-17  4:17 [PATCH 0/3] phy: core, qcom-mipi-csi2: add generic MIPI C-PHY support Anusha Arun Nandi
2026-10-17  4:17 ` [PATCH 1/3] phy: core: add generic MIPI C-PHY configuration API Anusha Arun Nandi
2026-10-17 23:00   ` Bryan O'Donoghue
2026-10-19 10:24     ` Bryan O'Donoghue
2026-10-19 11:24       ` Bryan O'Donoghue
2026-10-19 14:15         ` Loic Poulain
2026-10-23  0:39           ` Anusha Arun Nandi
2026-10-23  1:06         ` Anusha Arun Nandi
2026-10-23  0:33     ` Anusha Arun Nandi
2026-10-23  2:15       ` Bryan O'Donoghue [this message]
2026-10-17  4:17 ` [PATCH 2/3] phy: qcom-mipi-csi2: Add sa8775p C-PHY support Anusha Arun Nandi
2026-10-17 23:19   ` Bryan O'Donoghue
2026-10-17  4:17 ` [PATCH 3/3] phy: qcom-mipi-csi2: Add sc7280 " Anusha Arun Nandi

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=e3d322a0-43d5-4369-bd09-128152f4b233@linaro.org \
    --to=bryan.odonoghue@linaro.org \
    --cc=akapatra@quicinc.com \
    --cc=alex.vinarskis@gmail.com \
    --cc=andersson@kernel.org \
    --cc=anusha.nandi@oss.qualcomm.com \
    --cc=bod@kernel.org \
    --cc=christopher.obbard@linaro.org \
    --cc=conor+dt@kernel.org \
    --cc=daniel@quora.org \
    --cc=david@ixit.cz \
    --cc=devicetree@vger.kernel.org \
    --cc=gjorgji.rosikopulos@oss.qualcomm.com \
    --cc=hariram.purushothaman@oss.qualcomm.com \
    --cc=jigarkumar.zala@oss.qualcomm.com \
    --cc=konrad.dybcio@oss.qualcomm.com \
    --cc=konradybcio@kernel.org \
    --cc=krzk+dt@kernel.org \
    --cc=krzysztof.kozlowski@oss.qualcomm.com \
    --cc=linux-arm-msm@vger.kernel.org \
    --cc=linux-kernel@vger.kernel.org \
    --cc=linux-media@vger.kernel.org \
    --cc=loic.poulain@oss.qualcomm.com \
    --cc=mchehab@kernel.org \
    --cc=robh@kernel.org \
    --cc=vladimir.zapolskiy@linaro.org \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox

all inboxes | Powered by JetHome®