[PATCH 0/3] cpufreq: mediatek: add mt6572 support

[PATCH 0/3] cpufreq: mediatek: add mt6572 support

[Roman Vivchar via B4 Relay]

This series adds support for mt6572 SoC frequency scaling.

Since there are (at least) 3 variants of this SoC, first patch adds
support for CPU speedbin. This is also useful for mt67xx family, which
has a lot of SoCs where the only difference is CPU/GPU clock.

Tested on both mt6572m (1 GHz limit) and mt6572w (1.4 GHz).

Signed-off-by: Roman Vivchar <rva333@protonmail.com>
---
Roman Vivchar (3):
      cpufreq: mediatek: add support for CPU speedbin
      cpufreq: mediatek: add mt6572 support
      cpufreq: dt-platdev: block the driver from probing on MediaTek mt6572

 drivers/cpufreq/cpufreq-dt-platdev.c |  1 +
 drivers/cpufreq/mediatek-cpufreq.c   | 59 ++++++++++++++++++++++++++++++++++--
 2 files changed, 58 insertions(+), 2 deletions(-)
---
base-commit: 8d3ae59288f1e7d58d76558a6ee96d533bc5019f
change-id: 20260923-6572-cpufreq-51645181e634

Best regards,
--  
Roman Vivchar <rva333@protonmail.com>

[PATCH 1/3] cpufreq: mediatek: add support for CPU speedbin

[Roman Vivchar via B4 Relay]

From: Roman Vivchar <rva333@protonmail.com>

MediaTek SoCs are often released under the same marketing name, but with
different suffix for the speedbin. For example, mt6572m has 1 GHz limit,
mt6572a - 1.2 GHz, mt6572w - 1.4 GHz.

Add code to support per-cluster 'opp-supported-hw' property. The DT is
expected to pass a CPU speedbin using standard 'nvmem-cells' property
under the CPU node.

Signed-off-by: Roman Vivchar <rva333@protonmail.com>
---
 drivers/cpufreq/mediatek-cpufreq.c | 50 ++++++++++++++++++++++++++++++++++++--
 1 file changed, 48 insertions(+), 2 deletions(-)

diff --git a/drivers/cpufreq/mediatek-cpufreq.c b/drivers/cpufreq/mediatek-cpufreq.c
index 052ca7cd2f4f..f15135b2898b 100644
--- a/drivers/cpufreq/mediatek-cpufreq.c
+++ b/drivers/cpufreq/mediatek-cpufreq.c
@@ -10,6 +10,7 @@
 #include <linux/cpumask.h>
 #include <linux/minmax.h>
 #include <linux/module.h>
+#include <linux/nvmem-consumer.h>
 #include <linux/of.h>
 #include <linux/of_platform.h>
 #include <linux/platform_device.h>
@@ -57,6 +58,7 @@ struct mtk_cpu_dvfs_info {
 	const struct mtk_cpufreq_platform_data *soc_data;
 	int vtrack_max;
 	bool ccifreq_bound;
+	int opp_token;
 };
 
 static struct platform_device *cpufreq_pdev;
@@ -381,6 +383,38 @@ static struct device *of_get_cci(struct device *cpu_dev)
 	return &pdev->dev;
 }
 
+static int mtk_cpu_parse_speedbin(struct mtk_cpu_dvfs_info *info, int cpu)
+{
+	struct device *cpu_dev = get_cpu_device(cpu);
+	struct dev_pm_opp_config config = {};
+	u32 val, opp_hw_ver;
+	int ret;
+
+	ret = nvmem_cell_read_variable_le_u32(cpu_dev, "speed_grade", &val);
+	if (ret) {
+		if (ret == -ENOENT)
+			/* speedbin is optional */
+			return 0;
+		return dev_err_probe(cpu_dev, ret, "cpu%d: failed to read speedbin\n", cpu);
+	}
+
+	/* Convert the raw value to a bitmask */
+	if (val >= 32)
+		return dev_err_probe(cpu_dev, -EINVAL,
+				     "cpu%d: invalid speedbin value %u\n", cpu, val);
+	opp_hw_ver = BIT(val);
+
+	config.supported_hw = &opp_hw_ver;
+	config.supported_hw_count = 1;
+
+	info->opp_token = dev_pm_opp_set_config(cpu_dev, &config);
+	if (info->opp_token < 0)
+		return dev_err_probe(cpu_dev, info->opp_token,
+				     "cpu%d: failed to set OPP config\n", cpu);
+
+	return 0;
+}
+
 static int mtk_cpu_dvfs_info_init(struct mtk_cpu_dvfs_info *info, int cpu)
 {
 	struct device *cpu_dev;
@@ -450,18 +484,22 @@ static int mtk_cpu_dvfs_info_init(struct mtk_cpu_dvfs_info *info, int cpu)
 		}
 	}
 
+	ret = mtk_cpu_parse_speedbin(info, cpu);
+	if (ret)
+		goto out_disable_sram_reg;
+
 	/* Get OPP-sharing information from "operating-points-v2" bindings */
 	ret = dev_pm_opp_of_get_sharing_cpus(cpu_dev, &info->cpus);
 	if (ret) {
 		dev_err_probe(cpu_dev, ret,
 			"cpu%d: failed to get OPP-sharing information\n", cpu);
-		goto out_disable_sram_reg;
+		goto out_free_speedbin;
 	}
 
 	ret = dev_pm_opp_of_cpumask_add_table(&info->cpus);
 	if (ret) {
 		dev_err_probe(cpu_dev, ret, "cpu%d: no OPP table\n", cpu);
-		goto out_disable_sram_reg;
+		goto out_free_speedbin;
 	}
 
 	ret = clk_prepare_enable(info->cpu_clk);
@@ -533,6 +571,10 @@ static int mtk_cpu_dvfs_info_init(struct mtk_cpu_dvfs_info *info, int cpu)
 out_free_opp_table:
 	dev_pm_opp_of_cpumask_remove_table(&info->cpus);
 
+out_free_speedbin:
+	if (info->opp_token > 0)
+		dev_pm_opp_clear_config(info->opp_token);
+
 out_disable_sram_reg:
 	if (info->sram_reg)
 		regulator_disable(info->sram_reg);
@@ -573,6 +615,10 @@ static void mtk_cpu_dvfs_info_release(struct mtk_cpu_dvfs_info *info)
 	clk_disable_unprepare(info->inter_clk);
 	clk_put(info->inter_clk);
 	dev_pm_opp_of_cpumask_remove_table(&info->cpus);
+
+	if (info->opp_token > 0)
+		dev_pm_opp_clear_config(info->opp_token);
+
 	dev_pm_opp_unregister_notifier(info->cpu_dev, &info->opp_nb);
 	if (info->soc_data->ccifreq_supported)
 		put_device(info->cci_dev);

-- 
2.55.0

Re: [PATCH 1/3] cpufreq: mediatek: add support for CPU speedbin

[AngeloGioacchino Del Regno]

On 9/23/26 09:23, Roman Vivchar via B4 Relay wrote:
> From: Roman Vivchar <rva333@protonmail.com>
> 
> MediaTek SoCs are often released under the same marketing name, but with
> different suffix for the speedbin. For example, mt6572m has 1 GHz limit,
> mt6572a - 1.2 GHz, mt6572w - 1.4 GHz.
> 
> Add code to support per-cluster 'opp-supported-hw' property. The DT is
> expected to pass a CPU speedbin using standard 'nvmem-cells' property
> under the CPU node.
> 
> Signed-off-by: Roman Vivchar <rva333@protonmail.com>
> ---
>   drivers/cpufreq/mediatek-cpufreq.c | 50 ++++++++++++++++++++++++++++++++++++--
>   1 file changed, 48 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/cpufreq/mediatek-cpufreq.c b/drivers/cpufreq/mediatek-cpufreq.c
> index 052ca7cd2f4f..f15135b2898b 100644
> --- a/drivers/cpufreq/mediatek-cpufreq.c
> +++ b/drivers/cpufreq/mediatek-cpufreq.c
> @@ -10,6 +10,7 @@
>   #include <linux/cpumask.h>
>   #include <linux/minmax.h>
>   #include <linux/module.h>
> +#include <linux/nvmem-consumer.h>
>   #include <linux/of.h>
>   #include <linux/of_platform.h>
>   #include <linux/platform_device.h>
> @@ -57,6 +58,7 @@ struct mtk_cpu_dvfs_info {
>   	const struct mtk_cpufreq_platform_data *soc_data;
>   	int vtrack_max;
>   	bool ccifreq_bound;
> +	int opp_token;
>   };
>   
>   static struct platform_device *cpufreq_pdev;
> @@ -381,6 +383,38 @@ static struct device *of_get_cci(struct device *cpu_dev)
>   	return &pdev->dev;
>   }
>   
> +static int mtk_cpu_parse_speedbin(struct mtk_cpu_dvfs_info *info, int cpu)
> +{
> +	struct device *cpu_dev = get_cpu_device(cpu);
> +	struct dev_pm_opp_config config = {};
> +	u32 val, opp_hw_ver;
> +	int ret;
> +
> +	ret = nvmem_cell_read_variable_le_u32(cpu_dev, "speed_grade", &val);

Let's keep consistency with cell names: for example, on the GPU side, the node
in devicetree is called "gpu-speedbin@1234", and the panfrost node has

nvmem-cells = <&gpu_speedbin>;
nvmem-cell-names = "speed-bin";

Check MT8186 and MT8188 devicetrees ;-)

> +	if (ret) {
> +		if (ret == -ENOENT)

if (ret != -ENOENT && ret != -EOPNOTSUPP)

> +			/* speedbin is optional */
> +			return 0;
> +		return dev_err_probe(cpu_dev, ret, "cpu%d: failed to read speedbin\n", cpu);
> +	}
> +
> +	/* Convert the raw value to a bitmask */
> +	if (val >= 32)
> +		return dev_err_probe(cpu_dev, -EINVAL,
> +				     "cpu%d: invalid speedbin value %u\n", cpu, val);
> +	opp_hw_ver = BIT(val);

If you look at nvmem/mtk-efuse.c there is a mtk_efuse_gpu_speedbin_pp() function
that is doing (almost) *exactly* what you're doing here.

Check if the same constraints as GPU speed binning applies to the CPU: if they do,
just allow "cpu-speedbin" as node name in the fixup function, otherwise add a new
post processing function for the CPU and act accordingly.

> +
> +	config.supported_hw = &opp_hw_ver;
> +	config.supported_hw_count = 1;
> +
> +	info->opp_token = dev_pm_opp_set_config(cpu_dev, &config);

It's way easier if you use

devm_pm_opp_set_supported_hw(dev, &opp_hw_ver, 1);

Cheers,
Angelo

> +	if (info->opp_token < 0)
> +		return dev_err_probe(cpu_dev, info->opp_token,
> +				     "cpu%d: failed to set OPP config\n", cpu);
> +
> +	return 0;
> +}
> +
>   static int mtk_cpu_dvfs_info_init(struct mtk_cpu_dvfs_info *info, int cpu)
>   {
>   	struct device *cpu_dev;
> @@ -450,18 +484,22 @@ static int mtk_cpu_dvfs_info_init(struct mtk_cpu_dvfs_info *info, int cpu)
>   		}
>   	}
>   
> +	ret = mtk_cpu_parse_speedbin(info, cpu);
> +	if (ret)
> +		goto out_disable_sram_reg;
> +
>   	/* Get OPP-sharing information from "operating-points-v2" bindings */
>   	ret = dev_pm_opp_of_get_sharing_cpus(cpu_dev, &info->cpus);
>   	if (ret) {
>   		dev_err_probe(cpu_dev, ret,
>   			"cpu%d: failed to get OPP-sharing information\n", cpu);
> -		goto out_disable_sram_reg;
> +		goto out_free_speedbin;
>   	}
>   
>   	ret = dev_pm_opp_of_cpumask_add_table(&info->cpus);
>   	if (ret) {
>   		dev_err_probe(cpu_dev, ret, "cpu%d: no OPP table\n", cpu);
> -		goto out_disable_sram_reg;
> +		goto out_free_speedbin;
>   	}
>   
>   	ret = clk_prepare_enable(info->cpu_clk);
> @@ -533,6 +571,10 @@ static int mtk_cpu_dvfs_info_init(struct mtk_cpu_dvfs_info *info, int cpu)
>   out_free_opp_table:
>   	dev_pm_opp_of_cpumask_remove_table(&info->cpus);
>   
> +out_free_speedbin:
> +	if (info->opp_token > 0)
> +		dev_pm_opp_clear_config(info->opp_token);
> +
>   out_disable_sram_reg:
>   	if (info->sram_reg)
>   		regulator_disable(info->sram_reg);
> @@ -573,6 +615,10 @@ static void mtk_cpu_dvfs_info_release(struct mtk_cpu_dvfs_info *info)
>   	clk_disable_unprepare(info->inter_clk);
>   	clk_put(info->inter_clk);
>   	dev_pm_opp_of_cpumask_remove_table(&info->cpus);
> +
> +	if (info->opp_token > 0)
> +		dev_pm_opp_clear_config(info->opp_token);
> +
>   	dev_pm_opp_unregister_notifier(info->cpu_dev, &info->opp_nb);
>   	if (info->soc_data->ccifreq_supported)
>   		put_device(info->cci_dev);
> 

Re: [PATCH 1/3] cpufreq: mediatek: add support for CPU speedbin

[Roman Vivchar]

Hi Angelo,

On Wednesday, September 23rd, 2026 at 11:31 AM, AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> wrote:

> On 9/23/26 09:23, Roman Vivchar via B4 Relay wrote:
> > From: Roman Vivchar <rva333@protonmail.com>
> >
> > MediaTek SoCs are often released under the same marketing name, but with
> > different suffix for the speedbin. For example, mt6572m has 1 GHz limit,
> > mt6572a - 1.2 GHz, mt6572w - 1.4 GHz.
> >
> > Add code to support per-cluster 'opp-supported-hw' property. The DT is
> > expected to pass a CPU speedbin using standard 'nvmem-cells' property
> > under the CPU node.
> >
> > Signed-off-by: Roman Vivchar <rva333@protonmail.com>
> > ---
> >   drivers/cpufreq/mediatek-cpufreq.c | 50 ++++++++++++++++++++++++++++++++++++--
> >   1 file changed, 48 insertions(+), 2 deletions(-)
> >
> > diff --git a/drivers/cpufreq/mediatek-cpufreq.c b/drivers/cpufreq/mediatek-cpufreq.c
> > index 052ca7cd2f4f..f15135b2898b 100644
> > --- a/drivers/cpufreq/mediatek-cpufreq.c
> > +++ b/drivers/cpufreq/mediatek-cpufreq.c
> > @@ -10,6 +10,7 @@
> >   #include <linux/cpumask.h>
> >   #include <linux/minmax.h>
> >   #include <linux/module.h>
> > +#include <linux/nvmem-consumer.h>
> >   #include <linux/of.h>
> >   #include <linux/of_platform.h>
> >   #include <linux/platform_device.h>
> > @@ -57,6 +58,7 @@ struct mtk_cpu_dvfs_info {
> >   	const struct mtk_cpufreq_platform_data *soc_data;
> >   	int vtrack_max;
> >   	bool ccifreq_bound;
> > +	int opp_token;
> >   };
> >
> >   static struct platform_device *cpufreq_pdev;
> > @@ -381,6 +383,38 @@ static struct device *of_get_cci(struct device *cpu_dev)
> >   	return &pdev->dev;
> >   }
> >
> > +static int mtk_cpu_parse_speedbin(struct mtk_cpu_dvfs_info *info, int cpu)
> > +{
> > +	struct device *cpu_dev = get_cpu_device(cpu);
> > +	struct dev_pm_opp_config config = {};
> > +	u32 val, opp_hw_ver;
> > +	int ret;
> > +
> > +	ret = nvmem_cell_read_variable_le_u32(cpu_dev, "speed_grade", &val);
> 
> Let's keep consistency with cell names: for example, on the GPU side, the node
> in devicetree is called "gpu-speedbin@1234", and the panfrost node has
> 
> nvmem-cells = <&gpu_speedbin>;
> nvmem-cell-names = "speed-bin";
> 
> Check MT8186 and MT8188 devicetrees ;-)

Not sure if it works like that. speed_grade comes from the arm/cpus.yaml.
Indeed I'd prefer some other name, but this means either modifying cpus.yaml
schema or making something like qcom's custom opp table binding.

> 
> > +	if (ret) {
> > +		if (ret == -ENOENT)
> 
> if (ret != -ENOENT && ret != -EOPNOTSUPP)

Ack.

> 
> > +			/* speedbin is optional */
> > +			return 0;
> > +		return dev_err_probe(cpu_dev, ret, "cpu%d: failed to read speedbin\n", cpu);
> > +	}
> > +
> > +	/* Convert the raw value to a bitmask */
> > +	if (val >= 32)
> > +		return dev_err_probe(cpu_dev, -EINVAL,
> > +				     "cpu%d: invalid speedbin value %u\n", cpu, val);
> > +	opp_hw_ver = BIT(val);
> 
> If you look at nvmem/mtk-efuse.c there is a mtk_efuse_gpu_speedbin_pp() function
> that is doing (almost) *exactly* what you're doing here.
> 
> Check if the same constraints as GPU speed binning applies to the CPU: if they do,
> just allow "cpu-speedbin" as node name in the fixup function, otherwise add a new
> post processing function for the CPU and act accordingly.

...right. Should this go as separate nvmem patch or include it in this
series?

> 
> > +
> > +	config.supported_hw = &opp_hw_ver;
> > +	config.supported_hw_count = 1;
> > +
> > +	info->opp_token = dev_pm_opp_set_config(cpu_dev, &config);
> 
> It's way easier if you use
> 
> devm_pm_opp_set_supported_hw(dev, &opp_hw_ver, 1);

Ack

Best regards,
Roman

[PATCH 2/3] cpufreq: mediatek: add mt6572 support

[Roman Vivchar via B4 Relay]

From: Roman Vivchar <rva333@protonmail.com>

Add mt6572 SoC platform data for CPU frequency scaling.

Signed-off-by: Roman Vivchar <rva333@protonmail.com>
---
 drivers/cpufreq/mediatek-cpufreq.c | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/drivers/cpufreq/mediatek-cpufreq.c b/drivers/cpufreq/mediatek-cpufreq.c
index f15135b2898b..615bccc77c98 100644
--- a/drivers/cpufreq/mediatek-cpufreq.c
+++ b/drivers/cpufreq/mediatek-cpufreq.c
@@ -737,6 +737,14 @@ static const struct mtk_cpufreq_platform_data mt2701_platform_data = {
 	.ccifreq_supported = false,
 };
 
+static const struct mtk_cpufreq_platform_data mt6572_platform_data = {
+	.min_volt_shift = 100000,
+	.max_volt_shift = 200000,
+	.proc_max_volt = 1250000,
+	.sram_min_volt = 0,
+	.ccifreq_supported = false,
+};
+
 static const struct mtk_cpufreq_platform_data mt7622_platform_data = {
 	.min_volt_shift = 100000,
 	.max_volt_shift = 200000,
@@ -793,6 +801,7 @@ static const struct mtk_cpufreq_platform_data mt8516_platform_data = {
 static const struct of_device_id mtk_cpufreq_machines[] __initconst __maybe_unused = {
 	{ .compatible = "mediatek,mt2701", .data = &mt2701_platform_data },
 	{ .compatible = "mediatek,mt2712", .data = &mt2701_platform_data },
+	{ .compatible = "mediatek,mt6572", .data = &mt6572_platform_data },
 	{ .compatible = "mediatek,mt7622", .data = &mt7622_platform_data },
 	{ .compatible = "mediatek,mt7623", .data = &mt7623_platform_data },
 	{ .compatible = "mediatek,mt7988a", .data = &mt7988_platform_data },

-- 
2.55.0

Re: [PATCH 2/3] cpufreq: mediatek: add mt6572 support

[AngeloGioacchino Del Regno]

On 9/23/26 09:23, Roman Vivchar via B4 Relay wrote:
> From: Roman Vivchar <rva333@protonmail.com>
> 
> Add mt6572 SoC platform data for CPU frequency scaling.
> 
> Signed-off-by: Roman Vivchar <rva333@protonmail.com>
> ---
>   drivers/cpufreq/mediatek-cpufreq.c | 9 +++++++++
>   1 file changed, 9 insertions(+)
> 
> diff --git a/drivers/cpufreq/mediatek-cpufreq.c b/drivers/cpufreq/mediatek-cpufreq.c
> index f15135b2898b..615bccc77c98 100644
> --- a/drivers/cpufreq/mediatek-cpufreq.c
> +++ b/drivers/cpufreq/mediatek-cpufreq.c
> @@ -737,6 +737,14 @@ static const struct mtk_cpufreq_platform_data mt2701_platform_data = {
>   	.ccifreq_supported = false,
>   };
>   
> +static const struct mtk_cpufreq_platform_data mt6572_platform_data = {
> +	.min_volt_shift = 100000,
> +	.max_volt_shift = 200000,
> +	.proc_max_volt = 1250000,
> +	.sram_min_volt = 0,

Are you sure that there's no SRAM regulator on MT6572?

If there's none, there's no need to set sram_min_volt here, but if there is, you
also need to set sram_max_volt.

The ccifreq_supported explicitly set to false is ok for human readability of the
SoC features - that's also unneeded but keep it for the same of understanding
what's going on with this SoC.

Cheers,
Angelo

> +	.ccifreq_supported = false,
> +};
> +

Re: [PATCH 2/3] cpufreq: mediatek: add mt6572 support

[Roman Vivchar]

On Wednesday, September 23rd, 2026 at 11:36 AM, AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> wrote:

> On 9/23/26 09:23, Roman Vivchar via B4 Relay wrote:
> > From: Roman Vivchar <rva333@protonmail.com>
> >
> > Add mt6572 SoC platform data for CPU frequency scaling.
> >
> > Signed-off-by: Roman Vivchar <rva333@protonmail.com>
> > ---
> >   drivers/cpufreq/mediatek-cpufreq.c | 9 +++++++++
> >   1 file changed, 9 insertions(+)
> >
> > diff --git a/drivers/cpufreq/mediatek-cpufreq.c b/drivers/cpufreq/mediatek-cpufreq.c
> > index f15135b2898b..615bccc77c98 100644
> > --- a/drivers/cpufreq/mediatek-cpufreq.c
> > +++ b/drivers/cpufreq/mediatek-cpufreq.c
> > @@ -737,6 +737,14 @@ static const struct mtk_cpufreq_platform_data mt2701_platform_data = {
> >   	.ccifreq_supported = false,
> >   };
> >
> > +static const struct mtk_cpufreq_platform_data mt6572_platform_data = {
> > +	.min_volt_shift = 100000,
> > +	.max_volt_shift = 200000,
> > +	.proc_max_volt = 1250000,
> > +	.sram_min_volt = 0,
> 
> Are you sure that there's no SRAM regulator on MT6572?

Yes. There's no 'sram' mention in the downstream code, neither mt6323 has sram
regulator.

> If there's none, there's no need to set sram_min_volt here,

Ack

> but if there is, you
> also need to set sram_max_volt.
> 
> The ccifreq_supported explicitly set to false is ok for human readability of the
> SoC features - that's also unneeded but keep it for the same of understanding
> what's going on with this SoC.
> 
> Cheers,
> Angelo
> 
> > +	.ccifreq_supported = false,
> > +};
> > +
> 
>

Best regards,
Roman

[PATCH 3/3] cpufreq: dt-platdev: block the driver from probing on MediaTek mt6572

[Roman Vivchar via B4 Relay]

From: Roman Vivchar <rva333@protonmail.com>

MediaTek SoCs use mediatek-cpufreq driver instead of generic one. Add
mt6572 to the blocklist.

Signed-off-by: Roman Vivchar <rva333@protonmail.com>
---
 drivers/cpufreq/cpufreq-dt-platdev.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/cpufreq/cpufreq-dt-platdev.c b/drivers/cpufreq/cpufreq-dt-platdev.c
index ff1204c666b1..ff7fb61eda74 100644
--- a/drivers/cpufreq/cpufreq-dt-platdev.c
+++ b/drivers/cpufreq/cpufreq-dt-platdev.c
@@ -132,6 +132,7 @@ static const struct of_device_id blocklist[] __initconst = {
 
 	{ .compatible = "mediatek,mt2701", },
 	{ .compatible = "mediatek,mt2712", },
+	{ .compatible = "mediatek,mt6572", },
 	{ .compatible = "mediatek,mt7622", },
 	{ .compatible = "mediatek,mt7623", },
 	{ .compatible = "mediatek,mt8167", },

-- 
2.55.0

Re: [PATCH 3/3] cpufreq: dt-platdev: block the driver from probing on MediaTek mt6572

[AngeloGioacchino Del Regno]

On 9/23/26 09:23, Roman Vivchar via B4 Relay wrote:
> From: Roman Vivchar <rva333@protonmail.com>
> 
> MediaTek SoCs use mediatek-cpufreq driver instead of generic one. Add
> mt6572 to the blocklist.
> 
> Signed-off-by: Roman Vivchar <rva333@protonmail.com>

Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>