[PATCH 0/2] Drop the mem noc clocks from the IPQ5332 GCC driver

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* [PATCH 0/2] Drop the mem noc clocks from the IPQ5332 GCC driver
@ 2023-07-10 10:28 Kathiravan T
  2023-07-10 10:28 ` [PATCH 1/2] clk: qcom: ipq5332: drop the mem noc clocks Kathiravan T
                   ` (3 more replies)
  0 siblings, 4 replies; 7+ messages in thread
From: Kathiravan T @ 2023-07-10 10:28 UTC (permalink / raw)
  To: Bjorn Andersson, Andy Gross, Konrad Dybcio, Michael Turquette,
	Stephen Boyd, linux-arm-msm, linux-clk, linux-kernel
  Cc: quic_srichara, quic_sjaganat, quic_anusha, quic_saahtoma, Kathiravan T

Due to the recent design changes, all the mem noc clocks will be
configured by the bootloaders and it will be access protected by the TZ
firmware. Also there are no comsumers for these clocks in the kernel. So
drop these clocks from the GCC driver.

With these clocks removal, remove the gcc_apss_axi_clk_src clock as well
since no clocks uses this as a parent.

Kathiravan T (2):
  clk: qcom: ipq5332: drop the mem noc clocks
  clk: qcom: ipq5332: drop the gcc_apss_axi_clk_src clock

 drivers/clk/qcom/gcc-ipq5332.c | 206 +++++++--------------------------
 1 file changed, 39 insertions(+), 167 deletions(-)

-- 
2.34.1


^ permalink raw reply	[flat|nested] 7+ messages in thread

* [PATCH 1/2] clk: qcom: ipq5332: drop the mem noc clocks
  2023-07-10 10:28 [PATCH 0/2] Drop the mem noc clocks from the IPQ5332 GCC driver Kathiravan T
@ 2023-07-10 10:28 ` Kathiravan T
  2023-07-15 14:10   ` Konrad Dybcio
  2023-07-10 10:28 ` [PATCH 2/2] clk: qcom: ipq5332: drop the gcc_apss_axi_clk_src clock Kathiravan T
                   ` (2 subsequent siblings)
  3 siblings, 1 reply; 7+ messages in thread
From: Kathiravan T @ 2023-07-10 10:28 UTC (permalink / raw)
  To: Bjorn Andersson, Andy Gross, Konrad Dybcio, Michael Turquette,
	Stephen Boyd, linux-arm-msm, linux-clk, linux-kernel
  Cc: quic_srichara, quic_sjaganat, quic_anusha, quic_saahtoma, Kathiravan T

Due to the recent design changes, all the mem noc clocks will be
configured by the bootloaders and it will be access protected by the TZ
firmware. So drop these clocks from the GCC driver.

Signed-off-by: Kathiravan T <quic_kathirav@quicinc.com>
---
 drivers/clk/qcom/gcc-ipq5332.c | 95 ----------------------------------
 1 file changed, 95 deletions(-)

diff --git a/drivers/clk/qcom/gcc-ipq5332.c b/drivers/clk/qcom/gcc-ipq5332.c
index a75ab88ed14c..939925baa9eb 100644
--- a/drivers/clk/qcom/gcc-ipq5332.c
+++ b/drivers/clk/qcom/gcc-ipq5332.c
@@ -1635,42 +1635,6 @@ static struct clk_branch gcc_mdio_slave_ahb_clk = {
 	},
 };
 
-static struct clk_branch gcc_mem_noc_q6_axi_clk = {
-	.halt_reg = 0x19010,
-	.halt_check = BRANCH_HALT,
-	.clkr = {
-		.enable_reg = 0x19010,
-		.enable_mask = BIT(0),
-		.hw.init = &(const struct clk_init_data) {
-			.name = "gcc_mem_noc_q6_axi_clk",
-			.parent_hws = (const struct clk_hw*[]) {
-				&gcc_q6_axim_clk_src.clkr.hw,
-			},
-			.num_parents = 1,
-			.flags = CLK_SET_RATE_PARENT,
-			.ops = &clk_branch2_ops,
-		},
-	},
-};
-
-static struct clk_branch gcc_mem_noc_ts_clk = {
-	.halt_reg = 0x19028,
-	.halt_check = BRANCH_HALT_VOTED,
-	.clkr = {
-		.enable_reg = 0x19028,
-		.enable_mask = BIT(0),
-		.hw.init = &(const struct clk_init_data) {
-			.name = "gcc_mem_noc_ts_clk",
-			.parent_hws = (const struct clk_hw*[]) {
-				&gcc_qdss_tsctr_div8_clk_src.hw,
-			},
-			.num_parents = 1,
-			.flags = CLK_SET_RATE_PARENT,
-			.ops = &clk_branch2_ops,
-		},
-	},
-};
-
 static struct clk_branch gcc_nss_ts_clk = {
 	.halt_reg = 0x17018,
 	.halt_check = BRANCH_HALT_VOTED,
@@ -3339,42 +3303,6 @@ static struct clk_branch gcc_nssnoc_pcnoc_1_clk = {
 	},
 };
 
-static struct clk_branch gcc_mem_noc_ahb_clk = {
-	.halt_reg = 0x1900c,
-	.halt_check = BRANCH_HALT,
-	.clkr = {
-		.enable_reg = 0x1900c,
-		.enable_mask = BIT(0),
-		.hw.init = &(const struct clk_init_data) {
-			.name = "gcc_mem_noc_ahb_clk",
-			.parent_hws = (const struct clk_hw*[]) {
-				&gcc_pcnoc_bfdcd_clk_src.clkr.hw,
-			},
-			.num_parents = 1,
-			.flags = CLK_SET_RATE_PARENT,
-			.ops = &clk_branch2_ops,
-		},
-	},
-};
-
-static struct clk_branch gcc_mem_noc_apss_axi_clk = {
-	.halt_reg = 0x1901c,
-	.halt_check = BRANCH_HALT_VOTED,
-	.clkr = {
-		.enable_reg = 0xb004,
-		.enable_mask = BIT(6),
-		.hw.init = &(const struct clk_init_data) {
-			.name = "gcc_mem_noc_apss_axi_clk",
-			.parent_hws = (const struct clk_hw*[]) {
-				&gcc_apss_axi_clk_src.clkr.hw,
-			},
-			.num_parents = 1,
-			.flags = CLK_SET_RATE_PARENT,
-			.ops = &clk_branch2_ops,
-		},
-	},
-};
-
 static struct clk_regmap_div gcc_snoc_qosgen_extref_div_clk_src = {
 	.reg = 0x2e010,
 	.shift = 0,
@@ -3390,24 +3318,6 @@ static struct clk_regmap_div gcc_snoc_qosgen_extref_div_clk_src = {
 	},
 };
 
-static struct clk_branch gcc_mem_noc_qosgen_extref_clk = {
-	.halt_reg = 0x19024,
-	.halt_check = BRANCH_HALT,
-	.clkr = {
-		.enable_reg = 0x19024,
-		.enable_mask = BIT(0),
-		.hw.init = &(const struct clk_init_data) {
-			.name = "gcc_mem_noc_qosgen_extref_clk",
-			.parent_hws = (const struct clk_hw*[]) {
-				&gcc_snoc_qosgen_extref_div_clk_src.clkr.hw,
-			},
-			.num_parents = 1,
-			.flags = CLK_SET_RATE_PARENT,
-			.ops = &clk_branch2_ops,
-		},
-	},
-};
-
 static struct clk_regmap *gcc_ipq5332_clocks[] = {
 	[GPLL0_MAIN] = &gpll0_main.clkr,
 	[GPLL0] = &gpll0.clkr,
@@ -3451,8 +3361,6 @@ static struct clk_regmap *gcc_ipq5332_clocks[] = {
 	[GCC_LPASS_SWAY_CLK_SRC] = &gcc_lpass_sway_clk_src.clkr,
 	[GCC_MDIO_AHB_CLK] = &gcc_mdio_ahb_clk.clkr,
 	[GCC_MDIO_SLAVE_AHB_CLK] = &gcc_mdio_slave_ahb_clk.clkr,
-	[GCC_MEM_NOC_Q6_AXI_CLK] = &gcc_mem_noc_q6_axi_clk.clkr,
-	[GCC_MEM_NOC_TS_CLK] = &gcc_mem_noc_ts_clk.clkr,
 	[GCC_NSS_TS_CLK] = &gcc_nss_ts_clk.clkr,
 	[GCC_NSS_TS_CLK_SRC] = &gcc_nss_ts_clk_src.clkr,
 	[GCC_NSSCC_CLK] = &gcc_nsscc_clk.clkr,
@@ -3573,10 +3481,7 @@ static struct clk_regmap *gcc_ipq5332_clocks[] = {
 	[GCC_XO_DIV4_CLK] = &gcc_xo_div4_clk.clkr,
 	[GCC_IM_SLEEP_CLK] = &gcc_im_sleep_clk.clkr,
 	[GCC_NSSNOC_PCNOC_1_CLK] = &gcc_nssnoc_pcnoc_1_clk.clkr,
-	[GCC_MEM_NOC_AHB_CLK] = &gcc_mem_noc_ahb_clk.clkr,
-	[GCC_MEM_NOC_APSS_AXI_CLK] = &gcc_mem_noc_apss_axi_clk.clkr,
 	[GCC_SNOC_QOSGEN_EXTREF_DIV_CLK_SRC] = &gcc_snoc_qosgen_extref_div_clk_src.clkr,
-	[GCC_MEM_NOC_QOSGEN_EXTREF_CLK] = &gcc_mem_noc_qosgen_extref_clk.clkr,
 	[GCC_PCIE3X2_PIPE_CLK_SRC] = &gcc_pcie3x2_pipe_clk_src.clkr,
 	[GCC_PCIE3X1_0_PIPE_CLK_SRC] = &gcc_pcie3x1_0_pipe_clk_src.clkr,
 	[GCC_PCIE3X1_1_PIPE_CLK_SRC] = &gcc_pcie3x1_1_pipe_clk_src.clkr,
-- 
2.34.1


^ permalink raw reply	[flat|nested] 7+ messages in thread

* Re: [PATCH 1/2] clk: qcom: ipq5332: drop the mem noc clocks
  2023-07-10 10:28 ` [PATCH 1/2] clk: qcom: ipq5332: drop the mem noc clocks Kathiravan T
@ 2023-07-15 14:10   ` Konrad Dybcio
  2023-07-15 15:17     ` Kathiravan T
  0 siblings, 1 reply; 7+ messages in thread
From: Konrad Dybcio @ 2023-07-15 14:10 UTC (permalink / raw)
  To: Kathiravan T, Bjorn Andersson, Andy Gross, Michael Turquette,
	Stephen Boyd, linux-arm-msm, linux-clk, linux-kernel
  Cc: quic_srichara, quic_sjaganat, quic_anusha, quic_saahtoma

On 10.07.2023 12:28, Kathiravan T wrote:
> Due to the recent design changes, all the mem noc clocks will be
> configured by the bootloaders and it will be access protected by the TZ
> firmware. So drop these clocks from the GCC driver.
> 
> Signed-off-by: Kathiravan T <quic_kathirav@quicinc.com>
> ---
Are there any IPQ5332s outside Qualcomm labs that will presumably
never get that TZ update?

Konrad
>  drivers/clk/qcom/gcc-ipq5332.c | 95 ----------------------------------
>  1 file changed, 95 deletions(-)
> 
> diff --git a/drivers/clk/qcom/gcc-ipq5332.c b/drivers/clk/qcom/gcc-ipq5332.c
> index a75ab88ed14c..939925baa9eb 100644
> --- a/drivers/clk/qcom/gcc-ipq5332.c
> +++ b/drivers/clk/qcom/gcc-ipq5332.c
> @@ -1635,42 +1635,6 @@ static struct clk_branch gcc_mdio_slave_ahb_clk = {
>  	},
>  };
>  
> -static struct clk_branch gcc_mem_noc_q6_axi_clk = {
> -	.halt_reg = 0x19010,
> -	.halt_check = BRANCH_HALT,
> -	.clkr = {
> -		.enable_reg = 0x19010,
> -		.enable_mask = BIT(0),
> -		.hw.init = &(const struct clk_init_data) {
> -			.name = "gcc_mem_noc_q6_axi_clk",
> -			.parent_hws = (const struct clk_hw*[]) {
> -				&gcc_q6_axim_clk_src.clkr.hw,
> -			},
> -			.num_parents = 1,
> -			.flags = CLK_SET_RATE_PARENT,
> -			.ops = &clk_branch2_ops,
> -		},
> -	},
> -};
> -
> -static struct clk_branch gcc_mem_noc_ts_clk = {
> -	.halt_reg = 0x19028,
> -	.halt_check = BRANCH_HALT_VOTED,
> -	.clkr = {
> -		.enable_reg = 0x19028,
> -		.enable_mask = BIT(0),
> -		.hw.init = &(const struct clk_init_data) {
> -			.name = "gcc_mem_noc_ts_clk",
> -			.parent_hws = (const struct clk_hw*[]) {
> -				&gcc_qdss_tsctr_div8_clk_src.hw,
> -			},
> -			.num_parents = 1,
> -			.flags = CLK_SET_RATE_PARENT,
> -			.ops = &clk_branch2_ops,
> -		},
> -	},
> -};
> -
>  static struct clk_branch gcc_nss_ts_clk = {
>  	.halt_reg = 0x17018,
>  	.halt_check = BRANCH_HALT_VOTED,
> @@ -3339,42 +3303,6 @@ static struct clk_branch gcc_nssnoc_pcnoc_1_clk = {
>  	},
>  };
>  
> -static struct clk_branch gcc_mem_noc_ahb_clk = {
> -	.halt_reg = 0x1900c,
> -	.halt_check = BRANCH_HALT,
> -	.clkr = {
> -		.enable_reg = 0x1900c,
> -		.enable_mask = BIT(0),
> -		.hw.init = &(const struct clk_init_data) {
> -			.name = "gcc_mem_noc_ahb_clk",
> -			.parent_hws = (const struct clk_hw*[]) {
> -				&gcc_pcnoc_bfdcd_clk_src.clkr.hw,
> -			},
> -			.num_parents = 1,
> -			.flags = CLK_SET_RATE_PARENT,
> -			.ops = &clk_branch2_ops,
> -		},
> -	},
> -};
> -
> -static struct clk_branch gcc_mem_noc_apss_axi_clk = {
> -	.halt_reg = 0x1901c,
> -	.halt_check = BRANCH_HALT_VOTED,
> -	.clkr = {
> -		.enable_reg = 0xb004,
> -		.enable_mask = BIT(6),
> -		.hw.init = &(const struct clk_init_data) {
> -			.name = "gcc_mem_noc_apss_axi_clk",
> -			.parent_hws = (const struct clk_hw*[]) {
> -				&gcc_apss_axi_clk_src.clkr.hw,
> -			},
> -			.num_parents = 1,
> -			.flags = CLK_SET_RATE_PARENT,
> -			.ops = &clk_branch2_ops,
> -		},
> -	},
> -};
> -
>  static struct clk_regmap_div gcc_snoc_qosgen_extref_div_clk_src = {
>  	.reg = 0x2e010,
>  	.shift = 0,
> @@ -3390,24 +3318,6 @@ static struct clk_regmap_div gcc_snoc_qosgen_extref_div_clk_src = {
>  	},
>  };
>  
> -static struct clk_branch gcc_mem_noc_qosgen_extref_clk = {
> -	.halt_reg = 0x19024,
> -	.halt_check = BRANCH_HALT,
> -	.clkr = {
> -		.enable_reg = 0x19024,
> -		.enable_mask = BIT(0),
> -		.hw.init = &(const struct clk_init_data) {
> -			.name = "gcc_mem_noc_qosgen_extref_clk",
> -			.parent_hws = (const struct clk_hw*[]) {
> -				&gcc_snoc_qosgen_extref_div_clk_src.clkr.hw,
> -			},
> -			.num_parents = 1,
> -			.flags = CLK_SET_RATE_PARENT,
> -			.ops = &clk_branch2_ops,
> -		},
> -	},
> -};
> -
>  static struct clk_regmap *gcc_ipq5332_clocks[] = {
>  	[GPLL0_MAIN] = &gpll0_main.clkr,
>  	[GPLL0] = &gpll0.clkr,
> @@ -3451,8 +3361,6 @@ static struct clk_regmap *gcc_ipq5332_clocks[] = {
>  	[GCC_LPASS_SWAY_CLK_SRC] = &gcc_lpass_sway_clk_src.clkr,
>  	[GCC_MDIO_AHB_CLK] = &gcc_mdio_ahb_clk.clkr,
>  	[GCC_MDIO_SLAVE_AHB_CLK] = &gcc_mdio_slave_ahb_clk.clkr,
> -	[GCC_MEM_NOC_Q6_AXI_CLK] = &gcc_mem_noc_q6_axi_clk.clkr,
> -	[GCC_MEM_NOC_TS_CLK] = &gcc_mem_noc_ts_clk.clkr,
>  	[GCC_NSS_TS_CLK] = &gcc_nss_ts_clk.clkr,
>  	[GCC_NSS_TS_CLK_SRC] = &gcc_nss_ts_clk_src.clkr,
>  	[GCC_NSSCC_CLK] = &gcc_nsscc_clk.clkr,
> @@ -3573,10 +3481,7 @@ static struct clk_regmap *gcc_ipq5332_clocks[] = {
>  	[GCC_XO_DIV4_CLK] = &gcc_xo_div4_clk.clkr,
>  	[GCC_IM_SLEEP_CLK] = &gcc_im_sleep_clk.clkr,
>  	[GCC_NSSNOC_PCNOC_1_CLK] = &gcc_nssnoc_pcnoc_1_clk.clkr,
> -	[GCC_MEM_NOC_AHB_CLK] = &gcc_mem_noc_ahb_clk.clkr,
> -	[GCC_MEM_NOC_APSS_AXI_CLK] = &gcc_mem_noc_apss_axi_clk.clkr,
>  	[GCC_SNOC_QOSGEN_EXTREF_DIV_CLK_SRC] = &gcc_snoc_qosgen_extref_div_clk_src.clkr,
> -	[GCC_MEM_NOC_QOSGEN_EXTREF_CLK] = &gcc_mem_noc_qosgen_extref_clk.clkr,
>  	[GCC_PCIE3X2_PIPE_CLK_SRC] = &gcc_pcie3x2_pipe_clk_src.clkr,
>  	[GCC_PCIE3X1_0_PIPE_CLK_SRC] = &gcc_pcie3x1_0_pipe_clk_src.clkr,
>  	[GCC_PCIE3X1_1_PIPE_CLK_SRC] = &gcc_pcie3x1_1_pipe_clk_src.clkr,

^ permalink raw reply	[flat|nested] 7+ messages in thread

* Re: [PATCH 1/2] clk: qcom: ipq5332: drop the mem noc clocks
  2023-07-15 14:10   ` Konrad Dybcio
@ 2023-07-15 15:17     ` Kathiravan T
  0 siblings, 0 replies; 7+ messages in thread
From: Kathiravan T @ 2023-07-15 15:17 UTC (permalink / raw)
  To: Konrad Dybcio, Bjorn Andersson, Andy Gross, Michael Turquette,
	Stephen Boyd, linux-arm-msm, linux-clk, linux-kernel
  Cc: quic_srichara, quic_sjaganat, quic_anusha, quic_saahtoma


On 7/15/2023 7:40 PM, Konrad Dybcio wrote:
> On 10.07.2023 12:28, Kathiravan T wrote:
>> Due to the recent design changes, all the mem noc clocks will be
>> configured by the bootloaders and it will be access protected by the TZ
>> firmware. So drop these clocks from the GCC driver.
>>
>> Signed-off-by: Kathiravan T <quic_kathirav@quicinc.com>
>> ---
> Are there any IPQ5332s outside Qualcomm labs that will presumably
> never get that TZ update?
>
> Konrad

No, this TZ update will shipped as part of the next releases.

Thanks, Kathiravan T.



^ permalink raw reply	[flat|nested] 7+ messages in thread

* [PATCH 2/2] clk: qcom: ipq5332: drop the gcc_apss_axi_clk_src clock
  2023-07-10 10:28 [PATCH 0/2] Drop the mem noc clocks from the IPQ5332 GCC driver Kathiravan T
  2023-07-10 10:28 ` [PATCH 1/2] clk: qcom: ipq5332: drop the mem noc clocks Kathiravan T
@ 2023-07-10 10:28 ` Kathiravan T
  2023-07-31  5:25 ` [PATCH 0/2] Drop the mem noc clocks from the IPQ5332 GCC driver Kathiravan T
  2023-08-14  3:27 ` Bjorn Andersson
  3 siblings, 0 replies; 7+ messages in thread
From: Kathiravan T @ 2023-07-10 10:28 UTC (permalink / raw)
  To: Bjorn Andersson, Andy Gross, Konrad Dybcio, Michael Turquette,
	Stephen Boyd, linux-arm-msm, linux-clk, linux-kernel
  Cc: quic_srichara, quic_sjaganat, quic_anusha, quic_saahtoma, Kathiravan T

With the removal of the mem noc clocks in the commit e224dc703521 ("clk:
qcom: gcc-ipq5332: drop the mem noc clocks"), we can drop the
gcc_apss_axi_clk_src clock as well, since there are no clocks uses this
clock as a parent.

Signed-off-by: Kathiravan T <quic_kathirav@quicinc.com>
---
 drivers/clk/qcom/gcc-ipq5332.c | 111 ++++++++++++---------------------
 1 file changed, 39 insertions(+), 72 deletions(-)

diff --git a/drivers/clk/qcom/gcc-ipq5332.c b/drivers/clk/qcom/gcc-ipq5332.c
index 939925baa9eb..40d8e8d5956f 100644
--- a/drivers/clk/qcom/gcc-ipq5332.c
+++ b/drivers/clk/qcom/gcc-ipq5332.c
@@ -224,38 +224,20 @@ static const struct clk_parent_data gcc_parent_data_4[] = {
 };
 
 static const struct parent_map gcc_parent_map_5[] = {
-	{ P_XO, 0 },
-	{ P_GPLL0_OUT_MAIN, 1 },
-	{ P_GPLL2_OUT_AUX, 2 },
-	{ P_GPLL4_OUT_AUX, 3 },
-	{ P_GCC_GPLL0_OUT_MAIN_DIV_CLK_SRC, 4 },
-	{ P_GPLL0_OUT_AUX, 5 },
-};
-
-static const struct clk_parent_data gcc_parent_data_5[] = {
-	{ .index = DT_XO },
-	{ .hw = &gpll0.clkr.hw },
-	{ .hw = &gpll2.clkr.hw },
-	{ .hw = &gpll4.clkr.hw },
-	{ .hw = &gpll0_div2.hw },
-	{ .hw = &gpll0.clkr.hw },
-};
-
-static const struct parent_map gcc_parent_map_6[] = {
 	{ P_XO, 0 },
 	{ P_GPLL0_OUT_MAIN, 1 },
 	{ P_GPLL0_OUT_AUX, 2 },
 	{ P_SLEEP_CLK, 6 },
 };
 
-static const struct clk_parent_data gcc_parent_data_6[] = {
+static const struct clk_parent_data gcc_parent_data_5[] = {
 	{ .index = DT_XO },
 	{ .hw = &gpll0.clkr.hw },
 	{ .hw = &gpll0.clkr.hw },
 	{ .index = DT_SLEEP_CLK },
 };
 
-static const struct parent_map gcc_parent_map_7[] = {
+static const struct parent_map gcc_parent_map_6[] = {
 	{ P_XO, 0 },
 	{ P_GPLL0_OUT_MAIN, 1 },
 	{ P_GPLL2_OUT_AUX, 2 },
@@ -263,7 +245,7 @@ static const struct parent_map gcc_parent_map_7[] = {
 	{ P_SLEEP_CLK, 6 },
 };
 
-static const struct clk_parent_data gcc_parent_data_7[] = {
+static const struct clk_parent_data gcc_parent_data_6[] = {
 	{ .index = DT_XO },
 	{ .hw = &gpll0.clkr.hw },
 	{ .hw = &gpll2.clkr.hw },
@@ -271,74 +253,74 @@ static const struct clk_parent_data gcc_parent_data_7[] = {
 	{ .index = DT_SLEEP_CLK },
 };
 
-static const struct parent_map gcc_parent_map_8[] = {
+static const struct parent_map gcc_parent_map_7[] = {
 	{ P_XO, 0 },
 	{ P_GPLL0_OUT_MAIN, 1 },
 	{ P_GPLL2_OUT_AUX, 2 },
 };
 
-static const struct clk_parent_data gcc_parent_data_8[] = {
+static const struct clk_parent_data gcc_parent_data_7[] = {
 	{ .index = DT_XO },
 	{ .hw = &gpll0.clkr.hw },
 	{ .hw = &gpll2.clkr.hw },
 };
 
-static const struct parent_map gcc_parent_map_9[] = {
+static const struct parent_map gcc_parent_map_8[] = {
 	{ P_XO, 0 },
 	{ P_GPLL0_OUT_MAIN, 1 },
 	{ P_GPLL2_OUT_MAIN, 2 },
 	{ P_GCC_GPLL0_OUT_MAIN_DIV_CLK_SRC, 4 },
 };
 
-static const struct clk_parent_data gcc_parent_data_9[] = {
+static const struct clk_parent_data gcc_parent_data_8[] = {
 	{ .index = DT_XO },
 	{ .hw = &gpll0.clkr.hw },
 	{ .hw = &gpll2.clkr.hw },
 	{ .hw = &gpll0_div2.hw },
 };
 
-static const struct parent_map gcc_parent_map_10[] = {
+static const struct parent_map gcc_parent_map_9[] = {
 	{ P_SLEEP_CLK, 6 },
 };
 
-static const struct clk_parent_data gcc_parent_data_10[] = {
+static const struct clk_parent_data gcc_parent_data_9[] = {
 	{ .index = DT_SLEEP_CLK },
 };
 
-static const struct parent_map gcc_parent_map_11[] = {
+static const struct parent_map gcc_parent_map_10[] = {
 	{ P_XO, 0 },
 	{ P_GPLL0_OUT_MAIN, 1 },
 	{ P_GPLL4_OUT_MAIN, 2 },
 	{ P_GCC_GPLL0_OUT_MAIN_DIV_CLK_SRC, 3 },
 };
 
-static const struct clk_parent_data gcc_parent_data_11[] = {
+static const struct clk_parent_data gcc_parent_data_10[] = {
 	{ .index = DT_XO },
 	{ .hw = &gpll0.clkr.hw },
 	{ .hw = &gpll4.clkr.hw },
 	{ .hw = &gpll0_div2.hw },
 };
 
-static const struct parent_map gcc_parent_map_12[] = {
+static const struct parent_map gcc_parent_map_11[] = {
 	{ P_XO, 0 },
 	{ P_GPLL0_OUT_AUX, 2 },
 	{ P_SLEEP_CLK, 6 },
 };
 
-static const struct clk_parent_data gcc_parent_data_12[] = {
+static const struct clk_parent_data gcc_parent_data_11[] = {
 	{ .index = DT_XO },
 	{ .hw = &gpll0.clkr.hw },
 	{ .index = DT_SLEEP_CLK },
 };
 
-static const struct parent_map gcc_parent_map_13[] = {
+static const struct parent_map gcc_parent_map_12[] = {
 	{ P_XO, 0 },
 	{ P_GPLL4_OUT_AUX, 1 },
 	{ P_GPLL0_OUT_MAIN, 3 },
 	{ P_GCC_GPLL0_OUT_MAIN_DIV_CLK_SRC, 4 },
 };
 
-static const struct clk_parent_data gcc_parent_data_13[] = {
+static const struct clk_parent_data gcc_parent_data_12[] = {
 	{ .index = DT_XO },
 	{ .hw = &gpll4.clkr.hw },
 	{ .hw = &gpll0.clkr.hw },
@@ -371,20 +353,6 @@ static const struct freq_tbl ftbl_gcc_apss_axi_clk_src[] = {
 	{ }
 };
 
-static struct clk_rcg2 gcc_apss_axi_clk_src = {
-	.cmd_rcgr = 0x24004,
-	.mnd_width = 0,
-	.hid_width = 5,
-	.parent_map = gcc_parent_map_5,
-	.freq_tbl = ftbl_gcc_apss_axi_clk_src,
-	.clkr.hw.init = &(const struct clk_init_data) {
-		.name = "gcc_apss_axi_clk_src",
-		.parent_data = gcc_parent_data_5,
-		.num_parents = ARRAY_SIZE(gcc_parent_data_5),
-		.ops = &clk_rcg2_ops,
-	},
-};
-
 static const struct freq_tbl ftbl_gcc_blsp1_qup1_spi_apps_clk_src[] = {
 	F(960000, P_XO, 1, 1, 25),
 	F(4800000, P_XO, 5, 0, 0),
@@ -733,12 +701,12 @@ static struct clk_rcg2 gcc_pcie_aux_clk_src = {
 	.cmd_rcgr = 0x28004,
 	.mnd_width = 16,
 	.hid_width = 5,
-	.parent_map = gcc_parent_map_6,
+	.parent_map = gcc_parent_map_5,
 	.freq_tbl = ftbl_gcc_pcie_aux_clk_src,
 	.clkr.hw.init = &(const struct clk_init_data) {
 		.name = "gcc_pcie_aux_clk_src",
-		.parent_data = gcc_parent_data_6,
-		.num_parents = ARRAY_SIZE(gcc_parent_data_6),
+		.parent_data = gcc_parent_data_5,
+		.num_parents = ARRAY_SIZE(gcc_parent_data_5),
 		.ops = &clk_rcg2_ops,
 	},
 };
@@ -810,12 +778,12 @@ static struct clk_rcg2 gcc_q6_axim_clk_src = {
 	.cmd_rcgr = 0x25004,
 	.mnd_width = 0,
 	.hid_width = 5,
-	.parent_map = gcc_parent_map_7,
+	.parent_map = gcc_parent_map_6,
 	.freq_tbl = ftbl_gcc_apss_axi_clk_src,
 	.clkr.hw.init = &(const struct clk_init_data) {
 		.name = "gcc_q6_axim_clk_src",
-		.parent_data = gcc_parent_data_7,
-		.num_parents = ARRAY_SIZE(gcc_parent_data_7),
+		.parent_data = gcc_parent_data_6,
+		.num_parents = ARRAY_SIZE(gcc_parent_data_6),
 		.ops = &clk_rcg2_ops,
 	},
 };
@@ -931,12 +899,12 @@ static struct clk_rcg2 gcc_qpic_io_macro_clk_src = {
 	.cmd_rcgr = 0x32004,
 	.mnd_width = 0,
 	.hid_width = 5,
-	.parent_map = gcc_parent_map_8,
+	.parent_map = gcc_parent_map_7,
 	.freq_tbl = ftbl_gcc_qpic_io_macro_clk_src,
 	.clkr.hw.init = &(const struct clk_init_data) {
 		.name = "gcc_qpic_io_macro_clk_src",
-		.parent_data = gcc_parent_data_8,
-		.num_parents = ARRAY_SIZE(gcc_parent_data_8),
+		.parent_data = gcc_parent_data_7,
+		.num_parents = ARRAY_SIZE(gcc_parent_data_7),
 		.ops = &clk_rcg2_ops,
 	},
 };
@@ -957,12 +925,12 @@ static struct clk_rcg2 gcc_sdcc1_apps_clk_src = {
 	.cmd_rcgr = 0x33004,
 	.mnd_width = 8,
 	.hid_width = 5,
-	.parent_map = gcc_parent_map_9,
+	.parent_map = gcc_parent_map_8,
 	.freq_tbl = ftbl_gcc_sdcc1_apps_clk_src,
 	.clkr.hw.init = &(const struct clk_init_data) {
 		.name = "gcc_sdcc1_apps_clk_src",
-		.parent_data = gcc_parent_data_9,
-		.num_parents = ARRAY_SIZE(gcc_parent_data_9),
+		.parent_data = gcc_parent_data_8,
+		.num_parents = ARRAY_SIZE(gcc_parent_data_8),
 		.ops = &clk_rcg2_floor_ops,
 	},
 };
@@ -976,12 +944,12 @@ static struct clk_rcg2 gcc_sleep_clk_src = {
 	.cmd_rcgr = 0x3400c,
 	.mnd_width = 0,
 	.hid_width = 5,
-	.parent_map = gcc_parent_map_10,
+	.parent_map = gcc_parent_map_9,
 	.freq_tbl = ftbl_gcc_sleep_clk_src,
 	.clkr.hw.init = &(const struct clk_init_data) {
 		.name = "gcc_sleep_clk_src",
-		.parent_data = gcc_parent_data_10,
-		.num_parents = ARRAY_SIZE(gcc_parent_data_10),
+		.parent_data = gcc_parent_data_9,
+		.num_parents = ARRAY_SIZE(gcc_parent_data_9),
 		.ops = &clk_rcg2_ops,
 	},
 };
@@ -998,12 +966,12 @@ static struct clk_rcg2 gcc_system_noc_bfdcd_clk_src = {
 	.cmd_rcgr = 0x2e004,
 	.mnd_width = 0,
 	.hid_width = 5,
-	.parent_map = gcc_parent_map_11,
+	.parent_map = gcc_parent_map_10,
 	.freq_tbl = ftbl_gcc_system_noc_bfdcd_clk_src,
 	.clkr.hw.init = &(const struct clk_init_data) {
 		.name = "gcc_system_noc_bfdcd_clk_src",
-		.parent_data = gcc_parent_data_11,
-		.num_parents = ARRAY_SIZE(gcc_parent_data_11),
+		.parent_data = gcc_parent_data_10,
+		.num_parents = ARRAY_SIZE(gcc_parent_data_10),
 		.ops = &clk_rcg2_ops,
 	},
 };
@@ -1039,12 +1007,12 @@ static struct clk_rcg2 gcc_usb0_aux_clk_src = {
 	.cmd_rcgr = 0x2c018,
 	.mnd_width = 16,
 	.hid_width = 5,
-	.parent_map = gcc_parent_map_12,
+	.parent_map = gcc_parent_map_11,
 	.freq_tbl = ftbl_gcc_pcie_aux_clk_src,
 	.clkr.hw.init = &(const struct clk_init_data) {
 		.name = "gcc_usb0_aux_clk_src",
-		.parent_data = gcc_parent_data_12,
-		.num_parents = ARRAY_SIZE(gcc_parent_data_12),
+		.parent_data = gcc_parent_data_11,
+		.num_parents = ARRAY_SIZE(gcc_parent_data_11),
 		.ops = &clk_rcg2_ops,
 	},
 };
@@ -1091,12 +1059,12 @@ static struct clk_rcg2 gcc_usb0_mock_utmi_clk_src = {
 	.cmd_rcgr = 0x2c02c,
 	.mnd_width = 8,
 	.hid_width = 5,
-	.parent_map = gcc_parent_map_13,
+	.parent_map = gcc_parent_map_12,
 	.freq_tbl = ftbl_gcc_usb0_mock_utmi_clk_src,
 	.clkr.hw.init = &(const struct clk_init_data) {
 		.name = "gcc_usb0_mock_utmi_clk_src",
-		.parent_data = gcc_parent_data_13,
-		.num_parents = ARRAY_SIZE(gcc_parent_data_13),
+		.parent_data = gcc_parent_data_12,
+		.num_parents = ARRAY_SIZE(gcc_parent_data_12),
 		.ops = &clk_rcg2_ops,
 	},
 };
@@ -3328,7 +3296,6 @@ static struct clk_regmap *gcc_ipq5332_clocks[] = {
 	[GCC_ADSS_PWM_CLK] = &gcc_adss_pwm_clk.clkr,
 	[GCC_ADSS_PWM_CLK_SRC] = &gcc_adss_pwm_clk_src.clkr,
 	[GCC_AHB_CLK] = &gcc_ahb_clk.clkr,
-	[GCC_APSS_AXI_CLK_SRC] = &gcc_apss_axi_clk_src.clkr,
 	[GCC_BLSP1_AHB_CLK] = &gcc_blsp1_ahb_clk.clkr,
 	[GCC_BLSP1_QUP1_I2C_APPS_CLK] = &gcc_blsp1_qup1_i2c_apps_clk.clkr,
 	[GCC_BLSP1_QUP1_SPI_APPS_CLK] = &gcc_blsp1_qup1_spi_apps_clk.clkr,
-- 
2.34.1


^ permalink raw reply	[flat|nested] 7+ messages in thread

* Re: [PATCH 0/2] Drop the mem noc clocks from the IPQ5332 GCC driver
  2023-07-10 10:28 [PATCH 0/2] Drop the mem noc clocks from the IPQ5332 GCC driver Kathiravan T
  2023-07-10 10:28 ` [PATCH 1/2] clk: qcom: ipq5332: drop the mem noc clocks Kathiravan T
  2023-07-10 10:28 ` [PATCH 2/2] clk: qcom: ipq5332: drop the gcc_apss_axi_clk_src clock Kathiravan T
@ 2023-07-31  5:25 ` Kathiravan T
  2023-08-14  3:27 ` Bjorn Andersson
  3 siblings, 0 replies; 7+ messages in thread
From: Kathiravan T @ 2023-07-31  5:25 UTC (permalink / raw)
  To: Bjorn Andersson, Andy Gross, Konrad Dybcio, Michael Turquette,
	Stephen Boyd, linux-arm-msm, linux-clk, linux-kernel
  Cc: quic_srichara, quic_sjaganat, quic_anusha, quic_saahtoma


On 7/10/2023 3:58 PM, Kathiravan T wrote:
> Due to the recent design changes, all the mem noc clocks will be
> configured by the bootloaders and it will be access protected by the TZ
> firmware. Also there are no comsumers for these clocks in the kernel. So
> drop these clocks from the GCC driver.
>
> With these clocks removal, remove the gcc_apss_axi_clk_src clock as well
> since no clocks uses this as a parent.


Gentle Reminder...


>
> Kathiravan T (2):
>    clk: qcom: ipq5332: drop the mem noc clocks
>    clk: qcom: ipq5332: drop the gcc_apss_axi_clk_src clock
>
>   drivers/clk/qcom/gcc-ipq5332.c | 206 +++++++--------------------------
>   1 file changed, 39 insertions(+), 167 deletions(-)
>

^ permalink raw reply	[flat|nested] 7+ messages in thread

* Re: [PATCH 0/2] Drop the mem noc clocks from the IPQ5332 GCC driver
  2023-07-10 10:28 [PATCH 0/2] Drop the mem noc clocks from the IPQ5332 GCC driver Kathiravan T
                   ` (2 preceding siblings ...)
  2023-07-31  5:25 ` [PATCH 0/2] Drop the mem noc clocks from the IPQ5332 GCC driver Kathiravan T
@ 2023-08-14  3:27 ` Bjorn Andersson
  3 siblings, 0 replies; 7+ messages in thread
From: Bjorn Andersson @ 2023-08-14  3:27 UTC (permalink / raw)
  To: Andy Gross, Konrad Dybcio, Michael Turquette, Stephen Boyd,
	linux-arm-msm, linux-clk, linux-kernel, Kathiravan T
  Cc: quic_srichara, quic_sjaganat, quic_anusha, quic_saahtoma


On Mon, 10 Jul 2023 15:58:05 +0530, Kathiravan T wrote:
> Due to the recent design changes, all the mem noc clocks will be
> configured by the bootloaders and it will be access protected by the TZ
> firmware. Also there are no comsumers for these clocks in the kernel. So
> drop these clocks from the GCC driver.
> 
> With these clocks removal, remove the gcc_apss_axi_clk_src clock as well
> since no clocks uses this as a parent.
> 
> [...]

Applied, thanks!

[1/2] clk: qcom: ipq5332: drop the mem noc clocks
      commit: 1784d031ef1f329bd362343a8fe1c083116160af
[2/2] clk: qcom: ipq5332: drop the gcc_apss_axi_clk_src clock
      commit: 90d5c043dda7901065e9da4b23967903640fd2ea

Best regards,
-- 
Bjorn Andersson <andersson@kernel.org>

^ permalink raw reply	[flat|nested] 7+ messages in thread

end of thread, other threads:[~2023-08-14  3:25 UTC | newest]

Thread overview: 7+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2023-07-10 10:28 [PATCH 0/2] Drop the mem noc clocks from the IPQ5332 GCC driver Kathiravan T
2023-07-10 10:28 ` [PATCH 1/2] clk: qcom: ipq5332: drop the mem noc clocks Kathiravan T
2023-07-15 14:10   ` Konrad Dybcio
2023-07-15 15:17     ` Kathiravan T
2023-07-10 10:28 ` [PATCH 2/2] clk: qcom: ipq5332: drop the gcc_apss_axi_clk_src clock Kathiravan T
2023-07-31  5:25 ` [PATCH 0/2] Drop the mem noc clocks from the IPQ5332 GCC driver Kathiravan T
2023-08-14  3:27 ` Bjorn Andersson

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