Re: [PATCH v2 07/14] arm64: head: Force little-endian early during boot

["Ard Biesheuvel" <ardb@kernel.org>]

Hi Will,

On Mon, 7 Sep 2026, at 18:37, Will Deacon wrote:
> Commit 2ced0f30a426 ("arm64: head: Switch endianness before populating
> the ID map") configured SCTLR_ELx.EE at boot according to the endianness
> of the kernel in case the bootloader had entered the image in the wrong
> endianness. Additionally, if the MMU was enabled in such a case, logic
> was added to turn it back off to prevent the hardware walker from
> misinterpreting the idmap page-table.
>
> Given that the MMU is only expected to be enabled when booting EFI, EFI
> only supports little-endian and arm64 kernels cannot be built as
> big-endian images, we can rip out this handling and simply force
> SCTLR_ELx.EE to 0 (little-endian).
>
> Suggested-by: Ard Biesheuvel <ardb@kernel.org>
> Signed-off-by: Will Deacon <will@kernel.org>
> ---
>  arch/arm64/kernel/head.S | 20 +-------------------
>  1 file changed, 1 insertion(+), 19 deletions(-)
>
> diff --git a/arch/arm64/kernel/head.S b/arch/arm64/kernel/head.S
> index 8951ce693552..d5c1ea0c5b3c 100644
> --- a/arch/arm64/kernel/head.S
> +++ b/arch/arm64/kernel/head.S
> @@ -138,29 +138,11 @@ SYM_CODE_START_LOCAL(record_mmu_state)
>  	b.ne	0f
>  	mrs	x19, sctlr_el2
>  0:
> -	tbnz	x19, #SCTLR_ELx_EE_SHIFT, 1f
> +	bic	x19, x19, #SCTLR_ELx_EE		// Force little-endian

This bic has no effect here: the 'and' below clears it anyway, but x19
is not written back to SCTLR.

When I suggested this, I missed that SCTLR.EE still needs to be cleared
before populating the ID map, regardless of whether we enter with the
MMU and caches enabled.

IOW, we need to retain the SCTLR writeback logic below. The only thing
we can drop is the clearing of the M bit and the invocations of
pre_disable_mmu_workaround. But we might as well keep that.

Apologies for the bad suggestion.



>  	tst	x19, #SCTLR_ELx_C		// Z := (C == 0)
>  	and	x19, x19, #SCTLR_ELx_M		// isolate M bit
>  	csel	x19, xzr, x19, eq		// clear x19 if Z
>  	ret
> -
> -	/*
> -	 * Set the correct endianness early so all memory accesses issued
> -	 * before init_kernel_el() occur in the correct byte order. Note that
> -	 * this means the MMU must be disabled, or the active ID map will end
> -	 * up getting interpreted with the wrong byte order.
> -	 */
> -1:	eor	x19, x19, #SCTLR_ELx_EE
> -	bic	x19, x19, #SCTLR_ELx_M
> -	b.ne	2f
> -	pre_disable_mmu_workaround
> -	msr	sctlr_el2, x19
> -	b	3f
> -2:	pre_disable_mmu_workaround
> -	msr	sctlr_el1, x19
> -3:	isb
> -	mov	x19, xzr
> -	ret
>  SYM_CODE_END(record_mmu_state)
> 
>  /*
> -- 
> 2.55.0.979.g7e5102b832-goog