From: David Woodhouse <dwmw2@infradead.org>
To: "Ahmed S. Darwish" <darwi@linutronix.de>,
Borislav Petkov <bp@alien8.de>, Ingo Molnar <mingo@redhat.com>,
Dave Hansen <dave.hansen@linux.intel.com>
Cc: Thomas Gleixner <tglx@linutronix.de>,
Andrew Cooper <andrew.cooper3@citrix.com>,
"H. Peter Anvin" <hpa@zytor.com>,
Sean Christopherson <seanjc@google.com>,
Peter Zijlstra <peterz@infradead.org>,
Sohil Mehta <sohil.mehta@intel.com>,
John Ogness <john.ogness@linutronix.de>,
x86@kernel.org, x86-cpuid@lists.linux.dev,
LKML <linux-kernel@vger.kernel.org>
Subject: Re: [PATCH v4 00/34] x86: Introduce a centralized CPUID data model
Date: Sat, 16 Aug 2025 10:59:43 +0100 [thread overview]
Message-ID: <ebab779b93b8be44bd5089ae6ecc9746b1517a68.camel@infradead.org> (raw)
In-Reply-To: <20250815070227.19981-1-darwi@linutronix.de>
[-- Attachment #1: Type: text/plain, Size: 1157 bytes --]
On Fri, 2025-08-15 at 09:01 +0200, Ahmed S. Darwish wrote:
>
> This series introduces a centralized CPUID model for the x86
> subsystem.
>
> Rationale for this work can be found at:
>
> https://lore.kernel.org/lkml/874ixernra.ffs@tglx
>
> https://gitlab.com/x86-cpuid.org/x86-cpuid-db
>
> The first 5 patches can be independently applied.
Nice work. Looks like you haven't attempted to address hypervisor CPUID
yet. I've attempted to document that in a section at the end of
http://david.woodhou.se/ExtDestId.pdf — I wonder if we should find
somewhere to publish it as canonical?
I suspect our loop in cpuid_base_hypervisor() should be 'fixed' to
comply with the new rule I just made up, that it should only scan each
block at 0x4000_0.00 until it finds an empty block, rather than going
all the way up to 0x4001_0000?
Are there any hypervisors which provide more than one block, that
*aren't* just putting the Hyper-V leaves at 0x4000_0000 and their own
native leaves at 0x4000_0100 ?
Even when we support Xen under KVM we expose *only* the Xen leaves and
don't put the KVM leaves at 0x4000_0100 too.
[-- Attachment #2: smime.p7s --]
[-- Type: application/pkcs7-signature, Size: 5069 bytes --]
next prev parent reply other threads:[~2025-08-16 10:00 UTC|newest]
Thread overview: 55+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-08-15 7:01 Ahmed S. Darwish
2025-08-15 7:01 ` [PATCH v4 01/34] x86/cpuid: Remove transitional <asm/cpuid.h> header Ahmed S. Darwish
2025-08-15 10:11 ` [tip: x86/urgent] " tip-bot2 for Ahmed S. Darwish
2025-08-15 15:22 ` tip-bot2 for Ahmed S. Darwish
2025-08-15 7:01 ` [PATCH v4 02/34] ASoC: Intel: avs: Include CPUID header at file scope Ahmed S. Darwish
2025-08-18 14:56 ` Borislav Petkov
2025-08-18 15:14 ` Ahmed S. Darwish
2025-08-15 7:01 ` [PATCH v4 03/34] treewide: Explicitly include the x86 CPUID headers Ahmed S. Darwish
2025-08-15 7:01 ` [PATCH v4 04/34] x86/cpu: <asm/processor.h>: Do not include the CPUID API header Ahmed S. Darwish
2025-08-15 7:01 ` [PATCH v4 05/34] x86/cpuid: Rename cpuid_leaf()/cpuid_subleaf() APIs Ahmed S. Darwish
2025-08-15 7:01 ` [PATCH v4 06/34] x86/cpuid: Introduce <asm/cpuid/leaf_types.h> Ahmed S. Darwish
2025-08-25 14:18 ` Borislav Petkov
2025-08-25 14:56 ` Ahmed S. Darwish
2025-08-15 7:02 ` [PATCH v4 07/34] x86/cpuid: Introduce a centralized CPUID data model Ahmed S. Darwish
2025-08-15 15:34 ` Sean Christopherson
2025-08-18 13:49 ` Ahmed S. Darwish
2025-08-18 18:44 ` Sean Christopherson
2025-08-18 19:54 ` Ahmed S. Darwish
2025-08-18 21:29 ` Sean Christopherson
2025-08-19 13:10 ` Ahmed S. Darwish
2025-08-15 7:02 ` [PATCH v4 08/34] x86/cpuid: Introduce a centralized CPUID parser Ahmed S. Darwish
2025-08-15 7:02 ` [PATCH v4 09/34] x86/cpu: Use parsed CPUID(0x0) Ahmed S. Darwish
2025-08-15 7:02 ` [PATCH v4 10/34] x86/lib: Add CPUID(0x1) CPU family and model calculation Ahmed S. Darwish
2025-08-15 7:02 ` [PATCH v4 11/34] x86/cpu: Use parsed CPUID(0x1) Ahmed S. Darwish
2025-08-15 7:02 ` [PATCH v4 12/34] x86/cpuid: Parse CPUID(0x80000000) Ahmed S. Darwish
2025-08-15 7:02 ` [PATCH v4 13/34] x86/cpu: Use parsed CPUID(0x80000000) Ahmed S. Darwish
2025-08-15 7:02 ` [PATCH v4 14/34] x86/cpuid: Introduce a CPUID leaf x86 vendor table Ahmed S. Darwish
2025-08-15 7:02 ` [PATCH v4 15/34] x86/cpuid: Introduce CPUID parser debugfs interface Ahmed S. Darwish
2025-08-15 7:02 ` [PATCH v4 16/34] x86/cpuid: Parse CPUID(0x2) Ahmed S. Darwish
2025-08-15 7:02 ` [PATCH v4 17/34] x86/cpuid: Warn once on invalid CPUID(0x2) iteration count Ahmed S. Darwish
2025-08-15 7:02 ` [PATCH v4 18/34] x86/cpuid: Introduce parsed CPUID(0x2) API Ahmed S. Darwish
2025-08-15 7:02 ` [PATCH v4 19/34] x86/cpu: Use parsed CPUID(0x2) Ahmed S. Darwish
2025-08-15 7:02 ` [PATCH v4 20/34] x86/cacheinfo: " Ahmed S. Darwish
2025-08-15 7:02 ` [PATCH v4 21/34] x86/cpuid: Remove direct CPUID(0x2) query API Ahmed S. Darwish
2025-08-15 7:02 ` [PATCH v4 22/34] x86/cpuid: Parse 'deterministic cache parameters' CPUID leaves Ahmed S. Darwish
2025-08-15 7:02 ` [PATCH v4 23/34] x86/cacheinfo: Pass a 'struct cpuinfo_x86' refrence to CPUID(0x4) code Ahmed S. Darwish
2025-08-15 7:02 ` [PATCH v4 24/34] x86/cacheinfo: Use parsed CPUID(0x4) Ahmed S. Darwish
2025-08-15 7:02 ` [PATCH v4 25/34] x86/cacheinfo: Use parsed CPUID(0x8000001d) Ahmed S. Darwish
2025-08-15 7:02 ` [PATCH v4 26/34] x86/cpuid: Parse CPUID(0x80000005) and CPUID(0x80000006) Ahmed S. Darwish
2025-08-15 7:02 ` [PATCH v4 27/34] x86/cacheinfo: Use auto-generated data types Ahmed S. Darwish
2025-08-15 7:02 ` [PATCH v4 28/34] x86/cacheinfo: Use parsed CPUID(0x80000005) and CPUID(0x80000006) Ahmed S. Darwish
2025-08-15 15:25 ` Dave Hansen
2025-08-18 15:38 ` Ahmed S. Darwish
2025-08-18 15:52 ` David Woodhouse
2025-08-18 17:00 ` Ahmed S. Darwish
2025-08-15 7:02 ` [PATCH v4 29/34] x86/amd_nb: Trickle down 'struct cpuinfo_x86' reference Ahmed S. Darwish
2025-08-18 2:54 ` kernel test robot
2025-08-18 14:47 ` Ahmed S. Darwish
2025-08-15 7:02 ` [PATCH v4 30/34] x86/cpuid: Use parsed CPUID(0x80000006) Ahmed S. Darwish
2025-08-15 7:02 ` [PATCH v4 31/34] x86/cpu: Rescan CPUID table after PSN disable Ahmed S. Darwish
2025-08-15 7:02 ` [PATCH v4 32/34] x86/cpu: Rescan CPUID table after unlocking full CPUID range Ahmed S. Darwish
2025-08-15 7:02 ` [PATCH v4 33/34] x86/cpuid: Parse CPUID(0x16) Ahmed S. Darwish
2025-08-15 7:02 ` [PATCH v4 34/34] x86/tsc: Use parsed CPUID(0x16) Ahmed S. Darwish
2025-08-16 9:59 ` David Woodhouse [this message]
2025-08-18 16:37 ` [PATCH v4 00/34] x86: Introduce a centralized CPUID data model Ahmed S. Darwish
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=ebab779b93b8be44bd5089ae6ecc9746b1517a68.camel@infradead.org \
--to=dwmw2@infradead.org \
--cc=andrew.cooper3@citrix.com \
--cc=bp@alien8.de \
--cc=darwi@linutronix.de \
--cc=dave.hansen@linux.intel.com \
--cc=hpa@zytor.com \
--cc=john.ogness@linutronix.de \
--cc=linux-kernel@vger.kernel.org \
--cc=mingo@redhat.com \
--cc=peterz@infradead.org \
--cc=seanjc@google.com \
--cc=sohil.mehta@intel.com \
--cc=tglx@linutronix.de \
--cc=x86-cpuid@lists.linux.dev \
--cc=x86@kernel.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox
all inboxes | Powered by JetHome®