From: Krzysztof Kozlowski <krzk@kernel.org>
To: Khairul Anuar Romli <khairul.anuar.romli@altera.com>,
Dinh Nguyen <dinguyen@kernel.org>, Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>,
Mahesh Rao <mahesh.rao@altera.com>,
devicetree@vger.kernel.org,
open list <linux-kernel@vger.kernel.org>
Subject: Re: [PATCH 1/2] dt-bindings: firmware: Add Agilex5 SVC compatible string
Date: Tue, 28 Oct 2025 10:35:01 +0100 [thread overview]
Message-ID: <ec66c0b0-33c0-4036-ad33-c1faf9633e02@kernel.org> (raw)
In-Reply-To: <728e10b5100e3a41d2d4595f227d26df6bdbe205.1761643239.git.khairul.anuar.romli@altera.com>
On 28/10/2025 10:28, Khairul Anuar Romli wrote:
> Enable support for the Agilex5 in Stratix10 SoC service layer (SVC) by
> adding the new compatible string "intel,agilex5-svc" in the device tree
> bindings.
>
> This is needed to differentiate Agilex5 from previous SoC generations, as
> Agilex5 uses a different mechanism for mapping reserved memory regions,
> which rely on IOMMU support.
There are no iommus here, so this feels inaccurate.
Best regards,
Krzysztof
next prev parent reply other threads:[~2025-10-28 9:35 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
[not found] <cover.1761643239.git.khairul.anuar.romli@altera.com>
2025-10-28 9:28 ` Khairul Anuar Romli
2025-10-28 9:35 ` Krzysztof Kozlowski [this message]
2025-10-28 10:59 ` Romli, Khairul Anuar
2025-10-28 11:03 ` Krzysztof Kozlowski
2025-10-28 9:29 ` [PATCH 2/2] arm64: dts: intel: Add Agilex5 SVC node with memory region Khairul Anuar Romli
2025-10-28 9:36 ` Krzysztof Kozlowski
2025-10-28 11:01 ` Romli, Khairul Anuar
2025-11-01 11:06 ` kernel test robot
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