[PATCH 1/2] dt-bindings: firmware: Add Agilex5 SVC compatible string

[PATCH 1/2] dt-bindings: firmware: Add Agilex5 SVC compatible string

[Khairul Anuar Romli]

Enable support for the Agilex5 in Stratix10 SoC service layer (SVC) by
adding the new compatible string "intel,agilex5-svc" in the device tree
bindings.

This is needed to differentiate Agilex5 from previous SoC generations, as
Agilex5 uses a different mechanism for mapping reserved memory regions,
which rely on IOMMU support.

Signed-off-by: Khairul Anuar Romli <khairul.anuar.romli@altera.com>
---
 .../devicetree/bindings/firmware/intel,stratix10-svc.yaml        | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/firmware/intel,stratix10-svc.yaml b/Documentation/devicetree/bindings/firmware/intel,stratix10-svc.yaml
index fac1e955852e..90b4c00e3079 100644
--- a/Documentation/devicetree/bindings/firmware/intel,stratix10-svc.yaml
+++ b/Documentation/devicetree/bindings/firmware/intel,stratix10-svc.yaml
@@ -34,6 +34,7 @@ properties:
     enum:
       - intel,stratix10-svc
       - intel,agilex-svc
+      - intel,agilex5-svc
 
   method:
     description: |
-- 
2.43.7

[PATCH 2/2] arm64: dts: intel: Add Agilex5 SVC node with memory region

[Khairul Anuar Romli]

Introduce the Stratix10 SoC service layer (SVC) node for Agilex5 SoCs.
The node includes the compatible string "intel,agilex5-svc" and references
a reserved memory region required for communication with the Secure Device
Manager (SDM).

Agilex5 introduces a dependency on IOMMU-based translation for reserved
memory, unlike prior Agilex platforms. This commit introduces the
structural changes needed to support this feature once the IOMMU driver
is upstreamed.

Signed-off-by: Khairul Anuar Romli <khairul.anuar.romli@altera.com>
---
 arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi b/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi
index a13ccee3c4c3..15284092897e 100644
--- a/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi
+++ b/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi
@@ -841,5 +841,14 @@ queue7 {
 				};
 			};
 		};
+
+		firmware {
+			svc {
+				compatible = "intel,agilex5-svc";
+				method = "smc";
+				memory-region = <&service_reserved>;
+				iommus = <&smmu 10>;
+			};
+		};
 	};
 };
-- 
2.43.7

Re: [PATCH 1/2] dt-bindings: firmware: Add Agilex5 SVC compatible string

[Krzysztof Kozlowski]

On 28/10/2025 10:28, Khairul Anuar Romli wrote:
> Enable support for the Agilex5 in Stratix10 SoC service layer (SVC) by
> adding the new compatible string "intel,agilex5-svc" in the device tree
> bindings.
> 
> This is needed to differentiate Agilex5 from previous SoC generations, as
> Agilex5 uses a different mechanism for mapping reserved memory regions,
> which rely on IOMMU support.

There are no iommus here, so this feels inaccurate.

Best regards,
Krzysztof

Re: [PATCH 2/2] arm64: dts: intel: Add Agilex5 SVC node with memory region

[Krzysztof Kozlowski]

On 28/10/2025 10:29, Khairul Anuar Romli wrote:
> Introduce the Stratix10 SoC service layer (SVC) node for Agilex5 SoCs.
> The node includes the compatible string "intel,agilex5-svc" and references
> a reserved memory region required for communication with the Secure Device
> Manager (SDM).
> 
> Agilex5 introduces a dependency on IOMMU-based translation for reserved
> memory, unlike prior Agilex platforms. This commit introduces the
> structural changes needed to support this feature once the IOMMU driver
> is upstreamed.
> 
> Signed-off-by: Khairul Anuar Romli <khairul.anuar.romli@altera.com>
> ---
>  arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi | 9 +++++++++
>  1 file changed, 9 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi b/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi
> index a13ccee3c4c3..15284092897e 100644
> --- a/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi
> +++ b/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi
> @@ -841,5 +841,14 @@ queue7 {
>  				};
>  			};
>  		};
> +
> +		firmware {
> +			svc {
> +				compatible = "intel,agilex5-svc";
> +				method = "smc";
> +				memory-region = <&service_reserved>;
> +				iommus = <&smmu 10>;


You did not test your code.

Plus, where is the driver? Please read submitting patches in DT directory.

Best regards,
Krzysztof

Re: [PATCH 1/2] dt-bindings: firmware: Add Agilex5 SVC compatible string

[Romli, Khairul Anuar]

On 28/10/2025 5:35 pm, Krzysztof Kozlowski wrote:
> [You don't often get email from krzk@kernel.org. Learn why this is important at https://aka.ms/LearnAboutSenderIdentification ]
> 
> On 28/10/2025 10:28, Khairul Anuar Romli wrote:
>> Enable support for the Agilex5 in Stratix10 SoC service layer (SVC) by
>> adding the new compatible string "intel,agilex5-svc" in the device tree
>> bindings.
>>
>> This is needed to differentiate Agilex5 from previous SoC generations, as
>> Agilex5 uses a different mechanism for mapping reserved memory regions,
>> which rely on IOMMU support.
> 
> There are no iommus here, so this feels inaccurate.
> 
> Best regards,
> Krzysztof

I will remove this on the v2 revision as the iommu is part on future 
patch series.

Thanks
Khairul

Re: [PATCH 2/2] arm64: dts: intel: Add Agilex5 SVC node with memory region

[Romli, Khairul Anuar]

On 28/10/2025 5:36 pm, Krzysztof Kozlowski wrote:
> On 28/10/2025 10:29, Khairul Anuar Romli wrote:
>> Introduce the Stratix10 SoC service layer (SVC) node for Agilex5 SoCs.
>> The node includes the compatible string "intel,agilex5-svc" and references
>> a reserved memory region required for communication with the Secure Device
>> Manager (SDM).
>>
>> Agilex5 introduces a dependency on IOMMU-based translation for reserved
>> memory, unlike prior Agilex platforms. This commit introduces the
>> structural changes needed to support this feature once the IOMMU driver
>> is upstreamed.
>>
>> Signed-off-by: Khairul Anuar Romli <khairul.anuar.romli@altera.com>
>> ---
>>   arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi | 9 +++++++++
>>   1 file changed, 9 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi b/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi
>> index a13ccee3c4c3..15284092897e 100644
>> --- a/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi
>> +++ b/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi
>> @@ -841,5 +841,14 @@ queue7 {
>>   				};
>>   			};
>>   		};
>> +
>> +		firmware {
>> +			svc {
>> +				compatible = "intel,agilex5-svc";
>> +				method = "smc";
>> +				memory-region = <&service_reserved>;
>> +				iommus = <&smmu 10>;
> 
> 
> You did not test your code.
> 
> Plus, where is the driver? Please read submitting patches in DT directory.
> 
> Best regards,
> Krzysztof

I will add the driver implementation in the v2 as part of initial 
support enablement for this Agilex5.

Thanks

Best Regards,
Khairul

Re: [PATCH 1/2] dt-bindings: firmware: Add Agilex5 SVC compatible string

[Krzysztof Kozlowski]

On 28/10/2025 11:59, Romli, Khairul Anuar wrote:
> On 28/10/2025 5:35 pm, Krzysztof Kozlowski wrote:
>> [You don't often get email from krzk@kernel.org. Learn why this is important at https://aka.ms/LearnAboutSenderIdentification ]
>>
>> On 28/10/2025 10:28, Khairul Anuar Romli wrote:
>>> Enable support for the Agilex5 in Stratix10 SoC service layer (SVC) by
>>> adding the new compatible string "intel,agilex5-svc" in the device tree
>>> bindings.
>>>
>>> This is needed to differentiate Agilex5 from previous SoC generations, as
>>> Agilex5 uses a different mechanism for mapping reserved memory regions,
>>> which rely on IOMMU support.
>>
>> There are no iommus here, so this feels inaccurate.
>>
>> Best regards,
>> Krzysztof
> 
> I will remove this on the v2 revision as the iommu is part on future 
> patch series.
>

No, instead please post complete bindings for this device. So all of the
hardware properties. See writing bindings doc.

Best regards,
Krzysztof

Re: [PATCH 2/2] arm64: dts: intel: Add Agilex5 SVC node with memory region

[kernel test robot]

Hi Khairul,

kernel test robot noticed the following build errors:

[auto build test ERROR on robh/for-next]
[also build test ERROR on linus/master v6.18-rc3 next-20251031]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]

url:    https://github.com/intel-lab-lkp/linux/commits/Khairul-Anuar-Romli/arm64-dts-intel-Add-Agilex5-SVC-node-with-memory-region/20251028-183009
base:   https://git.kernel.org/pub/scm/linux/kernel/git/robh/linux.git for-next
patch link:    https://lore.kernel.org/r/a3182556c07839dcd9227fa6a4a9d295507f3e8e.1761643239.git.khairul.anuar.romli%40altera.com
patch subject: [PATCH 2/2] arm64: dts: intel: Add Agilex5 SVC node with memory region
config: arm64-randconfig-002-20251101 (https://download.01.org/0day-ci/archive/20251101/202511011821.wW4mmrec-lkp@intel.com/config)
compiler: clang version 22.0.0git (https://github.com/llvm/llvm-project cc271437553452ede002d871d32abc02084341a8)
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20251101/202511011821.wW4mmrec-lkp@intel.com/reproduce)

If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202511011821.wW4mmrec-lkp@intel.com/

All errors (new ones prefixed by >>):

>> ERROR: Input tree has errors, aborting (use -f to force output)

-- 
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki