From: Baolu Lu <baolu.lu@linux.intel.com>
To: "Tian, Kevin" <kevin.tian@intel.com>,
"iommu@lists.linux.dev" <iommu@lists.linux.dev>
Cc: baolu.lu@linux.intel.com, Joerg Roedel <joro@8bytes.org>,
Will Deacon <will@kernel.org>,
Robin Murphy <robin.murphy@arm.com>,
"Raj, Ashok" <ashok.raj@intel.com>,
"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>
Subject: Re: [PATCH 1/1] iommu/vt-d: Set No Execute Enable bit in PASID table entry
Date: Sat, 28 Jan 2023 15:42:41 +0800 [thread overview]
Message-ID: <ecef3c86-2f35-9f51-23c1-8e317c1afde6@linux.intel.com> (raw)
In-Reply-To: <BN9PR11MB5276D8D7CF2AD32D605EFD628CCD9@BN9PR11MB5276.namprd11.prod.outlook.com>
On 2023/1/28 15:19, Tian, Kevin wrote:
>> From: Lu Baolu<baolu.lu@linux.intel.com>
>> Sent: Thursday, January 26, 2023 5:55 PM
>>
>> Setup No Execute Enable bit (Bit 133) of a scalable mode PASID
>> entry. It is required when XD bit of the first level page table
>> entry is about to be set.
> "is about to set" sounds like the NXE bit is set conditionally when
> certain event happens. But the actual definition of NXE bit is to
> allow the use of XD bit of the first level page table.
>
> With the comment fixed:
>
> Reviewed-by: Kevin Tian<kevin.tian@intel.com>
Updated. Thank you, Kevin.
Best regards,
baolu
next prev parent reply other threads:[~2023-01-28 7:42 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-01-26 9:54 Lu Baolu
2023-01-28 7:19 ` Tian, Kevin
2023-01-28 7:42 ` Baolu Lu [this message]
2023-01-31 7:53 ` Baolu Lu
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