From: Baolu Lu <baolu.lu@linux.intel.com>
To: iommu@lists.linux.dev
Cc: baolu.lu@linux.intel.com, Joerg Roedel <joro@8bytes.org>,
Will Deacon <will@kernel.org>,
Robin Murphy <robin.murphy@arm.com>,
Kevin Tian <kevin.tian@intel.com>,
Ashok Raj <ashok.raj@intel.com>,
linux-kernel@vger.kernel.org
Subject: Re: [PATCH 1/1] iommu/vt-d: Set No Execute Enable bit in PASID table entry
Date: Tue, 31 Jan 2023 15:53:20 +0800 [thread overview]
Message-ID: <a9a4552e-a401-3ef3-1a29-f4b8f169afa0@linux.intel.com> (raw)
In-Reply-To: <20230126095438.354205-1-baolu.lu@linux.intel.com>
On 2023/1/26 17:54, Lu Baolu wrote:
> Setup No Execute Enable bit (Bit 133) of a scalable mode PASID
> entry. It is required when XD bit of the first level page table
> entry is about to be set.
>
> Fixes: ddf09b6d43ec ("iommu/vt-d: Setup pasid entries for iova over first level")
> Signed-off-by: Ashok Raj<ashok.raj@intel.com>
> Signed-off-by: Lu Baolu<baolu.lu@linux.intel.com>
Patch queued for v6.3.
https://lore.kernel.org/linux-iommu/20230131073740.378984-1-baolu.lu@linux.intel.com/
Best regards,
baolu
prev parent reply other threads:[~2023-01-31 7:53 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-01-26 9:54 Lu Baolu
2023-01-28 7:19 ` Tian, Kevin
2023-01-28 7:42 ` Baolu Lu
2023-01-31 7:53 ` Baolu Lu [this message]
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