Re: [PATCH net-next v12 04/12] dpll: sit9531x: read DPLL types and pin properties from system firmware

[Ivan Vecera <ivecera@redhat.com>]

On 10/9/26 20:31, Ali Rouhi wrote:
> From: Oleg Zadorozhnyi <Oleg.Zadorozhnyi@devoxsoftware.com>
> 
> The DPLL core wants a type per device and a property set per pin: a
> label, the direction, the capabilities, and the frequencies the pin
> supports.  None of that can be read from the chip -- which frequencies a
> board actually presents on a given input is a board fact -- so they come
> from the firmware node, with defaults for a node that does not describe
> them.
> 
> Input pins are interleaved P and N lanes of four differential pairs, so a
> logical index maps to a pair and a lane, and a pair configured
> single-ended presents two independent inputs where a differential one
> presents one.  The labels follow from that, and the two extra input
> positions -- the crystal and the inter-PLL sync net -- are named
> separately.
> 
> One of the advertised properties is worth naming.  An output whose node
> lists no supported frequencies is advertised as a continuous range rather
> than nothing at all, since those pins do accept a frequency set; a
> request inside the range that the integer output divider cannot produce
> is refused when it is made.
> 
> Kept in its own file, and introduced before anything is registered, so
> the registration code that follows has nothing to say about firmware.
> 
> Signed-off-by: Oleg Zadorozhnyi <Oleg.Zadorozhnyi@devoxsoftware.com>
> Assisted-by: LLM
> Signed-off-by: Ali Rouhi <arouhi@sitime.com>
Reviewed-by: Ivan Vecera <ivecera@redhat.com>