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From: Shrikanth Hegde <sshegde@linux.ibm.com>
To: Thomas Gleixner <tglx@kernel.org>, LKML <linux-kernel@vger.kernel.org>
Cc: x86@kernel.org, Michael Kelley <mhklinux@outlook.com>,
	Dmitry Ilvokhin <d@ilvokhin.com>, Radu Rendec <radu@rendec.net>,
	Jan Kiszka <jan.kiszka@siemens.com>,
	Kieran Bingham <kbingham@kernel.org>,
	Florian Fainelli <florian.fainelli@broadcom.com>,
	Marc Zyngier <maz@kernel.org>
Subject: Re: [patch V6 05/16] x86/irq: Suppress unlikely interrupt stats by default
Date: Thu, 21 May 2026 21:22:54 +0530	[thread overview]
Message-ID: <f189bab3-05ab-4815-a3e1-3365b3855731@linux.ibm.com> (raw)
In-Reply-To: <20260517194931.276486277@kernel.org>



On 5/18/26 1:31 AM, Thomas Gleixner wrote:
> From: Thomas Gleixner <tglx@kernel.org>
> 
> Unlikely interrupt counters like the spurious vector and the synthetic APIC
> ICR read retry show up in /proc/interrupts with all counts 0 most of the
> time.
> 
> As these are events which should never happen, suppress them by default and
> enable them for output when they actually happen.
> 
> This requires a seperate bitmap as the description array is marked
> __ro_after_init. With that bitmap in place it becomes RO data.
> 
> Signed-off-by: Thomas Gleixner <tglx@kernel.org>
> Tested-by: Michael Kelley <mhklinux@outlook.com>
> Reviewed-by: Radu Rendec <radu@rendec.net>
> ---
> V5: Move irq_stat_inc_and_enable() here
> V4: Fix the bad idea of writing to __ro_after_init marked data
> V3: New patch
> ---
>   arch/x86/include/asm/hardirq.h |    1 +
>   arch/x86/kernel/apic/apic.c    |    2 +-
>   arch/x86/kernel/apic/ipi.c     |    2 +-
>   arch/x86/kernel/irq.c          |   38 ++++++++++++++++++++++++++++----------
>   4 files changed, 31 insertions(+), 12 deletions(-)
> --- a/arch/x86/include/asm/hardirq.h
> +++ b/arch/x86/include/asm/hardirq.h
> @@ -68,6 +68,7 @@ DECLARE_PER_CPU_ALIGNED(struct pi_desc,
>   #define __ARCH_IRQ_STAT
>   
>   #define inc_irq_stat(index)	this_cpu_inc(irq_stat.counts[IRQ_COUNT_##index])
> +void irq_stat_inc_and_enable(enum irq_stat_counts which);
>   
>   #ifdef CONFIG_X86_LOCAL_APIC
>   #define inc_perf_irq_stat()	inc_irq_stat(APIC_PERF)
> --- a/arch/x86/kernel/apic/apic.c
> +++ b/arch/x86/kernel/apic/apic.c
> @@ -2114,7 +2114,7 @@ static noinline void handle_spurious_int
>   
>   	trace_spurious_apic_entry(vector);
>   
> -	inc_irq_stat(SPURIOUS);
> +	irq_stat_inc_and_enable(IRQ_COUNT_SPURIOUS);
>   
>   	/*
>   	 * If this is a spurious interrupt then do not acknowledge
> --- a/arch/x86/kernel/apic/ipi.c
> +++ b/arch/x86/kernel/apic/ipi.c
> @@ -120,7 +120,7 @@ u32 apic_mem_wait_icr_idle_timeout(void)
>   	for (cnt = 0; cnt < 1000; cnt++) {
>   		if (!(apic_read(APIC_ICR) & APIC_ICR_BUSY))
>   			return 0;
> -		inc_irq_stat(ICR_READ_RETRY);
> +		irq_stat_inc_and_enable(IRQ_COUNT_ICR_READ_RETRY);
>   		udelay(100);
>   	}
>   	return APIC_ICR_BUSY;
> --- a/arch/x86/kernel/irq.c
> +++ b/arch/x86/kernel/irq.c
> @@ -68,19 +68,24 @@ struct irq_stat_info {
>   	const char	*text;
>   };
>   
> +#define DEFAULT_SUPPRESSED_VECTOR	UINT_MAX
> +
>   #define ISS(idx, sym, txt) [IRQ_COUNT_##idx] = { .symbol = sym, .text = txt }
>   
>   #define ITS(idx, sym, txt) [IRQ_COUNT_##idx] =				\
>   	{ .skip_vector = idx## _VECTOR, .symbol = sym, .text = txt }
>   
> -static struct irq_stat_info irq_stat_info[IRQ_COUNT_MAX] __ro_after_init = {
> +#define IDS(idx, sym, txt) [IRQ_COUNT_##idx] =				\
> +	{ .skip_vector = DEFAULT_SUPPRESSED_VECTOR, .symbol = sym, .text = txt }
> +
> +static const struct irq_stat_info irq_stat_info[IRQ_COUNT_MAX] = {
>   	ISS(NMI,			"NMI",	"  Non-maskable interrupts\n"),
>   #ifdef CONFIG_X86_LOCAL_APIC
>   	ISS(APIC_TIMER,			"LOC",	"  Local timer interrupts\n"),
> -	ISS(SPURIOUS,			"SPU",	"  Spurious interrupts\n"),
> +	IDS(SPURIOUS,			"SPU",	"  Spurious interrupts\n"),
>   	ISS(APIC_PERF,			"PMI",	"  Performance monitoring interrupts\n"),
>   	ISS(IRQ_WORK,			"IWI",	"  IRQ work interrupts\n"),
> -	ISS(ICR_READ_RETRY,		"RTR",	"  APIC ICR read retries\n"),
> +	IDS(ICR_READ_RETRY,		"RTR",	"  APIC ICR read retries\n"),
>   	ISS(X86_PLATFORM_IPI,		"PLT",	"  Platform interrupts\n"),
>   #endif
>   #ifdef CONFIG_SMP
> @@ -121,34 +126,47 @@ static struct irq_stat_info irq_stat_inf
>   #endif
>   };
>   
> +static DECLARE_BITMAP(irq_stat_count_show, IRQ_COUNT_MAX) __read_mostly;
> +
>   static int __init irq_init_stats(void)
>   {
> -	struct irq_stat_info *info = irq_stat_info;
> +	const struct irq_stat_info *info = irq_stat_info;
>   
>   	for (unsigned int i = 0; i < ARRAY_SIZE(irq_stat_info); i++, info++) {
> -		if (info->skip_vector && test_bit(info->skip_vector, system_vectors))
> -			info->skip_vector = 0;
> +		if (!info->skip_vector || (info->skip_vector != DEFAULT_SUPPRESSED_VECTOR &&
> +					   test_bit(info->skip_vector, system_vectors)))
> +			set_bit(i, irq_stat_count_show);
>   	}
>   
>   #ifdef CONFIG_X86_LOCAL_APIC
>   	if (!x86_platform_ipi_callback)
> -		irq_stat_info[IRQ_COUNT_X86_PLATFORM_IPI].skip_vector = 1;
> +		clear_bit(IRQ_COUNT_X86_PLATFORM_IPI, irq_stat_count_show);
>   #endif
>   
>   #ifdef CONFIG_X86_POSTED_MSI
>   	if (!posted_msi_enabled())
> -		irq_stat_info[IRQ_COUNT_POSTED_MSI_NOTIFICATION].skip_vector = 1;
> +		clear_bit(IRQ_COUNT_POSTED_MSI_NOTIFICATION, irq_stat_count_show);
>   #endif
>   
>   #ifdef CONFIG_X86_MCE_AMD
>   	if (boot_cpu_data.x86_vendor != X86_VENDOR_AMD &&
>   	    boot_cpu_data.x86_vendor != X86_VENDOR_HYGON)
> -		irq_stat_info[IRQ_COUNT_DEFERRED_ERROR].skip_vector = 1;
> +		clear_bit(IRQ_COUNT_DEFERRED_ERROR, irq_stat_count_show);
>   #endif
>   	return 0;
>   }
>   late_initcall(irq_init_stats);
>   
> +/*
> + * Used for default enabled counters to increment the stats and to enable the
> + * entry for /proc/interrupts output.
> + */
> +void irq_stat_inc_and_enable(enum irq_stat_counts which)
> +{
> +	this_cpu_inc(irq_stat.counts[which]);
> +	set_bit(which, irq_stat_count_show);
> +}
> +
>   #ifdef CONFIG_PROC_FS
>   /*
>    * /proc/interrupts printing for arch specific interrupts
> @@ -158,7 +176,7 @@ int arch_show_interrupts(struct seq_file
>   	const struct irq_stat_info *info = irq_stat_info;
>   
>   	for (unsigned int i = 0; i < ARRAY_SIZE(irq_stat_info); i++, info++) {
> -		if (info->skip_vector)
> +		if (!test_bit(i, irq_stat_count_show))
>   			continue;

If this is done, then those lines will be absent in /proc/interrupts right?

If there was a tool expecting these entries, it will fail get to see that entry.
Is that ok?

>   
>   		seq_printf(p, "%*s:", prec, info->symbol);
> 


  reply	other threads:[~2026-05-21 15:53 UTC|newest]

Thread overview: 47+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-05-17 20:01 [patch V6 00/16] Improve /proc/interrupts further Thomas Gleixner
2026-05-17 20:01 ` [patch V6 01/16] x86/irq: Optimize interrupts decimals printing Thomas Gleixner
2026-05-26 14:22   ` [tip: irq/core] " tip-bot2 for Dmitry Ilvokhin
2026-05-17 20:01 ` [patch V6 02/16] genirq/proc: Avoid formatting zero counts in /proc/interrupts Thomas Gleixner
2026-05-19 21:24   ` Shrikanth Hegde
2026-05-26 14:22   ` [tip: irq/core] " tip-bot2 for Thomas Gleixner
2026-05-17 20:01 ` [patch V6 03/16] genirq/proc: Utilize irq_desc::tot_count to avoid evaluation Thomas Gleixner
2026-05-26 14:22   ` [tip: irq/core] " tip-bot2 for Thomas Gleixner
2026-05-17 20:01 ` [patch V6 04/16] x86/irq: Make irqstats array based Thomas Gleixner
2026-05-26 14:22   ` [tip: irq/core] " tip-bot2 for Thomas Gleixner
2026-05-30  9:36   ` [patch V6 04/16] " Dan Carpenter
2026-05-17 20:01 ` [patch V6 05/16] x86/irq: Suppress unlikely interrupt stats by default Thomas Gleixner
2026-05-21 15:52   ` Shrikanth Hegde [this message]
2026-05-21 20:46     ` Thomas Gleixner
2026-05-23 17:48   ` Shrikanth Hegde
2026-05-24 12:37     ` Thomas Gleixner
2026-05-26 14:22   ` [tip: irq/core] " tip-bot2 for Thomas Gleixner
2026-05-17 20:01 ` [patch V6 06/16] x86/irq: Move IOAPIC misrouted and PIC/APIC error counts into irq_stats Thomas Gleixner
2026-05-26 14:22   ` [tip: irq/core] " tip-bot2 for Thomas Gleixner
2026-05-17 20:02 ` [patch V6 07/16] scripts/gdb: Update x86 interrupts to the array based storage Thomas Gleixner
2026-05-26 14:22   ` [tip: irq/core] " tip-bot2 for Thomas Gleixner
2026-05-17 20:02 ` [patch V6 08/16] genirq: Expose nr_irqs in core code Thomas Gleixner
2026-05-19 21:29   ` Shrikanth Hegde
2026-05-26 14:22   ` [tip: irq/core] " tip-bot2 for Thomas Gleixner
2026-05-17 20:02 ` [patch V6 09/16] genirq/manage: Make NMI cleanup RT safe Thomas Gleixner
2026-05-26 14:22   ` [tip: irq/core] " tip-bot2 for Thomas Gleixner
2026-05-17 20:02 ` [patch V6 10/16] genirq: Cache the condition for /proc/interrupts exposure Thomas Gleixner
2026-05-26 14:22   ` [tip: irq/core] " tip-bot2 for Thomas Gleixner
2026-05-17 20:02 ` [patch V6 11/16] genirq: Calculate precision only when required Thomas Gleixner
2026-05-26 14:22   ` [tip: irq/core] " tip-bot2 for Thomas Gleixner
2026-05-17 20:02 ` [patch V6 12/16] genirq/proc: Increase default interrupt number precision to four Thomas Gleixner
2026-05-26 14:22   ` [tip: irq/core] " tip-bot2 for Thomas Gleixner
2026-05-17 20:02 ` [patch V6 13/16] genirq: Add rcuref count to struct irq_desc Thomas Gleixner
2026-05-26 14:22   ` [tip: irq/core] " tip-bot2 for Thomas Gleixner
2026-05-17 20:02 ` [patch V6 14/16] genirq: Expose irq_find_desc_at_or_after() in core code Thomas Gleixner
2026-05-26 14:22   ` [tip: irq/core] " tip-bot2 for Thomas Gleixner
2026-05-17 20:02 ` [patch V6 15/16] genirq/proc: Runtime size the chip name Thomas Gleixner
2026-05-26 14:22   ` [tip: irq/core] " tip-bot2 for Thomas Gleixner
2026-05-17 20:02 ` [patch V6 16/16] genirq/proc: Speed up /proc/interrupts iteration Thomas Gleixner
2026-05-26 14:22   ` [tip: irq/core] " tip-bot2 for Thomas Gleixner
2026-05-18  3:54 ` [patch V6 00/16] Improve /proc/interrupts further mhklkml
2026-05-19 21:18 ` Shrikanth Hegde
2026-05-20 15:27   ` Thomas Gleixner
2026-05-21  4:34     ` Shrikanth Hegde
2026-05-21  7:53       ` Thomas Gleixner
2026-05-21 14:48         ` Shrikanth Hegde
2026-05-21 21:07           ` Thomas Gleixner

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