From: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
To: Pankaj Gupta <pankaj.gupta@nxp.com>,
shawnguo@kernel.org, s.hauer@pengutronix.de,
kernel@pengutronix.de, clin@suse.com, conor+dt@kernel.org,
pierre.gondois@arm.com, ping.bai@nxp.com, xiaoning.wang@nxp.com,
wei.fang@nxp.com, peng.fan@nxp.com, haibo.chen@nxp.com,
festevam@gmail.com, linux-imx@nxp.com, davem@davemloft.net,
robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org,
linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org, gaurav.jain@nxp.com,
alexander.stein@ew.tq-group.com, sahil.malhotra@nxp.com,
aisheng.dong@nxp.com, V.Sethi@nxp.com
Subject: Re: [PATCH v4 1/7] dt-bindings: arm: fsl: add se-fw binding doc
Date: Wed, 12 Jul 2023 20:38:43 +0200 [thread overview]
Message-ID: <f3965cf1-3f0a-15fe-7dd3-e83817a4ba3a@linaro.org> (raw)
In-Reply-To: <20230712121219.2654234-2-pankaj.gupta@nxp.com>
On 12/07/2023 14:12, Pankaj Gupta wrote:
> The NXP's i.MX EdgeLock Enclave, a HW IP creating an embedded
> secure enclave within the SoC boundary to enable features like
> - HSM
> - SHE
> - V2X
>
> Communicates via message unit with linux kernel. This driver
> is enables communication ensuring well defined message sequence
> protocol between Application Core and enclave's firmware.
>
> Driver configures multiple misc-device on the MU, for multiple
> user-space applications can communicate on single MU.
>
> It exists on some i.MX processors. e.g. i.MX8ULP, i.MX93 etc.
>
> Signed-off-by: Pankaj Gupta <pankaj.gupta@nxp.com>
> ---
> .../bindings/arm/freescale/fsl,se-fw.yaml | 121 ++++++++++++++++++
> 1 file changed, 121 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/arm/freescale/fsl,se-fw.yaml
>
> diff --git a/Documentation/devicetree/bindings/arm/freescale/fsl,se-fw.yaml b/Documentation/devicetree/bindings/arm/freescale/fsl,se-fw.yaml
> new file mode 100644
> index 000000000000..7567da0b4c21
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/arm/freescale/fsl,se-fw.yaml
> @@ -0,0 +1,121 @@
> +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/arm/freescale/fsl,se-fw.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: NXP i.MX EdgeLock Enclave Firmware (ELEFW)
> +
> +maintainers:
> + - Pankaj Gupta <pankaj.gupta@nxp.com>
> +
> +description: |
> +
> + The NXP's i.MX EdgeLock Enclave, a HW IP creating an embedded
> + secure enclave within the SoC boundary to enable features like
> + - HSM
> + - SHE
> + - V2X
> +
> + It uses message unit to communicate and coordinate to pass messages
> + (e.g., data, status and control) through its interfaces.
> +
> + This driver configures multiple misc-devices on the MU, to exchange
> + messages from User-space application and NXP's Edgelocke Enclave firmware.
> + The driver ensures that the messages must follow the following protocol
> + defined.
> +
> + Non-Secure + Secure
> + |
> + |
> + +---------+ +-------------+ |
> + | ele_mu.c+<---->+imx-mailbox.c| |
> + | | | mailbox.c +<-->+------+ +------+
> + +---+-----+ +-------------+ | MU X +<-->+ ELE |
> + | +------+ +------+
> + +----------------+ |
> + | | |
> + v v |
> + logical logical |
> + receiver waiter |
> + + + |
> + | | |
> + | | |
> + | +----+------+ |
> + | | | |
> + | | | |
> + device_ctx device_ctx device_ctx |
> + |
> + User 0 User 1 User Y |
> + +------+ +------+ +------+ |
> + |misc.c| |misc.c| |misc.c| |
> + kernel space +------+ +------+ +------+ |
> + |
> + +------------------------------------------------------ |
> + | | | |
> + userspace /dev/ele_muXch0 | | |
> + /dev/ele_muXch1 | |
> + /dev/ele_muXchY |
> + |
> +
> + When a user sends a command to the ELE, it registers its device_ctx as
> + waiter of a response from ELE.
> +
> + A user can be registered as receiver of command from the ELE.
> + Create char devices in /dev as channels of the form /dev/ele_muXchY with X
> + the id of the driver and Y for each users. It allows to send and receive
> + messages to the NXP EdgeLock Enclave IP on NXP SoC, where current possible
> + value, i.e., supported SoC(s) are imx8ulp, imx93.
> +
> +properties:
> + compatible:
> + enum:
> + - fsl,imx-ele
> + - fsl,imx93-ele
> +
> + mboxes:
> + description:
> + A list of phandles of TX MU channels followed by a list of phandles of
> + RX MU channels. The number of expected tx and rx channels is 1 TX, and
> + 1 RX channels. All MU channels must be within the same MU instance.
> + Cross instances are not allowed. The MU instance to be used is S4MUAP
> + for imx8ulp & imx93. Users need to ensure that used MU instance does not
> + conflict with other execution environments.
> + items:
> + - description: TX0 MU channel
> + - description: RX0 MU channel
> +
> + mbox-names:
> + items:
> + - const: tx
> + - const: rx
> +
> + fsl,mu-did:
> + $ref: /schemas/types.yaml#/definitions/uint32
> + description:
> + Owner of message-unit, is identified via Domain ID or did.
What is Domain ID?
> +
> + fsl,mu-id:
> + $ref: /schemas/types.yaml#/definitions/uint32
> + description:
> + Identifier to the message-unit among the multiple message-unit that exists on SoC.
> + It is used to create the channels, default to 2
Do you expect then multiple ele nodes in the DTS? What are these two
properties and why they are fixed per SoC, but still embedded in DTS?
> +
> +
Drop stray blank line.
> +required:
> + - compatible
> + - mboxes
> + - mbox-names
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + ele_mu: ele_mu {
No underscores in node names, generic node names, e.g. firmware. Look at
existing code.
> + compatible = "fsl,imx93-ele";
> + mbox-names = "tx", "rx";
> + mboxes = <&s4muap 2 0
> + &s4muap 3 0>;
Two items, not one.
> + fsl,mu-did = <1>;
> + fsl,mu-id = <1>;
> + };
Plus you clearly did not test the binding and DTS. You said you did some
internal review, so I assume this also includes some testing. How did
you test your DTS?
Best regards,
Krzysztof
next prev parent reply other threads:[~2023-07-12 18:38 UTC|newest]
Thread overview: 33+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-07-12 12:12 [PATCH v4 0/7] firmware: imx: NXP Edgelock Enclave MUAP Driver Pankaj Gupta
2023-07-12 12:12 ` [PATCH v4 1/7] dt-bindings: arm: fsl: add se-fw binding doc Pankaj Gupta
2023-07-12 18:26 ` Conor Dooley
2023-07-12 18:34 ` Krzysztof Kozlowski
2023-07-24 6:37 ` [EXT] " Pankaj Gupta
2023-07-24 6:47 ` Conor Dooley
2023-07-27 9:20 ` Pankaj Gupta
2023-07-12 18:38 ` Krzysztof Kozlowski [this message]
2023-07-24 6:37 ` Pankaj Gupta
2023-07-24 7:16 ` Krzysztof Kozlowski
2023-07-12 12:12 ` [PATCH v4 2/7] arm64: dts: imx8ulp-evk: added nxp secure enclave firmware Pankaj Gupta
2023-07-12 18:37 ` Krzysztof Kozlowski
2023-08-08 11:07 ` [EXT] " Pankaj Gupta
2023-08-08 14:48 ` Krzysztof Kozlowski
2023-08-15 13:03 ` Pankaj Gupta
2023-07-12 12:12 ` [PATCH v4 3/7] arm64: dts: imx8ulp-evk: reserved mem-ranges to constrain ele_fw dma-range Pankaj Gupta
2023-07-12 12:12 ` [PATCH v4 4/7] arm64: dts: imx93-11x11-evk: added nxp secure enclave fw Pankaj Gupta
2023-07-12 19:07 ` Krzysztof Kozlowski
2023-07-24 12:57 ` [EXT] " Pankaj Gupta
2023-08-08 11:34 ` Pankaj Gupta
2023-08-08 11:49 ` Pankaj Gupta
2023-08-08 14:52 ` Krzysztof Kozlowski
2023-08-15 13:19 ` Pankaj Gupta
2023-07-12 12:12 ` [PATCH v4 5/7] arm64: dts: imx93-11x11-evk: reserved mem-ranges to constrain ele_fw dma-range Pankaj Gupta
2023-07-12 12:12 ` [PATCH v4 6/7] firmware: imx: add driver for NXP EdgeLock Enclave Pankaj Gupta
2023-07-12 18:56 ` Krzysztof Kozlowski
2023-08-08 12:36 ` [EXT] " Pankaj Gupta
2023-08-24 18:43 ` Krzysztof Kozlowski
[not found] ` <DU2PR04MB8630694397EEE3275F01A4E59517A@DU2PR04MB8630.eurprd04.prod.outlook.com>
2023-08-14 7:53 ` Varun Sethi
2023-07-12 12:12 ` [PATCH v4 7/7] MAINTAINERS: Added maintainer details Pankaj Gupta
2023-07-12 14:57 ` Randy Dunlap
2023-07-12 19:04 ` Krzysztof Kozlowski
2023-07-12 18:15 ` Conor Dooley
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=f3965cf1-3f0a-15fe-7dd3-e83817a4ba3a@linaro.org \
--to=krzysztof.kozlowski@linaro.org \
--cc=V.Sethi@nxp.com \
--cc=aisheng.dong@nxp.com \
--cc=alexander.stein@ew.tq-group.com \
--cc=clin@suse.com \
--cc=conor+dt@kernel.org \
--cc=davem@davemloft.net \
--cc=devicetree@vger.kernel.org \
--cc=festevam@gmail.com \
--cc=gaurav.jain@nxp.com \
--cc=haibo.chen@nxp.com \
--cc=kernel@pengutronix.de \
--cc=krzysztof.kozlowski+dt@linaro.org \
--cc=linux-arm-kernel@lists.infradead.org \
--cc=linux-imx@nxp.com \
--cc=linux-kernel@vger.kernel.org \
--cc=pankaj.gupta@nxp.com \
--cc=peng.fan@nxp.com \
--cc=pierre.gondois@arm.com \
--cc=ping.bai@nxp.com \
--cc=robh+dt@kernel.org \
--cc=s.hauer@pengutronix.de \
--cc=sahil.malhotra@nxp.com \
--cc=shawnguo@kernel.org \
--cc=wei.fang@nxp.com \
--cc=xiaoning.wang@nxp.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox
all inboxes | Powered by JetHome®