From: Xi Ruoyao <xry111@xry111.site>
To: Rui Wang <wangrui@loongson.cn>
Cc: Huacai Chen <chenhuacai@kernel.org>,
WANG Xuerui <kernel@xen0n.name>,
loongarch@lists.linux.dev, linux-kernel@vger.kernel.org,
loongson-kernel@lists.loongnix.cn
Subject: Re: [PATCH] LoongArch: Improve memory ops
Date: Mon, 10 Apr 2023 22:37:56 +0800 [thread overview]
Message-ID: <f568fd917bb8789fcef4206e256ef045176605e2.camel@xry111.site> (raw)
In-Reply-To: <CAHirt9jXQcvSQPEFgW6B-qeakcRXGFfd1eYCw2g23Fmu4bbS8g@mail.gmail.com>
On Mon, 2023-04-10 at 22:19 +0800, Rui Wang wrote:
> On Mon, Apr 10, 2023 at 8:20 PM Xi Ruoyao <xry111@xry111.site> wrote:
> >
> > On Mon, 2023-04-10 at 19:57 +0800, WANG rui wrote:
> > > + /* align up address */
> > > + andi t1, a0, 7
> > > + sub.d a0, a0, t1
> >
> > bstrins.d a0, zero, 2, 0
> >
> > Likewise for other aligning operations if the temporary is not used.
>
> I think we're on the same page. I had previously tested this on the
> user-space version[1], but it's not a performance-critical area.
The point is "if you can reduce one instruction and one register usage
with no harm, why not do it?" :)
AFAIK bstrins.d should be available on all 64-bit LoongArch CPUs.
--
Xi Ruoyao <xry111@xry111.site>
School of Aerospace Science and Technology, Xidian University
next prev parent reply other threads:[~2023-04-10 14:38 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-04-10 11:57 WANG rui
2023-04-10 12:20 ` Xi Ruoyao
2023-04-10 14:19 ` Rui Wang
2023-04-10 14:37 ` Xi Ruoyao [this message]
2023-04-10 15:53 ` WANG Rui
2023-04-10 12:53 ` Xi Ruoyao
2023-04-10 14:22 ` Rui Wang
2023-04-10 14:36 ` Xi Ruoyao
2023-04-10 15:52 ` WANG Rui
2023-04-11 6:21 ` Xi Ruoyao
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