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From: Zhangfei Gao <zhangfei.gao@linaro.org>
To: Jean-Philippe Brucker <jean-philippe@linaro.org>
Cc: Bjorn Helgaas <bhelgaas@google.com>,
	Greg Kroah-Hartman <gregkh@linuxfoundation.org>,
	Arnd Bergmann <arnd@arndb.de>,
	kenneth-lee-2012@foxmail.com, Wangzhou <wangzhou1@hisilicon.com>,
	linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org
Subject: Re: [RFC PATCH] PCI: Remove End-End TLP as PASID dependency
Date: Wed, 10 Jun 2020 16:00:25 +0800	[thread overview]
Message-ID: <f59c5a39-b13e-8232-57cb-089a8d62a2a7@linaro.org> (raw)
In-Reply-To: <20200610074633.GA6844@myrica>



On 2020/6/10 下午3:46, Jean-Philippe Brucker wrote:
> On Wed, Jun 10, 2020 at 12:18:14PM +0800, Zhangfei Gao wrote:
>> Some platform devices appear as PCI and have PCI cfg space,
>> but are actually on the AMBA bus.
>> They can support PASID via smmu stall feature, but does not
>> support tlp since they are not real pci devices.
>> So remove tlp as a PASID dependency.
>>
>> Signed-off-by: Zhangfei Gao <zhangfei.gao@linaro.org>
>> ---
>>   drivers/pci/ats.c | 3 ---
>>   1 file changed, 3 deletions(-)
>>
>> diff --git a/drivers/pci/ats.c b/drivers/pci/ats.c
>> index 390e92f..8e31278 100644
>> --- a/drivers/pci/ats.c
>> +++ b/drivers/pci/ats.c
>> @@ -344,9 +344,6 @@ int pci_enable_pasid(struct pci_dev *pdev, int features)
>>   	if (WARN_ON(pdev->pasid_enabled))
>>   		return -EBUSY;
>>   
>> -	if (!pdev->eetlp_prefix_path)
>> -		return -EINVAL;
>> -
> This check is useful, and follows the PCI specification (4.0r1.0
> 2.2.10.2 End-End TLP Prefix Processing: "Software should ensure that TLPs
> containing End-End TLP Prefixes are not sent to components that do not
> support them.")
Thanks Jean,
>
> Why not set the eetlp_prefix_path bit from a PCI quirk?  Unlike the stall
> problem from the other thread, this one looks like a simple design mistake
> that can be fixed easily in future iterations of the platform: just set
> the "End-End TLP Prefix Supported" bit in the Device Capability 2 Register
> of all bridges.
Yes, we can still set eetlp_prefix_path bit from a PCI quirk.

And we also have considered adding this bit in Device Capability 2 
Register in future silicon.
But we hesitated that it does reflect the real function: from register, 
it can support tlp, but in fact, it does not.

Thanks


  reply	other threads:[~2020-06-10  8:00 UTC|newest]

Thread overview: 6+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-06-10  4:18 Zhangfei Gao
2020-06-10  7:46 ` Jean-Philippe Brucker
2020-06-10  8:00   ` Zhangfei Gao [this message]
2020-06-11 14:11     ` Sinan Kaya
2020-06-11 17:41 ` Bjorn Helgaas
2020-06-13 13:49   ` Zhangfei Gao

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