From: Timur Tabi <timur@codeaurora.org>
To: Florian Fainelli <f.fainelli@gmail.com>,
linux-arm-kernel@lists.infradead.org
Cc: tchalamarla@cavium.com, rrichter@cavium.com, opendmb@gmail.com,
Catalin Marinas <catalin.marinas@arm.com>,
Will Deacon <will.deacon@arm.com>,
Mark Rutland <mark.rutland@arm.com>,
open list <linux-kernel@vger.kernel.org>
Subject: Re: [PATCH] arm64: Make L1_CACHE_SHIFT configurable
Date: Mon, 12 Feb 2018 18:10:38 -0600 [thread overview]
Message-ID: <f5d6d768-d354-56b5-ce0c-4f46d4e6d642@codeaurora.org> (raw)
In-Reply-To: <ffc090d5-62c9-e608-32e2-8d13d01234e6@gmail.com>
On 02/12/2018 05:57 PM, Florian Fainelli wrote:
> That is debatable, is there a good publicly available table of what the
> typical L1 cache line size is on ARMv8 platforms?
I don't have that, but I was under the impression that we moved from 6
to 7 because more and more ARMv8 platforms have 128-byte caches, so that
is the "new normal".
--
Qualcomm Datacenter Technologies, Inc. as an affiliate of Qualcomm
Technologies, Inc. Qualcomm Technologies, Inc. is a member of the
Code Aurora Forum, a Linux Foundation Collaborative Project.
next prev parent reply other threads:[~2018-02-13 0:10 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-02-12 23:45 Florian Fainelli
2018-02-12 23:52 ` Timur Tabi
2018-02-12 23:57 ` Florian Fainelli
2018-02-13 0:10 ` Timur Tabi [this message]
2018-02-13 0:17 ` Florian Fainelli
2018-02-19 23:46 ` Jon Masters
2018-02-13 11:57 ` Catalin Marinas
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