* [PATCH] clk: qcom: gcc-x1e80100: Don't poll the status bit of GCC_USB4_n_SYS_CLK
@ 2026-09-15 19:18 Konrad Dybcio
2026-09-16 3:52 ` Taniya Das
2026-09-16 10:34 ` Abel Vesa
0 siblings, 2 replies; 3+ messages in thread
From: Konrad Dybcio @ 2026-09-15 19:18 UTC (permalink / raw)
To: Bjorn Andersson, Abel Vesa, Stephen Boyd, Brian Masney,
Jerome Brunet, Sibi Sankar, Konrad Dybcio, Rajendra Nayak
Cc: Bryan O'Donoghue, linux-arm-msm, linux-clk, linux-kernel,
Konrad Dybcio
From: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
These clocks are PHY-sourced and their halt bits seem not to update
reliably. Ignore it to prevent spurious warnings.
Fixes: 161b7c401f4b ("clk: qcom: Add Global Clock controller (GCC) driver for X1E80100")
Signed-off-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
---
drivers/clk/qcom/gcc-x1e80100.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/clk/qcom/gcc-x1e80100.c b/drivers/clk/qcom/gcc-x1e80100.c
index 8c146d62c077..754d1e03c2fa 100644
--- a/drivers/clk/qcom/gcc-x1e80100.c
+++ b/drivers/clk/qcom/gcc-x1e80100.c
@@ -6049,7 +6049,7 @@ static struct clk_branch gcc_usb4_0_sb_if_clk = {
static struct clk_branch gcc_usb4_0_sys_clk = {
.halt_reg = 0x9f054,
- .halt_check = BRANCH_HALT,
+ .halt_check = BRANCH_HALT_SKIP,
.clkr = {
.enable_reg = 0x9f054,
.enable_mask = BIT(0),
@@ -6266,7 +6266,7 @@ static struct clk_branch gcc_usb4_1_sb_if_clk = {
static struct clk_branch gcc_usb4_1_sys_clk = {
.halt_reg = 0x2b054,
- .halt_check = BRANCH_HALT,
+ .halt_check = BRANCH_HALT_SKIP,
.clkr = {
.enable_reg = 0x2b054,
.enable_mask = BIT(0),
@@ -6483,7 +6483,7 @@ static struct clk_branch gcc_usb4_2_sb_if_clk = {
static struct clk_branch gcc_usb4_2_sys_clk = {
.halt_reg = 0x11054,
- .halt_check = BRANCH_HALT,
+ .halt_check = BRANCH_HALT_SKIP,
.clkr = {
.enable_reg = 0x11054,
.enable_mask = BIT(0),
---
base-commit: 1a1de54f7369cd2b5bac0f265910e60ad3a6b4c3
change-id: 20260915-topic-hamoa_clk_usb4-5573d067a4c3
Best regards,
--
Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
^ permalink raw reply [flat|nested] 3+ messages in thread* Re: [PATCH] clk: qcom: gcc-x1e80100: Don't poll the status bit of GCC_USB4_n_SYS_CLK
2026-09-15 19:18 [PATCH] clk: qcom: gcc-x1e80100: Don't poll the status bit of GCC_USB4_n_SYS_CLK Konrad Dybcio
@ 2026-09-16 3:52 ` Taniya Das
2026-09-16 10:34 ` Abel Vesa
1 sibling, 0 replies; 3+ messages in thread
From: Taniya Das @ 2026-09-16 3:52 UTC (permalink / raw)
To: Konrad Dybcio, Bjorn Andersson, Abel Vesa, Stephen Boyd,
Brian Masney, Jerome Brunet, Sibi Sankar, Rajendra Nayak
Cc: Bryan O'Donoghue, linux-arm-msm, linux-clk, linux-kernel,
Konrad Dybcio
On 9/16/2026 12:48 AM, Konrad Dybcio wrote:
> rom: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
>
> These clocks are PHY-sourced and their halt bits seem not to update
> reliably. Ignore it to prevent spurious warnings.
>
> Fixes: 161b7c401f4b ("clk: qcom: Add Global Clock controller (GCC) driver for X1E80100")
> Signed-off-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
> ---
> drivers/clk/qcom/gcc-x1e80100.c | 6 +++---
> 1 file changed, 3 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/clk/qcom/gcc-x1e80100.c b/drivers/clk/qcom/gcc-x1e80100.c
> index 8c146d62c077..754d1e03c2fa 100644
> --- a/drivers/clk/qcom/gcc-x1e80100.c
> +++ b/drivers/clk/qcom/gcc-x1e80100.c
Reviewed-by: Taniya Das <taniya.das@oss.qualcomm.com>
--
Thanks,
Taniya Das
^ permalink raw reply [flat|nested] 3+ messages in thread* Re: [PATCH] clk: qcom: gcc-x1e80100: Don't poll the status bit of GCC_USB4_n_SYS_CLK
2026-09-15 19:18 [PATCH] clk: qcom: gcc-x1e80100: Don't poll the status bit of GCC_USB4_n_SYS_CLK Konrad Dybcio
2026-09-16 3:52 ` Taniya Das
@ 2026-09-16 10:34 ` Abel Vesa
1 sibling, 0 replies; 3+ messages in thread
From: Abel Vesa @ 2026-09-16 10:34 UTC (permalink / raw)
To: Konrad Dybcio
Cc: Bjorn Andersson, Abel Vesa, Stephen Boyd, Brian Masney,
Jerome Brunet, Sibi Sankar, Rajendra Nayak, Bryan O'Donoghue,
linux-arm-msm, linux-clk, linux-kernel, Konrad Dybcio
On 26-09-15 21:18:15, Konrad Dybcio wrote:
> From: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
>
> These clocks are PHY-sourced and their halt bits seem not to update
> reliably. Ignore it to prevent spurious warnings.
>
> Fixes: 161b7c401f4b ("clk: qcom: Add Global Clock controller (GCC) driver for X1E80100")
> Signed-off-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Reviewed-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
^ permalink raw reply [flat|nested] 3+ messages in thread
end of thread, other threads:[~2026-09-16 10:35 UTC | newest]
Thread overview: 3+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2026-09-15 19:18 [PATCH] clk: qcom: gcc-x1e80100: Don't poll the status bit of GCC_USB4_n_SYS_CLK Konrad Dybcio
2026-09-16 3:52 ` Taniya Das
2026-09-16 10:34 ` Abel Vesa
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox
all inboxes | Powered by JetHome®