From: bot+bpf-ci@kernel.org
To: cp0613@linux.alibaba.com,ast@kernel.org,daniel@iogearbox.net,andrii@kernel.org,memxor@gmail.com,bjorn@kernel.org,puranjay@kernel.org
Cc: ihor.solodrai@linux.dev,eddyz87@gmail.com,martin.lau@linux.dev,song@kernel.org,yonghong.song@linux.dev,jolsa@kernel.org,emil@etsalapatis.com,pulehui@huawei.com,pjw@kernel.org,palmer@dabbelt.com,shuah@kernel.org,guoren@kernel.org,bpf@vger.kernel.org,linux-riscv@lists.infradead.org,linux-kselftest@vger.kernel.org,linux-kernel@vger.kernel.org,ast@kernel.org,andrii@kernel.org,daniel@iogearbox.net,martin.lau@kernel.org,eddyz87@gmail.com,yonghong.song@linux.dev,clm@meta.com,ihor.solodrai@linux.dev
Subject: Re: [PATCH bpf-next v2 1/2] bpf, riscv: Add support for signed arena loads
Date: Wed, 19 Aug 2026 09:37:15 +0000 (UTC) [thread overview]
Message-ID: <f6d031ece454ad8a2a3e09bbdf48d9030c74cb6741f76aabf58bf7af1931abfd@mail.kernel.org> (raw)
In-Reply-To: <a78cd29b238aa1aba87efeb2fc09d25a56c22f69.1787128322.git.cp0613@linux.alibaba.com>
[-- Attachment #1: Type: text/plain, Size: 1986 bytes --]
> diff --git a/arch/riscv/net/bpf_jit_comp64.c b/arch/riscv/net/bpf_jit_comp64.c
> index 74efe4b138d2..56196b001286 100644
> --- a/arch/riscv/net/bpf_jit_comp64.c
> +++ b/arch/riscv/net/bpf_jit_comp64.c
[ ... ]
> @@ -1908,13 +1910,19 @@ int bpf_jit_emit_insn(const struct bpf_insn *insn, struct rv_jit_context *ctx,
> case BPF_LDX | BPF_PROBE_MEM32 | BPF_H:
> case BPF_LDX | BPF_PROBE_MEM32 | BPF_W:
> case BPF_LDX | BPF_PROBE_MEM32 | BPF_DW:
> + /* LDX | PROBE_MEM32SX: sign-extending arena load */
> + case BPF_LDX | BPF_PROBE_MEM32SX | BPF_B:
> + case BPF_LDX | BPF_PROBE_MEM32SX | BPF_H:
> + case BPF_LDX | BPF_PROBE_MEM32SX | BPF_W:
> {
> bool sign_ext;
>
> sign_ext = BPF_MODE(insn->code) == BPF_MEMSX ||
> - BPF_MODE(insn->code) == BPF_PROBE_MEMSX;
> + BPF_MODE(insn->code) == BPF_PROBE_MEMSX ||
> + BPF_MODE(insn->code) == BPF_PROBE_MEM32SX;
>
> - if (BPF_MODE(insn->code) == BPF_PROBE_MEM32) {
> + if (BPF_MODE(insn->code) == BPF_PROBE_MEM32 ||
> + BPF_MODE(insn->code) == BPF_PROBE_MEM32SX) {
> emit_add(RV_REG_T2, rs, RV_REG_ARENA, ctx);
> rs = RV_REG_T2;
> }
This isn't a bug, but would the comment fit the surrounding style better as
an expression? The neighbouring case-group comments all spell the access
out in pseudo-code form:
/* LDX: dst = *(unsigned size *)(src + off) */
/* LDSX: dst = *(signed size *)(src + off) */
/* LDX | PROBE_MEM32: dst = *(unsigned size *)(src + RV_REG_ARENA + off) */
/* ST | PROBE_MEM32: *(size *)(dst + RV_REG_ARENA + off) = imm */
/* STX | PROBE_MEM32: *(size *)(dst + RV_REG_ARENA + off) = src */
Something like this would match the pattern:
/* LDX | PROBE_MEM32SX: dst = *(signed size *)(src + RV_REG_ARENA + off) */
---
AI reviewed your patch. Please fix the bug or email reply why it's not a bug.
See: https://github.com/kernel-patches/vmtest/blob/master/ci/claude/README.md
CI run summary: https://github.com/kernel-patches/bpf/actions/runs/32235574103
next prev parent reply other threads:[~2026-08-19 9:37 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-08-19 8:53 [PATCH bpf-next v2 0/2] " Chen Pei
2026-08-19 8:53 ` [PATCH bpf-next v2 1/2] " Chen Pei
2026-08-19 9:37 ` bot+bpf-ci [this message]
2026-08-19 12:06 ` Chen Pei
2026-08-19 8:53 ` [PATCH bpf-next v2 2/2] selftests/bpf: Enable arena LDSX tests for riscv64 Chen Pei
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