[PATCH v2 1/2] Revert "drm/amd/display: Remove v_startup workaround for dcn3+"

[PATCH v2 1/2] Revert "drm/amd/display: Remove v_startup workaround for dcn3+"

[Hamza Mahfooz]

This reverts commit 3a31e8b89b7240d9a17ace8a1ed050bdcb560f9e.

We still need to call dcn20_adjust_freesync_v_startup() for older DCN3+
ASICs otherwise it can cause DP to HDMI 2.1 PCONs to fail to light up.

Cc: stable@vger.kernel.org
Link: https://gitlab.freedesktop.org/drm/amd/-/issues/2809
Signed-off-by: Hamza Mahfooz <hamza.mahfooz@amd.com>
---
 .../drm/amd/display/dc/dml/dcn20/dcn20_fpu.c  | 24 ++++---------------
 1 file changed, 4 insertions(+), 20 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c b/drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c
index 0989a0152ae8..1bfdf0271fdf 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c
@@ -1099,6 +1099,10 @@ void dcn20_calculate_dlg_params(struct dc *dc,
 		context->res_ctx.pipe_ctx[i].plane_res.bw.dppclk_khz =
 						pipes[pipe_idx].clks_cfg.dppclk_mhz * 1000;
 		context->res_ctx.pipe_ctx[i].pipe_dlg_param = pipes[pipe_idx].pipe.dest;
+		if (context->res_ctx.pipe_ctx[i].stream->adaptive_sync_infopacket.valid)
+			dcn20_adjust_freesync_v_startup(
+				&context->res_ctx.pipe_ctx[i].stream->timing,
+				&context->res_ctx.pipe_ctx[i].pipe_dlg_param.vstartup_start);
 
 		pipe_idx++;
 	}
@@ -1927,7 +1931,6 @@ static bool dcn20_validate_bandwidth_internal(struct dc *dc, struct dc_state *co
 	int vlevel = 0;
 	int pipe_split_from[MAX_PIPES];
 	int pipe_cnt = 0;
-	int i = 0;
 	display_e2e_pipe_params_st *pipes = kzalloc(dc->res_pool->pipe_count * sizeof(display_e2e_pipe_params_st), GFP_ATOMIC);
 	DC_LOGGER_INIT(dc->ctx->logger);
 
@@ -1951,15 +1954,6 @@ static bool dcn20_validate_bandwidth_internal(struct dc *dc, struct dc_state *co
 	dcn20_calculate_wm(dc, context, pipes, &pipe_cnt, pipe_split_from, vlevel, fast_validate);
 	dcn20_calculate_dlg_params(dc, context, pipes, pipe_cnt, vlevel);
 
-	for (i = 0; i < dc->res_pool->pipe_count; i++) {
-		if (!context->res_ctx.pipe_ctx[i].stream)
-			continue;
-		if (context->res_ctx.pipe_ctx[i].stream->adaptive_sync_infopacket.valid)
-			dcn20_adjust_freesync_v_startup(
-				&context->res_ctx.pipe_ctx[i].stream->timing,
-				&context->res_ctx.pipe_ctx[i].pipe_dlg_param.vstartup_start);
-	}
-
 	BW_VAL_TRACE_END_WATERMARKS();
 
 	goto validate_out;
@@ -2232,7 +2226,6 @@ bool dcn21_validate_bandwidth_fp(struct dc *dc,
 	int vlevel = 0;
 	int pipe_split_from[MAX_PIPES];
 	int pipe_cnt = 0;
-	int i = 0;
 	display_e2e_pipe_params_st *pipes = kzalloc(dc->res_pool->pipe_count * sizeof(display_e2e_pipe_params_st), GFP_ATOMIC);
 	DC_LOGGER_INIT(dc->ctx->logger);
 
@@ -2261,15 +2254,6 @@ bool dcn21_validate_bandwidth_fp(struct dc *dc,
 	dcn21_calculate_wm(dc, context, pipes, &pipe_cnt, pipe_split_from, vlevel, fast_validate);
 	dcn20_calculate_dlg_params(dc, context, pipes, pipe_cnt, vlevel);
 
-	for (i = 0; i < dc->res_pool->pipe_count; i++) {
-		if (!context->res_ctx.pipe_ctx[i].stream)
-			continue;
-		if (context->res_ctx.pipe_ctx[i].stream->adaptive_sync_infopacket.valid)
-			dcn20_adjust_freesync_v_startup(
-				&context->res_ctx.pipe_ctx[i].stream->timing,
-				&context->res_ctx.pipe_ctx[i].pipe_dlg_param.vstartup_start);
-	}
-
 	BW_VAL_TRACE_END_WATERMARKS();
 
 	goto validate_out;
-- 
2.41.0

[PATCH v2 2/2] drm/amd/display: limit the v_startup workaround for ASICs older than DCN3.1

[Hamza Mahfooz]

Since, calling dcn20_adjust_freesync_v_startup() on DCN3.1+ ASICs
can cause the display to flicker and underflow to occur we shouldn't
call it for them. So, ensure that the DCN version is less than
DCN_VERSION_3_1 before calling dcn20_adjust_freesync_v_startup().

Cc: stable@vger.kernel.org
Signed-off-by: Hamza Mahfooz <hamza.mahfooz@amd.com>
---
 drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c b/drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c
index 1bfdf0271fdf..a68fb45ed487 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c
@@ -1099,7 +1099,8 @@ void dcn20_calculate_dlg_params(struct dc *dc,
 		context->res_ctx.pipe_ctx[i].plane_res.bw.dppclk_khz =
 						pipes[pipe_idx].clks_cfg.dppclk_mhz * 1000;
 		context->res_ctx.pipe_ctx[i].pipe_dlg_param = pipes[pipe_idx].pipe.dest;
-		if (context->res_ctx.pipe_ctx[i].stream->adaptive_sync_infopacket.valid)
+		if (dc->ctx->dce_version < DCN_VERSION_3_1 &&
+		    context->res_ctx.pipe_ctx[i].stream->adaptive_sync_infopacket.valid)
 			dcn20_adjust_freesync_v_startup(
 				&context->res_ctx.pipe_ctx[i].stream->timing,
 				&context->res_ctx.pipe_ctx[i].pipe_dlg_param.vstartup_start);
-- 
2.41.0

Re: [PATCH v2 1/2] Revert "drm/amd/display: Remove v_startup workaround for dcn3+"

[Harry Wentland]

On 2023-08-31 15:44, Zuo, Jerry wrote:
> [AMD Official Use Only - General]
> 
> 
> Series is:
> 
> Reviewed-By: Fangzhi Zuo <jerry.zuo@amd.com>
> 

Reviewed-by: Harry Wentland <harry.wentland@amd.com>

Harry

> ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
> *发件人:* Mahfooz, Hamza <Hamza.Mahfooz@amd.com>
> *发送时间:* 星期四, 八月 31, 2023 3:39:04 下午
> *收件人:* amd-gfx@lists.freedesktop.org <amd-gfx@lists.freedesktop.org>
> *抄送:* Zuo, Jerry <Jerry.Zuo@amd.com>; Mahfooz, Hamza <Hamza.Mahfooz@amd.com>; stable@vger.kernel.org <stable@vger.kernel.org>; Wentland, Harry <Harry.Wentland@amd.com>; Li, Sun peng (Leo) <Sunpeng.Li@amd.com>; Siqueira, Rodrigo <Rodrigo.Siqueira@amd.com>; Deucher, Alexander <Alexander.Deucher@amd.com>; Koenig, Christian <Christian.Koenig@amd.com>; Pan, Xinhui <Xinhui.Pan@amd.com>; David Airlie <airlied@gmail.com>; Daniel Vetter <daniel@ffwll.ch>; Lei, Jun <Jun.Lei@amd.com>; Pillai, Aurabindo <Aurabindo.Pillai@amd.com>; Kazlauskas, Nicholas <Nicholas.Kazlauskas@amd.com>; Liu, Wenjing <Wenjing.Liu@amd.com>; Lee, Alvin <Alvin.Lee2@amd.com>; Kim, Sung joon <Sungjoon.Kim@amd.com>; Miess, Daniel <Daniel.Miess@amd.com>; Teeger, Gabe <Gabe.Teeger@amd.com>; dri-devel@lists.freedesktop.org <dri-devel@lists.freedesktop.org>; linux-kernel@vger.kernel.org <linux-kernel@vger.kernel.org>
> *主题:* [PATCH v2 1/2] Revert "drm/amd/display: Remove v_startup workaround for dcn3+"
> 
> This reverts commit 3a31e8b89b7240d9a17ace8a1ed050bdcb560f9e.
> 
> We still need to call dcn20_adjust_freesync_v_startup() for older DCN3+
> ASICs otherwise it can cause DP to HDMI 2.1 PCONs to fail to light up.
> 
> Cc: stable@vger.kernel.org
> Link: https://gitlab.freedesktop.org/drm/amd/-/issues/2809 <https://gitlab.freedesktop.org/drm/amd/-/issues/2809>
> Signed-off-by: Hamza Mahfooz <hamza.mahfooz@amd.com>
> ---
>  .../drm/amd/display/dc/dml/dcn20/dcn20_fpu.c  | 24 ++++---------------
>  1 file changed, 4 insertions(+), 20 deletions(-)
> 
> diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c b/drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c
> index 0989a0152ae8..1bfdf0271fdf 100644
> --- a/drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c
> +++ b/drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c
> @@ -1099,6 +1099,10 @@ void dcn20_calculate_dlg_params(struct dc *dc,
>                  context->res_ctx.pipe_ctx[i].plane_res.bw.dppclk_khz =
>                                                  pipes[pipe_idx].clks_cfg.dppclk_mhz * 1000;
>                  context->res_ctx.pipe_ctx[i].pipe_dlg_param = pipes[pipe_idx].pipe.dest;
> +               if (context->res_ctx.pipe_ctx[i].stream->adaptive_sync_infopacket.valid)
> +                       dcn20_adjust_freesync_v_startup(
> +                               &context->res_ctx.pipe_ctx[i].stream->timing,
> +                               &context->res_ctx.pipe_ctx[i].pipe_dlg_param.vstartup_start);
>  
>                  pipe_idx++;
>          }
> @@ -1927,7 +1931,6 @@ static bool dcn20_validate_bandwidth_internal(struct dc *dc, struct dc_state *co
>          int vlevel = 0;
>          int pipe_split_from[MAX_PIPES];
>          int pipe_cnt = 0;
> -       int i = 0;
>          display_e2e_pipe_params_st *pipes = kzalloc(dc->res_pool->pipe_count * sizeof(display_e2e_pipe_params_st), GFP_ATOMIC);
>          DC_LOGGER_INIT(dc->ctx->logger);
>  
> @@ -1951,15 +1954,6 @@ static bool dcn20_validate_bandwidth_internal(struct dc *dc, struct dc_state *co
>          dcn20_calculate_wm(dc, context, pipes, &pipe_cnt, pipe_split_from, vlevel, fast_validate);
>          dcn20_calculate_dlg_params(dc, context, pipes, pipe_cnt, vlevel);
>  
> -       for (i = 0; i < dc->res_pool->pipe_count; i++) {
> -               if (!context->res_ctx.pipe_ctx[i].stream)
> -                       continue;
> -               if (context->res_ctx.pipe_ctx[i].stream->adaptive_sync_infopacket.valid)
> -                       dcn20_adjust_freesync_v_startup(
> -                               &context->res_ctx.pipe_ctx[i].stream->timing,
> -                               &context->res_ctx.pipe_ctx[i].pipe_dlg_param.vstartup_start);
> -       }
> -
>          BW_VAL_TRACE_END_WATERMARKS();
>  
>          goto validate_out;
> @@ -2232,7 +2226,6 @@ bool dcn21_validate_bandwidth_fp(struct dc *dc,
>          int vlevel = 0;
>          int pipe_split_from[MAX_PIPES];
>          int pipe_cnt = 0;
> -       int i = 0;
>          display_e2e_pipe_params_st *pipes = kzalloc(dc->res_pool->pipe_count * sizeof(display_e2e_pipe_params_st), GFP_ATOMIC);
>          DC_LOGGER_INIT(dc->ctx->logger);
>  
> @@ -2261,15 +2254,6 @@ bool dcn21_validate_bandwidth_fp(struct dc *dc,
>          dcn21_calculate_wm(dc, context, pipes, &pipe_cnt, pipe_split_from, vlevel, fast_validate);
>          dcn20_calculate_dlg_params(dc, context, pipes, pipe_cnt, vlevel);
>  
> -       for (i = 0; i < dc->res_pool->pipe_count; i++) {
> -               if (!context->res_ctx.pipe_ctx[i].stream)
> -                       continue;
> -               if (context->res_ctx.pipe_ctx[i].stream->adaptive_sync_infopacket.valid)
> -                       dcn20_adjust_freesync_v_startup(
> -                               &context->res_ctx.pipe_ctx[i].stream->timing,
> -                               &context->res_ctx.pipe_ctx[i].pipe_dlg_param.vstartup_start);
> -       }
> -
>          BW_VAL_TRACE_END_WATERMARKS();
>  
>          goto validate_out;
> -- 
> 2.41.0
> 
>