[PATCH 0/2] clk: samsung: Update PLL locktime and samsung function

[PATCH 0/2] clk: samsung: Update PLL locktime and samsung function

[Varada Pavani]

This patch series updates samsung clock driver with common samsung
CCF function and defines locktime value for PLL142XX controller.

Varada Pavani (2):
  clk: samsung: Use samsung CCF common function
	This patch is missed in this series https://patchwork.kernel.org/project/linux-clk/cover/20240926144513.71349-1-v.pavani@samsung.com/ hence posting again.
  clk: samsung: Fixes PLL locktime for PLL142XX used on FSD platfom
	Got review comment in this patch will address in next patch series.

 drivers/clk/samsung/clk-exynos4.c | 78 +++++++++++++++++--------------
 drivers/clk/samsung/clk-pll.c     |  7 ++-
 2 files changed, 50 insertions(+), 35 deletions(-)

-- 
2.17.1

[PATCH 1/2] clk: samsung: Use samsung CCF common function

[Varada Pavani]

Use samsung CCF function which registers multiple clock providers using
single function call samsung_cmu_register_clocks().

Signed-off-by: Varada Pavani <v.pavani@samsung.com>
---
 drivers/clk/samsung/clk-exynos4.c | 78 +++++++++++++++++--------------
 1 file changed, 44 insertions(+), 34 deletions(-)

diff --git a/drivers/clk/samsung/clk-exynos4.c b/drivers/clk/samsung/clk-exynos4.c
index 28945b6b0ee1..31cb85330549 100644
--- a/drivers/clk/samsung/clk-exynos4.c
+++ b/drivers/clk/samsung/clk-exynos4.c
@@ -1269,6 +1269,45 @@ static const struct samsung_cpu_clock exynos4412_cpu_clks[] __initconst = {
 		CPUCLK_LAYOUT_E4210, e4412_armclk_d),
 };
 
+static const struct samsung_cmu_info cmu_info_exynos4 __initconst = {
+	.mux_clks		= exynos4_mux_clks,
+	.nr_mux_clks		= ARRAY_SIZE(exynos4_mux_clks),
+	.div_clks		= exynos4_div_clks,
+	.nr_div_clks		= ARRAY_SIZE(exynos4_div_clks),
+	.gate_clks		= exynos4_gate_clks,
+	.nr_gate_clks		= ARRAY_SIZE(exynos4_gate_clks),
+	.fixed_factor_clks	= exynos4_fixed_factor_clks,
+	.nr_fixed_factor_clks	= ARRAY_SIZE(exynos4_fixed_factor_clks),
+	.fixed_clks	= exynos4_fixed_rate_clks,
+	.nr_fixed_clks	= ARRAY_SIZE(exynos4_fixed_rate_clks),
+};
+
+static const struct samsung_cmu_info cmu_info_exynos4210 __initconst = {
+	.mux_clks		= exynos4210_mux_clks,
+	.nr_mux_clks		= ARRAY_SIZE(exynos4210_mux_clks),
+	.div_clks		= exynos4210_div_clks,
+	.nr_div_clks		= ARRAY_SIZE(exynos4210_div_clks),
+	.gate_clks		= exynos4210_gate_clks,
+	.nr_gate_clks		= ARRAY_SIZE(exynos4210_gate_clks),
+	.fixed_factor_clks	= exynos4210_fixed_factor_clks,
+	.nr_fixed_factor_clks	= ARRAY_SIZE(exynos4210_fixed_factor_clks),
+	.fixed_clks	= exynos4210_fixed_rate_clks,
+	.nr_fixed_clks	= ARRAY_SIZE(exynos4210_fixed_rate_clks),
+	.cpu_clks		= exynos4210_cpu_clks,
+	.nr_cpu_clks		= ARRAY_SIZE(exynos4210_cpu_clks),
+};
+
+static const struct samsung_cmu_info cmu_info_exynos4x12 __initconst = {
+	.mux_clks		= exynos4x12_mux_clks,
+	.nr_mux_clks		= ARRAY_SIZE(exynos4x12_mux_clks),
+	.div_clks		= exynos4x12_div_clks,
+	.nr_div_clks		= ARRAY_SIZE(exynos4x12_div_clks),
+	.gate_clks		= exynos4x12_gate_clks,
+	.nr_gate_clks		= ARRAY_SIZE(exynos4x12_gate_clks),
+	.fixed_factor_clks	= exynos4x12_fixed_factor_clks,
+	.nr_fixed_factor_clks	= ARRAY_SIZE(exynos4x12_fixed_factor_clks),
+};
+
 /* register exynos4 clocks */
 static void __init exynos4_clk_init(struct device_node *np,
 				    enum exynos4_soc soc)
@@ -1322,41 +1361,12 @@ static void __init exynos4_clk_init(struct device_node *np,
 					ARRAY_SIZE(exynos4x12_plls));
 	}
 
-	samsung_clk_register_fixed_rate(ctx, exynos4_fixed_rate_clks,
-			ARRAY_SIZE(exynos4_fixed_rate_clks));
-	samsung_clk_register_mux(ctx, exynos4_mux_clks,
-			ARRAY_SIZE(exynos4_mux_clks));
-	samsung_clk_register_div(ctx, exynos4_div_clks,
-			ARRAY_SIZE(exynos4_div_clks));
-	samsung_clk_register_gate(ctx, exynos4_gate_clks,
-			ARRAY_SIZE(exynos4_gate_clks));
-	samsung_clk_register_fixed_factor(ctx, exynos4_fixed_factor_clks,
-			ARRAY_SIZE(exynos4_fixed_factor_clks));
+	samsung_cmu_register_clocks(ctx, &cmu_info_exynos4);
 
-	if (exynos4_soc == EXYNOS4210) {
-		samsung_clk_register_fixed_rate(ctx, exynos4210_fixed_rate_clks,
-			ARRAY_SIZE(exynos4210_fixed_rate_clks));
-		samsung_clk_register_mux(ctx, exynos4210_mux_clks,
-			ARRAY_SIZE(exynos4210_mux_clks));
-		samsung_clk_register_div(ctx, exynos4210_div_clks,
-			ARRAY_SIZE(exynos4210_div_clks));
-		samsung_clk_register_gate(ctx, exynos4210_gate_clks,
-			ARRAY_SIZE(exynos4210_gate_clks));
-		samsung_clk_register_fixed_factor(ctx,
-			exynos4210_fixed_factor_clks,
-			ARRAY_SIZE(exynos4210_fixed_factor_clks));
-		samsung_clk_register_cpu(ctx, exynos4210_cpu_clks,
-				ARRAY_SIZE(exynos4210_cpu_clks));
-	} else {
-		samsung_clk_register_mux(ctx, exynos4x12_mux_clks,
-			ARRAY_SIZE(exynos4x12_mux_clks));
-		samsung_clk_register_div(ctx, exynos4x12_div_clks,
-			ARRAY_SIZE(exynos4x12_div_clks));
-		samsung_clk_register_gate(ctx, exynos4x12_gate_clks,
-			ARRAY_SIZE(exynos4x12_gate_clks));
-		samsung_clk_register_fixed_factor(ctx,
-			exynos4x12_fixed_factor_clks,
-			ARRAY_SIZE(exynos4x12_fixed_factor_clks));
+	if (exynos4_soc == EXYNOS4210)
+		samsung_cmu_register_clocks(ctx, &cmu_info_exynos4210);
+	else {
+		samsung_cmu_register_clocks(ctx, &cmu_info_exynos4x12);
 		if (soc == EXYNOS4412)
 			samsung_clk_register_cpu(ctx, exynos4412_cpu_clks,
 					ARRAY_SIZE(exynos4412_cpu_clks));
-- 
2.17.1

[PATCH 2/2] clk: samsung: Fixes PLL locktime for PLL142XX used on FSD platfom

[Varada Pavani]

Add PLL locktime for PLL142XX controller.

Fixes: 4f346005aaed ("clk: samsung: fsd: Add initial clock support")
Cc: stable@vger.kernel.org
Signed-off-by: Varada Pavani <v.pavani@samsung.com>
---
 drivers/clk/samsung/clk-pll.c | 7 ++++++-
 1 file changed, 6 insertions(+), 1 deletion(-)

diff --git a/drivers/clk/samsung/clk-pll.c b/drivers/clk/samsung/clk-pll.c
index 4be879ab917e..d4c5ae20de4f 100644
--- a/drivers/clk/samsung/clk-pll.c
+++ b/drivers/clk/samsung/clk-pll.c
@@ -206,6 +206,7 @@ static const struct clk_ops samsung_pll3000_clk_ops = {
  */
 /* Maximum lock time can be 270 * PDIV cycles */
 #define PLL35XX_LOCK_FACTOR	(270)
+#define PLL142XX_LOCK_FACTOR	(150)
 
 #define PLL35XX_MDIV_MASK       (0x3FF)
 #define PLL35XX_PDIV_MASK       (0x3F)
@@ -272,7 +273,11 @@ static int samsung_pll35xx_set_rate(struct clk_hw *hw, unsigned long drate,
 	}
 
 	/* Set PLL lock time. */
-	writel_relaxed(rate->pdiv * PLL35XX_LOCK_FACTOR,
+	if (pll->type == pll_142xx)
+		writel_relaxed(rate->pdiv * PLL142XX_LOCK_FACTOR,
+			pll->lock_reg);
+	else
+		writel_relaxed(rate->pdiv * PLL35XX_LOCK_FACTOR,
 			pll->lock_reg);
 
 	/* Change PLL PMS values */
-- 
2.17.1

Re: [PATCH 2/2] clk: samsung: Fixes PLL locktime for PLL142XX used on FSD platfom

[Krzysztof Kozlowski]

On 30/09/2024 13:18, Varada Pavani wrote:
> Add PLL locktime for PLL142XX controller.
> 

So you send the same? Or something new? Please provide proper changelog
and mark patches as v2/v3 or RESEND.

But anyway this cannot be RESEND as I explicitly asked for fixing.

<form letter>
This is a friendly reminder during the review process.

It seems my or other reviewer's previous comments were not fully
addressed. Maybe the feedback got lost between the quotes, maybe you
just forgot to apply it. Please go back to the previous discussion and
either implement all requested changes or keep discussing them.

Thank you.
</form letter>

Best regards,
Krzysztof

RE: [PATCH 2/2] clk: samsung: Fixes PLL locktime for PLL142XX used on FSD platfom

[Varada Pavani]

> -----Original Message-----
> From: Krzysztof Kozlowski [mailto:krzk@kernel.org]
> Sent: 30 September 2024 18:05
> To: Varada Pavani <v.pavani@samsung.com>; s.nawrocki@samsung.com;
> cw00.choi@samsung.com; alim.akhtar@samsung.com;
> mturquette@baylibre.com; sboyd@kernel.org; linux-samsung-
> soc@vger.kernel.org; linux-clk@vger.kernel.org; linux-arm-
> kernel@lists.infradead.org; linux-kernel@vger.kernel.org
> Cc: aswani.reddy@samsung.com; pankaj.dubey@samsung.com;
> gost.dev@samsung.com; stable@vger.kernel.org
> Subject: Re: [PATCH 2/2] clk: samsung: Fixes PLL locktime for PLL142XX used
> on FSD platfom
> 
> On 30/09/2024 13:18, Varada Pavani wrote:
> > Add PLL locktime for PLL142XX controller.
> >
> 
> So you send the same? Or something new? Please provide proper changelog
> and mark patches as v2/v3 or RESEND.
> 
> But anyway this cannot be RESEND as I explicitly asked for fixing.
> 
> <form letter>
> This is a friendly reminder during the review process.
> 
> It seems my or other reviewer's previous comments were not fully
> addressed. Maybe the feedback got lost between the quotes, maybe you
> just forgot to apply it. Please go back to the previous discussion and either
> implement all requested changes or keep discussing them.
> 
> Thank you.
> </form letter>
> 
> Best regards,
> Krzysztof

Sorry, have sent the same patch again. As I need to post one patch alone which got
missed due to internal technical issue. Next time onwards will make sure to mark the
patches as V2/V3 or RESEND accordingly.

Regards,
Varada Pavani

[PATCH 0/2] clk: samsung: Update PLL locktime and samsung function

[Varada Pavani]

This patch series updates samsung clock driver with common samsung
CCF function and defines locktime value for PLL142XX controller.

Varada Pavani (2):
  clk: samsung: Use samsung CCF common function
  clk: samsung: Fixes PLL locktime for PLL142XX used on FSD platfom

 drivers/clk/samsung/clk-exynos4.c | 78 +++++++++++++++++--------------
 drivers/clk/samsung/clk-pll.c     |  7 ++-
 2 files changed, 50 insertions(+), 35 deletions(-)

-- 
2.17.1

[PATCH 2/2] clk: samsung: Fixes PLL locktime for PLL142XX used on FSD platfom

[Varada Pavani]

Add PLL locktime for PLL142XX controller.

Fixes: 4f346005aaed ("clk: samsung: fsd: Add initial clock support")
Cc: stable@vger.kernel.org
Signed-off-by: Varada Pavani <v.pavani@samsung.com>
---
 drivers/clk/samsung/clk-pll.c | 7 ++++++-
 1 file changed, 6 insertions(+), 1 deletion(-)

diff --git a/drivers/clk/samsung/clk-pll.c b/drivers/clk/samsung/clk-pll.c
index 4be879ab917e..d4c5ae20de4f 100644
--- a/drivers/clk/samsung/clk-pll.c
+++ b/drivers/clk/samsung/clk-pll.c
@@ -206,6 +206,7 @@ static const struct clk_ops samsung_pll3000_clk_ops = {
  */
 /* Maximum lock time can be 270 * PDIV cycles */
 #define PLL35XX_LOCK_FACTOR	(270)
+#define PLL142XX_LOCK_FACTOR	(150)
 
 #define PLL35XX_MDIV_MASK       (0x3FF)
 #define PLL35XX_PDIV_MASK       (0x3F)
@@ -272,7 +273,11 @@ static int samsung_pll35xx_set_rate(struct clk_hw *hw, unsigned long drate,
 	}
 
 	/* Set PLL lock time. */
-	writel_relaxed(rate->pdiv * PLL35XX_LOCK_FACTOR,
+	if (pll->type == pll_142xx)
+		writel_relaxed(rate->pdiv * PLL142XX_LOCK_FACTOR,
+			pll->lock_reg);
+	else
+		writel_relaxed(rate->pdiv * PLL35XX_LOCK_FACTOR,
 			pll->lock_reg);
 
 	/* Change PLL PMS values */
-- 
2.17.1

Re: [PATCH 2/2] clk: samsung: Fixes PLL locktime for PLL142XX used on FSD platfom

[Krzysztof Kozlowski]

On 26/09/2024 16:45, Varada Pavani wrote:
> Add PLL locktime for PLL142XX controller.

You marked it as fixes. Please describe the observable bug and its
impact. See submitting patches and stable kernel rules.

> 
> Fixes: 4f346005aaed ("clk: samsung: fsd: Add initial clock support")
> Cc: stable@vger.kernel.org
> Signed-off-by: Varada Pavani <v.pavani@samsung.com>
> ---
Best regards,
Krzysztof

RE: [PATCH 2/2] clk: samsung: Fixes PLL locktime for PLL142XX used on FSD platfom

[Varada Pavani]

> -----Original Message-----
> From: Krzysztof Kozlowski [mailto:krzk@kernel.org]
> Sent: 30 September 2024 16:07
> To: Varada Pavani <v.pavani@samsung.com>; aswani.reddy@samsung.com;
> pankaj.dubey@samsung.com; s.nawrocki@samsung.com;
> cw00.choi@samsung.com; alim.akhtar@samsung.com;
> mturquette@baylibre.com; sboyd@kernel.org; linux-samsung-
> soc@vger.kernel.org; linux-clk@vger.kernel.org; linux-arm-
> kernel@lists.infradead.org; linux-kernel@vger.kernel.org
> Cc: gost.dev@samsung.com; stable@vger.kernel.org
> Subject: Re: [PATCH 2/2] clk: samsung: Fixes PLL locktime for PLL142XX used
> on FSD platfom
> 
> On 26/09/2024 16:45, Varada Pavani wrote:
> > Add PLL locktime for PLL142XX controller.
> 
> You marked it as fixes. Please describe the observable bug and its impact.
> See submitting patches and stable kernel rules.
> 

We marked it fixes because there is a software bug.  Both PLL142XX and
PLL35XX have same configurations with only change in locktime period
which is 150*PDIV . Hence updated locktime as per the defined spec.
Will update this information in the commit message and push V2 version.

Regards,
Varada Pavani

> >
> > Fixes: 4f346005aaed ("clk: samsung: fsd: Add initial clock support")
> > Cc: stable@vger.kernel.org
> > Signed-off-by: Varada Pavani <v.pavani@samsung.com>
> > ---
> Best regards,
> Krzysztof