Re: [PATCH v2 5/9] MIPS: Ingenic: Update Ingenic XBurst implementation IDs

[Paul Cercueil <paul@crapouillou.net>]

Hi Nikolaus,

Le jeudi 12 novembre 2026 à 09:10 +0100, H. Nikolaus Schaller a écrit :
> Add PRID implementation constants for Ingenic XBurst and XBurst II
> processors and handle the corresponding implementation IDs in
> cpu_probe_ingenic().
> 
> The PRID table is updated based on Programming Manuals and hardware tests:
> - jz4780: 0x3ee1024f (confirmed on CI20 board)
> - x1000:  0x2ed1024f (unconfirmed)
> - x1600:  0x00d00000 (confirmed on LX16 board)
> - X1830:  0x00d00100 (unconfirmed)
> - X2000:  0x00132000 (read out from LX20 board)
> - X2600:  0x001320xx (confirmed 0x00132000 on LX26 board)
> 
> Additionally, clean up extra spaces in the comments for
> PRID_IMP_XBURST_REV2 and PRID_IMP_XBURST2.
> 
> Distinguish XBurst1 implementations with different SIMD ISA revisions
> and identify XBurst II processors using PRID_IMP_XBURST2.
> The XBurst II classification follows the Ingenic vendor kernel.
> 
> Keep the existing writecombine handling unchanged, since no
> independent evidence justifies changing the cache attribute for
> XBurst II.
> 
> Public references:
> - Ingenic Community, public SoC datasheets and programming manuals:
>   https://github.com/Ingenic-community/datasheets/tree/main/X
>   Includes the X1600 programming manual (X1600_PM_20220117.pdf)
>   and documentation for other X-series SoCs, including X1000,
>   X1830 and X2000.
> - Ingenic, XBurst1 CPU Core Programming Manual:
>   https://cdn.hackaday.io/files/1855627939084608/XBurst1_Core_PM.pdf
>   Documents the XBurst1 core architecture and CP0 configuration.
> - Ingenic, XBurst Instruction Set Architecture Programming Manual:
>   https://www.setphaserstostun.org/ci20/X1000_M200_XBurst_ISA_MXU_PM.pdf
>   Documents the original XBurst SIMD instruction set.
> - Ingenic, XBurst2 CPU Core Programming Manual:
>   https://www.manualslib.com/manual/2646351/Ingenic-Xburst-2-Cpu-Core.html
>   Documents the XBurst2 core architecture.
> - Ingenic, MIPS-LINUX toolchain R6.0.0 release notes:
>   https://www.ingenic.com.cn/news-detail/nid-343.html
>   Distinguishes MSA, MXA and MXU/MXU2 support in the toolchain.
> - Ingenic, MIPS-LINUX toolchain R6.2.1 release notes:
>   https://www.ingenic.com.cn/news-detail/nid-348.html
>   Documents MXU3 support and identifies X2000 as an MSA target.
> 
> The public references document the available CPU, SoC and ISA
> information. The PRID implementation handling follows the Ingenic
> vendor kernel.
> 
> AI assistance: ChatGPT was used to help review the PRID definitions,
> compare the Ingenic vendor implementation with the upstream code,
> and draft the commit message with public references. The code changes,
> hardware observations, and final patch were reviewed by the authors.
> 
> Co-developed-by: Paul Boddie <paul@boddie.org.uk>
> Signed-off-by: Paul Boddie <paul@boddie.org.uk>
> Signed-off-by: H. Nikolaus Schaller <hns@goldelico.com>
> ---
> 
> Notes:
>     Changes in V2:
>     - removed the PRID_IMP_XBURST2_R2 definition and hints for an x2100 as
>       there is no public reference
>     - merged into single commit changing the PRID definitions and code
>     - reviewed details and rewrote commit message
>     
>     Open Issue:
>     Olivier Louvignes <olivier@mgcrea.io> pointed out that he has
>     simply reused the definition of the X1830 for the X1600. This
>     sets c->writecombine differently (_CACHE_CACHABLE_WA) from
>     _CACHE_UNCACHED_ACCELERATED as we do here.
>     Both settings appear to work but it needs expert comment which
>     is the right/better one.
> 
>  arch/mips/include/asm/cpu.h  | 9 +++++----
>  arch/mips/kernel/cpu-probe.c | 7 +++++++
>  2 files changed, 12 insertions(+), 4 deletions(-)
> 
> diff --git a/arch/mips/include/asm/cpu.h b/arch/mips/include/asm/cpu.h
> index add26f08e8029..79fd9a0747cf2 100644
> --- a/arch/mips/include/asm/cpu.h
> +++ b/arch/mips/include/asm/cpu.h
> @@ -47,7 +47,7 @@
>  #define PRID_COMP_CAVIUM	0x0d0000
>  #define PRID_COMP_LOONGSON	0x140000
>  #define PRID_COMP_INGENIC_13	0x130000	/* X2000, X2100 */
> -#define PRID_COMP_INGENIC_D0	0xd00000	/* JZ4730, JZ4740, JZ4750,
> JZ4755, JZ4760, X1830 */
> +#define PRID_COMP_INGENIC_D0	0xd00000	/* JZ4730, JZ4740, JZ4750,
> JZ4755, JZ4760, X1830, X1600 */
>  #define PRID_COMP_INGENIC_D1	0xd10000	/* JZ4770, JZ4775, X1000 */
>  #define PRID_COMP_INGENIC_E1	0xe10000	/* JZ4780 */
>  
> @@ -186,9 +186,10 @@
>   * These are the PRID's for when 23:16 == PRID_COMP_INGENIC_*
>   */
>  
> -#define PRID_IMP_XBURST_REV1	0x0200	/* XBurst®1 with MXU1.0/MXU1.1 SIMD
> ISA	*/
> -#define PRID_IMP_XBURST_REV2	0x0100	/* XBurst®1 with MXU2.0 SIMD
> ISA		*/
> -#define PRID_IMP_XBURST2		0x2000	/* XBurst®2 with MXU2.1 SIMD
> ISA		*/
> +#define PRID_IMP_XBURST		0x0000	/* XBurst1 */
> +#define PRID_IMP_XBURST_REV1	0x0200	/* XBurst1 with MXU1.0/MXU1.1 SIMD
> ISA */
> +#define PRID_IMP_XBURST_REV2	0x0100	/* XBurst1 with MXU2.0 SIMD ISA */
> +#define PRID_IMP_XBURST2	0x2000	/* XBurst2 with MXU2.1 SIMD ISA */
>  
>  /*
>   * These are the PRID's for when 23:16 == PRID_COMP_NETLOGIC
> diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c
> index 489612ed9d498..69b68d00b66f7 100644
> --- a/arch/mips/kernel/cpu-probe.c
> +++ b/arch/mips/kernel/cpu-probe.c
> @@ -1768,6 +1768,13 @@ static inline void cpu_probe_ingenic(struct
> cpuinfo_mips *c, unsigned int cpu)
>  
>  	switch (c->processor_id & PRID_IMP_MASK) {
>  
> +	/* XBurst®1 with ISA */
> +	case PRID_IMP_XBURST:
> +		c->cputype = CPU_XBURST;
> +		c->writecombine = _CACHE_UNCACHED_ACCELERATED;
> +		__cpu_name[cpu] = "Ingenic XBurst";
> +		break;

What SoCs actually use PRID_IMP_XBURST? The JZ4730?

If it's really used somewhere, you'll also need to add a compatible string for
it in Documentation/devicetree/bindings/mips/cpus.yaml. I guess just
"ingenic,xburst".

Cheers,
-Paul