* [PATCH v2 0/1] ARM: dts: draeger: Add socfpga devicetree for Draeger's M48 board.
@ 2026-09-08 11:09 Petko Manolov
2026-09-08 11:10 ` [PATCH v2 1/1] " Petko Manolov
0 siblings, 1 reply; 8+ messages in thread
From: Petko Manolov @ 2026-09-08 11:09 UTC (permalink / raw)
To: linux-kernel; +Cc: devicetree, robh, krzk+dt, conor+dt, dinguyen, Petko Manolov
Adding the device trees for “Dräger M48 on NXP i.MX6 (Q) and Intel/Altera
SoCFPGA Cyclone V” board variant. It has both (the SoC and FPGA) on the same
carrier and they are cross-monitoring each other.
This is the SoCFPGA devicetree part.
Petko Manolov (1):
ARM: dts: draeger: Add socfpga devicetree for Draeger's M48 board.
.../devicetree/bindings/arm/altera.yaml | 1 +
arch/arm/boot/dts/intel/socfpga/Makefile | 1 +
.../socfpga/socfpga_cyclone5_draeger_m48.dts | 130 ++++++++++++++++++
3 files changed, 132 insertions(+)
create mode 100644 arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_draeger_m48.dts
--
2.47.3
^ permalink raw reply [flat|nested] 8+ messages in thread
* [PATCH v2 1/1] ARM: dts: draeger: Add socfpga devicetree for Draeger's M48 board.
2026-09-08 11:09 [PATCH v2 0/1] ARM: dts: draeger: Add socfpga devicetree for Draeger's M48 board Petko Manolov
@ 2026-09-08 11:10 ` Petko Manolov
2026-09-09 6:36 ` Krzysztof Kozlowski
0 siblings, 1 reply; 8+ messages in thread
From: Petko Manolov @ 2026-09-08 11:10 UTC (permalink / raw)
To: linux-kernel; +Cc: devicetree, robh, krzk+dt, conor+dt, dinguyen, Petko Manolov
Signed-off-by: Petko Manolov <petko.manolov@konsulko.com>
---
.../devicetree/bindings/arm/altera.yaml | 1 +
arch/arm/boot/dts/intel/socfpga/Makefile | 1 +
.../socfpga/socfpga_cyclone5_draeger_m48.dts | 130 ++++++++++++++++++
3 files changed, 132 insertions(+)
create mode 100644 arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_draeger_m48.dts
diff --git a/Documentation/devicetree/bindings/arm/altera.yaml b/Documentation/devicetree/bindings/arm/altera.yaml
index 3030cf46fe74..8ed1ba733510 100644
--- a/Documentation/devicetree/bindings/arm/altera.yaml
+++ b/Documentation/devicetree/bindings/arm/altera.yaml
@@ -47,6 +47,7 @@ properties:
- enum:
- altr,socfpga-cyclone5-socdk
- denx,mcvevk
+ - draeger,M48
- ebv,socrates
- macnica,sodia
- novtech,chameleon96
diff --git a/arch/arm/boot/dts/intel/socfpga/Makefile b/arch/arm/boot/dts/intel/socfpga/Makefile
index 8df0976da01c..cdcea11abdfa 100644
--- a/arch/arm/boot/dts/intel/socfpga/Makefile
+++ b/arch/arm/boot/dts/intel/socfpga/Makefile
@@ -11,6 +11,7 @@ dtb-$(CONFIG_ARCH_INTEL_SOCFPGA) += \
socfpga_arria10_mercury_aa1_st1_emmc.dtb \
socfpga_arria10_mercury_aa1_st1_qspi.dtb \
socfpga_arria10_mercury_aa1_st1_sdmmc.dtb \
+ socfpga_cyclone5_draeger_m48.dtb \
socfpga_cyclone5_mercury_sa1_pe1_emmc.dtb \
socfpga_cyclone5_mercury_sa1_pe1_qspi.dtb \
socfpga_cyclone5_mercury_sa1_pe1_sdmmc.dtb \
diff --git a/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_draeger_m48.dts b/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_draeger_m48.dts
new file mode 100644
index 000000000000..423c76cd1d4a
--- /dev/null
+++ b/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_draeger_m48.dts
@@ -0,0 +1,130 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2020 Draeger and Licensors, info@draeger.com
+ */
+#include "socfpga_cyclone5.dtsi"
+
+/ {
+ model = "Draeger M48 Cyclone V SoC";
+ compatible = "draeger,M48", "altr,socfpga-cyclone5", "altr,socfpga";
+
+ chosen {
+ bootargs = "earlyprintk";
+ stdout-path = "serial0:115200n8";
+ };
+
+ memory@0 {
+ name = "memory";
+ device_type = "memory";
+ reg = <0x0 0x40000000>;
+
+ /* 1GB */
+ };
+
+ aliases {
+ /* this allow the ethaddr uboot environmnet variable contents
+ * to be added to the gmac0 device tree blob.
+ */
+ ethernet0 = &gmac0;
+ };
+
+ soc {
+ gpio3: gpio@ff202000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "snps,dw-apb-gpio";
+ reg = <0xff202000 0x20>;
+ status = "okay";
+
+ portd: gpio-controller@0 {
+ compatible = "snps,dw-apb-gpio-port";
+ gpio-controller;
+ #gpio-cells = <2>;
+ snps,nr-gpios = <2>;
+ reg = <0>;
+ bank-name = "SYNC_I";
+ };
+ };
+
+ gpio4: gpio@ff202020 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "snps,dw-apb-gpio";
+ reg = <0xff202020 0x20>;
+ status = "okay";
+
+ porte: gpio-controller@0 {
+ compatible = "snps,dw-apb-gpio-port";
+ gpio-controller;
+ #gpio-cells = <2>;
+ snps,nr-gpios = <2>;
+ reg = <0>;
+ bank-name = "SYNC_O";
+ };
+ };
+ };
+};
+
+&gmac0 {
+ status = "okay";
+ phy-mode = "rgmii-id";
+ rxc-skew-ps = <1860>;
+ rxd0-skew-ps = <0>;
+ rxd1-skew-ps = <0>;
+ rxd2-skew-ps = <0>;
+ rxd3-skew-ps = <0>;
+ rxdv-skew-ps = <0>;
+ txc-skew-ps = <900>;
+ txd0-skew-ps = <0>;
+ txd1-skew-ps = <0>;
+ txd2-skew-ps = <0>;
+ txd3-skew-ps = <0>;
+ txen-skew-ps = <0>;
+};
+
+&gpio0 {
+ status = "okay";
+};
+
+&gpio1 {
+ status = "okay";
+};
+
+&gpio2 {
+ status = "okay";
+};
+
+&i2c0 {
+ status = "okay";
+ clock-frequency = <100000>;
+
+ eeprom_mac: eeprom@50 {
+ compatible = "atmel,24c08";
+ reg = <0x50>;
+ pagesize = <16>;
+ };
+};
+
+&mmc0 {
+ status = "okay";
+};
+
+&qspi {
+ status = "okay";
+
+ flash: flash@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "micron,n25q256a", "jedec,spi-nor";
+ reg = <0>;
+
+ /* chip select */
+ spi-max-frequency = <100000000>;
+ m25p,fast-read;
+ cdns,read-delay = <4>;
+ cdns,tshsl-ns = <50>;
+ cdns,tsd2d-ns = <50>;
+ cdns,tchsh-ns = <4>;
+ cdns,tslch-ns = <4>;
+ };
+};
--
2.47.3
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH v2 1/1] ARM: dts: draeger: Add socfpga devicetree for Draeger's M48 board.
2026-09-08 11:10 ` [PATCH v2 1/1] " Petko Manolov
@ 2026-09-09 6:36 ` Krzysztof Kozlowski
2026-09-09 6:50 ` Petko Manolov
2026-09-09 10:07 ` Petko Manolov
0 siblings, 2 replies; 8+ messages in thread
From: Krzysztof Kozlowski @ 2026-09-09 6:36 UTC (permalink / raw)
To: Petko Manolov, linux-kernel; +Cc: devicetree, robh, krzk+dt, conor+dt, dinguyen
On 08/09/2026 13:10, Petko Manolov wrote:
> Signed-off-by: Petko Manolov <petko.manolov@konsulko.com>
Please run scripts/checkpatch.pl on the patches and fix reported
warnings. After that, run also 'scripts/checkpatch.pl --strict' on the
patches and (probably) fix more warnings. Some warnings can be ignored,
especially from --strict run, but the code here looks like it needs a
fix. Feel free to get in touch if the warning is not clear.
> ---
> .../devicetree/bindings/arm/altera.yaml | 1 +
> arch/arm/boot/dts/intel/socfpga/Makefile | 1 +
> .../socfpga/socfpga_cyclone5_draeger_m48.dts | 130 ++++++++++++++++++
> 3 files changed, 132 insertions(+)
> create mode 100644 arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_draeger_m48.dts
>
> diff --git a/Documentation/devicetree/bindings/arm/altera.yaml b/Documentation/devicetree/bindings/arm/altera.yaml
> index 3030cf46fe74..8ed1ba733510 100644
> --- a/Documentation/devicetree/bindings/arm/altera.yaml
> +++ b/Documentation/devicetree/bindings/arm/altera.yaml
Same comments. Binding should not be part of other patches.
> @@ -47,6 +47,7 @@ properties:
> - enum:
> - altr,socfpga-cyclone5-socdk
> - denx,mcvevk
> + - draeger,M48
> - ebv,socrates
> - macnica,sodia
> - novtech,chameleon96
> diff --git a/arch/arm/boot/dts/intel/socfpga/Makefile b/arch/arm/boot/dts/intel/socfpga/Makefile
> index 8df0976da01c..cdcea11abdfa 100644
> --- a/arch/arm/boot/dts/intel/socfpga/Makefile
> +++ b/arch/arm/boot/dts/intel/socfpga/Makefile
> @@ -11,6 +11,7 @@ dtb-$(CONFIG_ARCH_INTEL_SOCFPGA) += \
> socfpga_arria10_mercury_aa1_st1_emmc.dtb \
> socfpga_arria10_mercury_aa1_st1_qspi.dtb \
> socfpga_arria10_mercury_aa1_st1_sdmmc.dtb \
> + socfpga_cyclone5_draeger_m48.dtb \
> socfpga_cyclone5_mercury_sa1_pe1_emmc.dtb \
> socfpga_cyclone5_mercury_sa1_pe1_qspi.dtb \
> socfpga_cyclone5_mercury_sa1_pe1_sdmmc.dtb \
> diff --git a/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_draeger_m48.dts b/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_draeger_m48.dts
> new file mode 100644
> index 000000000000..423c76cd1d4a
> --- /dev/null
> +++ b/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_draeger_m48.dts
> @@ -0,0 +1,130 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * (C) Copyright 2020 Draeger and Licensors, info@draeger.com
> + */
> +#include "socfpga_cyclone5.dtsi"
> +
> +/ {
> + model = "Draeger M48 Cyclone V SoC";
> + compatible = "draeger,M48", "altr,socfpga-cyclone5", "altr,socfpga";
> +
> + chosen {
> + bootargs = "earlyprintk";
That's not a mainline suitable argument, drop.
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH v2 1/1] ARM: dts: draeger: Add socfpga devicetree for Draeger's M48 board.
2026-09-09 6:36 ` Krzysztof Kozlowski
@ 2026-09-09 6:50 ` Petko Manolov
2026-09-09 6:52 ` Krzysztof Kozlowski
2026-09-09 10:07 ` Petko Manolov
1 sibling, 1 reply; 8+ messages in thread
From: Petko Manolov @ 2026-09-09 6:50 UTC (permalink / raw)
To: Krzysztof Kozlowski
Cc: linux-kernel, devicetree, robh, krzk+dt, conor+dt, dinguyen
On 26-09-09 08:36:23, Krzysztof Kozlowski wrote:
> On 08/09/2026 13:10, Petko Manolov wrote:
> > Signed-off-by: Petko Manolov <petko.manolov@konsulko.com>
>
> Please run scripts/checkpatch.pl on the patches and fix reported warnings.
> After that, run also 'scripts/checkpatch.pl --strict' on the patches and
> (probably) fix more warnings. Some warnings can be ignored, especially from
> --strict run, but the code here looks like it needs a fix. Feel free to get in
> touch if the warning is not clear.
>
>
> > ---
> > .../devicetree/bindings/arm/altera.yaml | 1 +
> > arch/arm/boot/dts/intel/socfpga/Makefile | 1 +
> > .../socfpga/socfpga_cyclone5_draeger_m48.dts | 130 ++++++++++++++++++
> > 3 files changed, 132 insertions(+)
> > create mode 100644 arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_draeger_m48.dts
> >
> > diff --git a/Documentation/devicetree/bindings/arm/altera.yaml b/Documentation/devicetree/bindings/arm/altera.yaml
> > index 3030cf46fe74..8ed1ba733510 100644
> > --- a/Documentation/devicetree/bindings/arm/altera.yaml
> > +++ b/Documentation/devicetree/bindings/arm/altera.yaml
>
> Same comments. Binding should not be part of other patches.
Does this mean i should submit the bindings related patches first?
> > @@ -47,6 +47,7 @@ properties:
> > - enum:
> > - altr,socfpga-cyclone5-socdk
> > - denx,mcvevk
> > + - draeger,M48
> > - ebv,socrates
> > - macnica,sodia
> > - novtech,chameleon96
> > diff --git a/arch/arm/boot/dts/intel/socfpga/Makefile b/arch/arm/boot/dts/intel/socfpga/Makefile
> > index 8df0976da01c..cdcea11abdfa 100644
> > --- a/arch/arm/boot/dts/intel/socfpga/Makefile
> > +++ b/arch/arm/boot/dts/intel/socfpga/Makefile
> > @@ -11,6 +11,7 @@ dtb-$(CONFIG_ARCH_INTEL_SOCFPGA) += \
> > socfpga_arria10_mercury_aa1_st1_emmc.dtb \
> > socfpga_arria10_mercury_aa1_st1_qspi.dtb \
> > socfpga_arria10_mercury_aa1_st1_sdmmc.dtb \
> > + socfpga_cyclone5_draeger_m48.dtb \
> > socfpga_cyclone5_mercury_sa1_pe1_emmc.dtb \
> > socfpga_cyclone5_mercury_sa1_pe1_qspi.dtb \
> > socfpga_cyclone5_mercury_sa1_pe1_sdmmc.dtb \
> > diff --git a/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_draeger_m48.dts b/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_draeger_m48.dts
> > new file mode 100644
> > index 000000000000..423c76cd1d4a
> > --- /dev/null
> > +++ b/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_draeger_m48.dts
> > @@ -0,0 +1,130 @@
> > +// SPDX-License-Identifier: GPL-2.0+
> > +/*
> > + * (C) Copyright 2020 Draeger and Licensors, info@draeger.com
> > + */
> > +#include "socfpga_cyclone5.dtsi"
> > +
> > +/ {
> > + model = "Draeger M48 Cyclone V SoC";
> > + compatible = "draeger,M48", "altr,socfpga-cyclone5", "altr,socfpga";
> > +
> > + chosen {
> > + bootargs = "earlyprintk";
>
> That's not a mainline suitable argument, drop.
These DTs are meant for u-boot only usage, but OK, will drop the bootargs.
Petko
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH v2 1/1] ARM: dts: draeger: Add socfpga devicetree for Draeger's M48 board.
2026-09-09 6:50 ` Petko Manolov
@ 2026-09-09 6:52 ` Krzysztof Kozlowski
0 siblings, 0 replies; 8+ messages in thread
From: Krzysztof Kozlowski @ 2026-09-09 6:52 UTC (permalink / raw)
To: Petko Manolov; +Cc: linux-kernel, devicetree, robh, krzk+dt, conor+dt, dinguyen
On 09/09/2026 08:50, Petko Manolov wrote:
> On 26-09-09 08:36:23, Krzysztof Kozlowski wrote:
>> On 08/09/2026 13:10, Petko Manolov wrote:
>>> Signed-off-by: Petko Manolov <petko.manolov@konsulko.com>
>>
>> Please run scripts/checkpatch.pl on the patches and fix reported warnings.
>> After that, run also 'scripts/checkpatch.pl --strict' on the patches and
>> (probably) fix more warnings. Some warnings can be ignored, especially from
>> --strict run, but the code here looks like it needs a fix. Feel free to get in
>> touch if the warning is not clear.
>>
>>
>>> ---
>>> .../devicetree/bindings/arm/altera.yaml | 1 +
>>> arch/arm/boot/dts/intel/socfpga/Makefile | 1 +
>>> .../socfpga/socfpga_cyclone5_draeger_m48.dts | 130 ++++++++++++++++++
>>> 3 files changed, 132 insertions(+)
>>> create mode 100644 arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_draeger_m48.dts
>>>
>>> diff --git a/Documentation/devicetree/bindings/arm/altera.yaml b/Documentation/devicetree/bindings/arm/altera.yaml
>>> index 3030cf46fe74..8ed1ba733510 100644
>>> --- a/Documentation/devicetree/bindings/arm/altera.yaml
>>> +++ b/Documentation/devicetree/bindings/arm/altera.yaml
>>
>> Same comments. Binding should not be part of other patches.
>
> Does this mean i should submit the bindings related patches first?
Please read both submitting patches documents.
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH v2 1/1] ARM: dts: draeger: Add socfpga devicetree for Draeger's M48 board.
2026-09-09 6:36 ` Krzysztof Kozlowski
2026-09-09 6:50 ` Petko Manolov
@ 2026-09-09 10:07 ` Petko Manolov
2026-09-09 10:14 ` Krzysztof Kozlowski
1 sibling, 1 reply; 8+ messages in thread
From: Petko Manolov @ 2026-09-09 10:07 UTC (permalink / raw)
To: Krzysztof Kozlowski
Cc: linux-kernel, devicetree, robh, krzk+dt, conor+dt, dinguyen
On 26-09-09 08:36:23, Krzysztof Kozlowski wrote:
> On 08/09/2026 13:10, Petko Manolov wrote:
> > +
> > + chosen {
> > + bootargs = "earlyprintk";
>
> That's not a mainline suitable argument, drop.
Well, i'm a bit confused. These files in arch/arm/boot/dts/intel/socfpga/
socfpga_arria5_socdk.dts
socfpga_cyclone5_de0_nano_soc.dts
socfpga_cyclone5_vining_fpga.dts
socfpga_arria10_socdk.dtsi
socfpga_cyclone5_socdk.dts
socfpga_cyclone5_chameleon96.dts
socfpga_cyclone5_socrates.dts
socfpga_cyclone5_sodia.dts
socfpga_cyclone5_sockit.dts
all have:
chosen {
bootargs = "earlyprintk";
stdout-path = "serial0:115200n8";
};
Is this some sort of legacy that isn't accepted in modern days or is it
something else?
Petko
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH v2 1/1] ARM: dts: draeger: Add socfpga devicetree for Draeger's M48 board.
2026-09-09 10:07 ` Petko Manolov
@ 2026-09-09 10:14 ` Krzysztof Kozlowski
2026-09-09 11:16 ` Petko Manolov
0 siblings, 1 reply; 8+ messages in thread
From: Krzysztof Kozlowski @ 2026-09-09 10:14 UTC (permalink / raw)
To: Petko Manolov; +Cc: linux-kernel, devicetree, robh, krzk+dt, conor+dt, dinguyen
On 09/09/2026 12:07, Petko Manolov wrote:
> On 26-09-09 08:36:23, Krzysztof Kozlowski wrote:
>> On 08/09/2026 13:10, Petko Manolov wrote:
>>> +
>>> + chosen {
>>> + bootargs = "earlyprintk";
>>
>> That's not a mainline suitable argument, drop.
>
> Well, i'm a bit confused. These files in arch/arm/boot/dts/intel/socfpga/
>
> socfpga_arria5_socdk.dts
> socfpga_cyclone5_de0_nano_soc.dts
> socfpga_cyclone5_vining_fpga.dts
> socfpga_arria10_socdk.dtsi
> socfpga_cyclone5_socdk.dts
> socfpga_cyclone5_chameleon96.dts
> socfpga_cyclone5_socrates.dts
> socfpga_cyclone5_sodia.dts
> socfpga_cyclone5_sockit.dts
>
> all have:
>
> chosen {
> bootargs = "earlyprintk";
> stdout-path = "serial0:115200n8";
> };
>
> Is this some sort of legacy that isn't accepted in modern days or is it
> something else?
And git log tells...? Anyway, pre-existing code is a poor argument why
code should be added.
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH v2 1/1] ARM: dts: draeger: Add socfpga devicetree for Draeger's M48 board.
2026-09-09 10:14 ` Krzysztof Kozlowski
@ 2026-09-09 11:16 ` Petko Manolov
0 siblings, 0 replies; 8+ messages in thread
From: Petko Manolov @ 2026-09-09 11:16 UTC (permalink / raw)
To: Krzysztof Kozlowski
Cc: linux-kernel, devicetree, robh, krzk+dt, conor+dt, dinguyen
On 26-09-09 12:14:34, Krzysztof Kozlowski wrote:
>
> And git log tells...? Anyway, pre-existing code is a poor argument why code
> should be added.
OK, dropping the earlyprintk argument...
Petko
^ permalink raw reply [flat|nested] 8+ messages in thread
end of thread, other threads:[~2026-09-09 11:16 UTC | newest]
Thread overview: 8+ messages (download: mbox.gz / follow: Atom feed)
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2026-09-08 11:09 [PATCH v2 0/1] ARM: dts: draeger: Add socfpga devicetree for Draeger's M48 board Petko Manolov
2026-09-08 11:10 ` [PATCH v2 1/1] " Petko Manolov
2026-09-09 6:36 ` Krzysztof Kozlowski
2026-09-09 6:50 ` Petko Manolov
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