RE: [PATCH 1/4] x86_64 io_apic: Implement remove_pin_to_irq

RE: [PATCH 1/4] x86_64 io_apic: Implement remove_pin_to_irq

[Lu, Yinghai]

-----Original Message-----
From: ebiederm@xmission.com [mailto:ebiederm@xmission.com] 
Sent: Monday, January 08, 2007 7:50 AM
To: Linus Torvalds
Cc: Tobias Diedrich; Lu, Yinghai; Andrew Morton; Adrian Bunk; Andi
Kleen; Linux Kernel Mailing List
Subject: [PATCH 1/4] x86_64 io_apic: Implement remove_pin_to_irq

+static void remove_pin_to_irq(unsigned int irq, int apic, int pin)
+{
+	struct irq_pin_list *entry = irq_2_pin + irq;

You may need to update add_pin_to_irq to avoid multi entries for irq 0.

YH

Re: [PATCH 1/4] x86_64 io_apic: Implement remove_pin_to_irq

[Eric W. Biederman]

"Lu, Yinghai" <yinghai.lu@amd.com> writes:

> -----Original Message-----
> From: ebiederm@xmission.com [mailto:ebiederm@xmission.com] 
> Sent: Monday, January 08, 2007 7:50 AM
> To: Linus Torvalds
> Cc: Tobias Diedrich; Lu, Yinghai; Andrew Morton; Adrian Bunk; Andi
> Kleen; Linux Kernel Mailing List
> Subject: [PATCH 1/4] x86_64 io_apic: Implement remove_pin_to_irq
>
> +static void remove_pin_to_irq(unsigned int irq, int apic, int pin)
> +{
> +	struct irq_pin_list *entry = irq_2_pin + irq;
>
> You may need to update add_pin_to_irq to avoid multi entries for irq 0.

Any updates to add_pin_to_irq are wrong.  It works fine.  If there
is something wrong we need to fix remove_pin_to_irq.

What is the problem you see?  Sorry I'm dense at the moment.

I preserve the invariant that irq_2_pin + irq is always the first
entry in the chain.  I do this when I delete a multi chain entry
by copying the next entry over the current entry, and then freeing
(and leaking) the second entry in the chain.

Is there something wrong with that?  I came within an inch of deleting
this multiple apic, pin to irq mapping code but the comments said it
is needed for some ioapic case.  So in resurrecting this variant I may
have goofed somewhere.

Eric

RE: [PATCH 1/4] x86_64 io_apic: Implement remove_pin_to_irq

[Lu, Yinghai]

-----Original Message-----
From: ebiederm@xmission.com [mailto:ebiederm@xmission.com] 
Sent: Monday, January 08, 2007 1:31 PM
To: Lu, Yinghai
Cc: Linus Torvalds; Tobias Diedrich; Andrew Morton; Adrian Bunk; Andi
Kleen; Linux Kernel Mailing List
Subject: Re: [PATCH 1/4] x86_64 io_apic: Implement remove_pin_to_irq

>Any updates to add_pin_to_irq are wrong.  It works fine.  If there
>is something wrong we need to fix remove_pin_to_irq.

>What is the problem you see?  Sorry I'm dense at the moment.

+static int check_timer_pin(int apic, int pin) {
+	int irq, idx;
+	/* 
+	 * Test the architecture default i8254 timer pin
+	 * of apic 0 pin 2.
+	 */
+
+
+	/* If the apic pin pair is in use by another irq fail */
+	irq = irq_from_pin(apic, pin);
+	if ((irq != -1) && (irq != 0)) {
+		apic_printk(APIC_VERBOSE,KERN_INFO "...apic %d pin % in
use by irq %d\n",
+			apic, pin, irq);
+		return 0; 
+	}
+
+	/* Add an entry in mp_irqs for irq 0 */
+	idx = update_irq0_entry(apic, pin);
+
+	/* Add an entry in irq_to_pin */
+	add_pin_to_irq(0, apic, pin);
+
+	/* Now setup the irq */
+	setup_IO_APIC_irq(apic, pin, idx, 0);
+
+	/* And finally check to see if the irq works */
+	return do_check_timer_pin(apic, pin);
+}
+

In the check_timer_pin, irq_from_pin could return 0, it mean some entry
is for IRQ0 already.
The add_pin_to_irq could add another same entry for it again.

YH

Re: 2.6.20-rc3: known unfixed regressions - x86_64 boot failure: "IO-APIC + timer doesn't work"

[Yinghai Lu]

[-- Attachment #1: Type: text/plain, Size: 51 bytes --]

Please check the latest version. ( 01/02/2007)

YH

[-- Warning: decoded text below may be mangled, UTF-8 assumed --]
[-- Attachment #2: timer_01022007.diff --]
[-- Type: text/x-patch; name="timer_01022007.diff", Size: 8611 bytes --]

[PATCH] x86_64: check_timer with io apic setup before try_apic_pin

In the check_timer, it forget to set up the io apic before try_apic_pin for
timer. So add set_try_apic_pin to set up the io apic pin. otherwise the 
try_apic_pin will not work.

also add remove_irq_to_pin to corresponging to add_pin_to_irq to make irq_2_pin
more complete and make the set io apic more convenient.

Also add add_irq_entry in mparese.c to add apic/pin pair to mp_irqs in case 
some nvidia based MB have wrong io apic pin entry for timer. Some ck804 based 
MB, MPTABLE or ACPI assume timer is on ioapic pin2. but HW is set to pin0. or 
reversing case.

the check_timer will try 
1. apic1, pin1 with 8259 IRQ0 disabled
2. apic=0, pin=0 with 8259 IRQ0 disabled
3. apic=0, pin=2 with 8259 IRQ0 disabled
4. apic1, pin1 with 8259 IRQ0 enabled
5. apic2, pin2, pure 8259A routing on the 8259 as reported by BIOS

without the patch:
..TIMER: trying IO-APIC=0 PIN=0 with 8259 IRQ0 disabled<3> .. failed
..TIMER: trying IO-APIC=0 PIN=0 with 8259 IRQ0 enabled<7>APIC error on CPU0: 00(40) .. failed
..TIMER: trying IO-APIC=0 PIN=2 fallback with 8259 IRQ0 disabled<3> .. failed
..TIMER: trying IO-APIC=0 PIN=0 8259A broadcast ExtINT from BIOS<7>number of MP IRQ sources: 84.
testing the IO APIC.......................


.................................... done.

with the patch:
..TIMER: trying IO-APIC=0 PIN=0 with 8259 IRQ0 disabled<3> .. failed
..TIMER: trying IO-APIC=0 PIN=2 fallback with 8259 IRQ0 disabled<7>number of MP IRQ sources: 85.
testing the IO APIC.......................


.................................... done.                                     
 
cc: Andi Kleen <ak@suse.de>
cc: Eric W. Biederman <ebiederm@xmission.com>
Signed-off-by: Yinghai Lu <yinghai.lu@amd.com>

diff --git a/arch/x86_64/kernel/io_apic.c b/arch/x86_64/kernel/io_apic.c
index 2a1dcd5..e200d0a 100644
--- a/arch/x86_64/kernel/io_apic.c
+++ b/arch/x86_64/kernel/io_apic.c
@@ -273,10 +273,17 @@ static void add_pin_to_irq(unsigned int irq, int apic, int pin)
 	struct irq_pin_list *entry = irq_2_pin + irq;
 
 	BUG_ON(irq >= NR_IRQS);
-	while (entry->next)
+	while (entry->next) {
+		if (entry->apic == apic && entry->pin == pin) 
+			return;
+		if (entry->pin == -1) 
+			break;
 		entry = irq_2_pin + entry->next;
+	}
 
 	if (entry->pin != -1) {
+		if (entry->apic == apic && entry->pin == pin) 
+			return;
 		entry->next = first_free_entry;
 		entry = irq_2_pin + entry->next;
 		if (++first_free_entry >= PIN_MAP_SIZE)
@@ -286,6 +293,39 @@ static void add_pin_to_irq(unsigned int irq, int apic, int pin)
 	entry->pin = pin;
 }
 
+static void remove_pin_to_irq(unsigned int irq, int apic, int pin)
+{
+	struct irq_pin_list *entry = irq_2_pin + irq;
+	struct irq_pin_list *pri;
+	struct irq_pin_list *next;
+
+	BUG_ON(irq >= NR_IRQS);
+
+	for (;;) {
+		if (entry->apic == apic && entry->pin == pin) {
+			if(entry->next) {
+				next = irq_2_pin + entry->next;
+				entry->apic = next->apic;
+				entry->pin = next->pin;
+				entry->next = next->next;
+				next->apic = -1;
+				next->pin = -1;
+				next->next = 0;
+			} else {
+				entry->apic = -1;
+				entry->pin = -1;
+			}
+			return;
+		}
+		pri = entry;
+		if (pri->next) 
+			entry = irq_2_pin + pri->next;
+		else
+			break;
+	} 
+
+}
+
 
 #define DO_ACTION(name,R,ACTION, FINAL)					\
 									\
@@ -1570,6 +1610,22 @@ static inline void unlock_ExtINT_logic(void)
  * fanatically on his truly buggy board.
  */
 
+static void set_try_apic_pin(int apic, int pin, int type)
+{
+	int idx;
+	int irq = 0;
+	int bus = 0; /* MP_ISA_BUS */
+	int irqflag = 5; /* MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH */
+
+	idx = find_irq_entry(apic,pin,type);
+
+	if (idx == -1) 
+		idx = add_irq_entry(type, irqflag, bus, irq, apic, pin);
+
+	add_pin_to_irq(irq, apic, pin);
+	setup_IO_APIC_irq(apic, pin, idx, irq);
+}
+
 static int try_apic_pin(int apic, int pin, char *msg)
 {
 	apic_printk(APIC_VERBOSE, KERN_INFO
@@ -1588,7 +1644,7 @@ static int try_apic_pin(int apic, int pin, char *msg)
 		}
 		return 1;
 	}
-	clear_IO_APIC_pin(apic, pin);
+
 	apic_printk(APIC_QUIET, KERN_ERR " .. failed\n");
 	return 0;
 }
@@ -1599,6 +1655,7 @@ static void check_timer(void)
 	int apic1, pin1, apic2, pin2;
 	int vector;
 	cpumask_t mask;
+	int i;
 
 	/*
 	 * get/set the timer IRQ vector:
@@ -1621,33 +1678,60 @@ static void check_timer(void)
 	pin2  = ioapic_i8259.pin;
 	apic2 = ioapic_i8259.apic;
 
-	/* Do this first, otherwise we get double interrupts on ATI boards */
-	if ((pin1 != -1) && try_apic_pin(apic1, pin1,"with 8259 IRQ0 disabled"))
-		return;
+	apic_printk(APIC_VERBOSE,KERN_INFO "..TIMER: vector=0x%02X apic1=%d pin1=%d apic2=%d pin2=%d\n",
+		vector, apic1, pin1, apic2, pin2);
 
-	/* Now try again with IRQ0 8259A enabled.
-	   Assumes timer is on IO-APIC 0 ?!? */
-	enable_8259A_irq(0);
-	unmask_IO_APIC_irq(0);
-	if (try_apic_pin(apic1, pin1, "with 8259 IRQ0 enabled"))
-		return;
-	disable_8259A_irq(0);
+	if (pin1 != -1) {
+		/* Do this first, otherwise we get double interrupts on ATI boards */
+		/* set_try_apic_pin will call disable_8259A_irq */
+		set_try_apic_pin(apic1, pin1, mp_INT);
+		unmask_IO_APIC_irq(0);
+		if (try_apic_pin(apic1, pin1,"with 8259 IRQ0 disabled"))
+			return;
+
+		clear_IO_APIC_pin(apic1, pin1);
+		remove_pin_to_irq(0, apic1, pin1);
+	}
 
 	/* Always try pin0 and pin2 on APIC 0 to handle buggy timer overrides
 	   on Nvidia boards */
-	if (!(apic1 == 0 && pin1 == 0) &&
-	    try_apic_pin(0, 0, "fallback with 8259 IRQ0 disabled"))
-		return;
-	if (!(apic1 == 0 && pin1 == 2) &&
-	    try_apic_pin(0, 2, "fallback with 8259 IRQ0 disabled"))
-		return;
+	for (i = 0; i <= 2; i += 2) 
+	if (!(apic1 == 0 && pin1 == i)) {
+		/* set_try_apic_pin will call disable_8259A_irq */
+		set_try_apic_pin(0, i, mp_INT); 
+		unmask_IO_APIC_irq(0);
+		if (try_apic_pin(0, i, "fallback with 8259 IRQ0 disabled"))
+			return;
+
+		clear_IO_APIC_pin(0, i);
+		remove_pin_to_irq(0, 0, i);
+	}
+
+	if (pin1 != -1) {
+		/* set_try_apic_pin will call disable_8259A_irq */
+		set_try_apic_pin(apic1, pin1, mp_INT);
+		unmask_IO_APIC_irq(0);
+
+		/* Now try again with IRQ0 8259A enabled.
+		   Assumes timer is on IO-APIC 0 ?!? */
+		enable_8259A_irq(0);
+		if (try_apic_pin(apic1, pin1, "with 8259 IRQ0 enabled"))
+			return;
+		disable_8259A_irq(0);
+
+		clear_IO_APIC_pin(apic1, pin1);
+		remove_pin_to_irq(0, apic1, pin1);
+	}
 
 	/* Then try pure 8259A routing on the 8259 as reported by BIOS*/
-	enable_8259A_irq(0);
 	if (pin2 != -1) {
 		setup_ExtINT_IRQ0_pin(apic2, pin2, vector);
+		add_pin_to_irq(0, apic2, pin2);
+		enable_8259A_irq(0);
 		if (try_apic_pin(apic2,pin2,"8259A broadcast ExtINT from BIOS"))
 			return;
+		clear_IO_APIC_pin(apic2, pin2);
+		remove_pin_to_irq(0, apic2, pin2);
 	}
 
 	/* Tried all possibilities to go through the IO-APIC. Now come the
diff --git a/arch/x86_64/kernel/mpparse.c b/arch/x86_64/kernel/mpparse.c
index 0807256..5f7a95a 100644
--- a/arch/x86_64/kernel/mpparse.c
+++ b/arch/x86_64/kernel/mpparse.c
@@ -314,6 +314,34 @@ static int __init ELCR_trigger(unsigned int irq)
 	return (inb(port) >> (irq & 7)) & 1;
 }
 
+int add_irq_entry(int type, int irqflag, int bus, int irq, int apic, int pin)
+{
+	struct mpc_config_intsrc intsrc;
+	int idx;
+
+	intsrc.mpc_type = MP_INTSRC;
+	intsrc.mpc_irqflag = irqflag; /* conforming */
+	intsrc.mpc_srcbus = bus;
+	intsrc.mpc_dstapic = (apic != -1) ? mp_ioapics[apic].mpc_apicid: MP_APIC_ALL;
+
+	intsrc.mpc_irqtype = type;
+
+	intsrc.mpc_srcbusirq = irq;
+	intsrc.mpc_dstirq = pin;
+
+	mp_irqs [mp_irq_entries] = intsrc;
+	Dprintk("Int: type %d, pol %d, trig %d, bus %d,"
+		" IRQ %02x, APIC ID %x, APIC INT %02x\n",
+			intsrc.mpc_irqtype, intsrc.mpc_irqflag & 3,
+			(intsrc.mpc_irqflag >> 2) & 3, intsrc.mpc_srcbus,
+			intsrc.mpc_srcbusirq, intsrc.mpc_dstapic, intsrc.mpc_dstirq);
+	idx = mp_irq_entries;
+	if (++mp_irq_entries >= MAX_IRQ_SOURCES)
+		panic("Max # of irq sources exceeded!!\n");
+	return idx;
+
+}
+
 static void __init construct_default_ioirq_mptable(int mpc_default_type)
 {
 	struct mpc_config_intsrc intsrc;
diff --git a/include/asm-x86_64/mpspec.h b/include/asm-x86_64/mpspec.h
index 017fddb..1ddfd4d 100644
--- a/include/asm-x86_64/mpspec.h
+++ b/include/asm-x86_64/mpspec.h
@@ -165,6 +165,7 @@ extern int mp_bus_id_to_pci_bus [MAX_MP_BUSSES];
 extern unsigned int boot_cpu_physical_apicid;
 extern int smp_found_config;
 extern void find_smp_config (void);
+extern int add_irq_entry (int type, int irqflag, int bus, int irq, int apic, int pin);
 extern void get_smp_config (void);
 extern int nr_ioapics;
 extern unsigned char apic_version [MAX_APICS];

Re: 2.6.20-rc3: known unfixed regressions - x86_64 boot failure: "IO-APIC + timer doesn't work"

[Tobias Diedrich]

Yinghai Lu wrote:
> Please check the latest version. ( 01/02/2007)

Works for me, with both BIOS versions / routing variants.

patches/series:
patch-2.6.20-rc4
patch-2.6.19-rc3-nokmem
myconfig
ccache
timer_01022007.diff
hpet-quirk

dmesg diff:
--- dmesg-20070108-2.6.20-rc4-bios-0402	2007-01-08 01:51:57.000000000 +0100
+++ dmesg-20070108-2.6.20-rc4-bios-0609	2007-01-08 01:52:05.000000000 +0100
@@ -13,14 +13,15 @@
 Entering add_active_range(0, 0, 159) 0 entries of 256 used
 Entering add_active_range(0, 256, 261856) 1 entries of 256 used
 end_pfn_map = 1048576
-DMI 2.3 present.
-ACPI: RSDP (v000 Nvidia                                ) @ 0x00000000000f7ce0
-ACPI: RSDT (v001 Nvidia AWRDACPI 0x42302e31 AWRD 0x00000000) @ 0x000000003fee3040
-ACPI: FADT (v001 Nvidia AWRDACPI 0x42302e31 AWRD 0x00000000) @ 0x000000003fee30c0
-ACPI: SSDT (v001 PTLTD  POWERNOW 0x00000001  LTP 0x00000001) @ 0x000000003feec2c0
-ACPI: MCFG (v001 Nvidia AWRDACPI 0x42302e31 AWRD 0x00000000) @ 0x000000003feec400
-ACPI: MADT (v001 Nvidia AWRDACPI 0x42302e31 AWRD 0x00000000) @ 0x000000003feec200
-ACPI: DSDT (v001 NVIDIA AWRDACPI 0x00001000 MSFT 0x0100000e) @ 0x0000000000000000
+DMI 2.4 present.
+ACPI: RSDP (v002 Nvidia                                ) @ 0x00000000000f7b70
+ACPI: XSDT (v001 Nvidia ASUSACPI 0x42302e31 AWRD 0x00000000) @ 0x000000003fee30c0
+ACPI: FADT (v003 Nvidia ASUSACPI 0x42302e31 AWRD 0x00000000) @ 0x000000003feec5c0
+ACPI: SSDT (v001 PTLTD  POWERNOW 0x00000001  LTP 0x00000001) @ 0x000000003feec7c0
+ACPI: HPET (v001 Nvidia ASUSACPI 0x42302e31 AWRD 0x00000098) @ 0x000000003feec900
+ACPI: MCFG (v001 Nvidia ASUSACPI 0x42302e31 AWRD 0x00000000) @ 0x000000003feec980
+ACPI: MADT (v001 Nvidia ASUSACPI 0x42302e31 AWRD 0x00000000) @ 0x000000003feec700
+ACPI: DSDT (v001 NVIDIA AWRDACPI 0x00001000 MSFT 0x03000000) @ 0x0000000000000000
 Entering add_active_range(0, 0, 159) 0 entries of 256 used
 Entering add_active_range(0, 256, 261856) 1 entries of 256 used
 Zone PFN ranges:
@@ -37,8 +38,6 @@
   DMA32 zone: 3524 pages used for memmap
   DMA32 zone: 254236 pages, LIFO batch:31
   Normal zone: 0 pages used for memmap
-Nvidia board detected. Ignoring ACPI timer override.
-If you got timer trouble try acpi_use_timer_override
 ACPI: PM-Timer IO Port: 0x1008
 ACPI: Local APIC address 0xfee00000
 ACPI: LAPIC (acpi_id[0x00] lapic_id[0x00] enabled)
@@ -48,13 +47,17 @@
 ACPI: LAPIC_NMI (acpi_id[0x01] high edge lint[0x1])
 ACPI: IOAPIC (id[0x02] address[0xfec00000] gsi_base[0])
 IOAPIC[0]: apic_id 2, address 0xfec00000, GSI 0-23
+ACPI: INT_SRC_OVR (bus 0 bus_irq 0 global_irq 2 dfl dfl)
 ACPI: INT_SRC_OVR (bus 0 bus_irq 9 global_irq 9 high level)
 ACPI: INT_SRC_OVR (bus 0 bus_irq 14 global_irq 14 high edge)
 ACPI: INT_SRC_OVR (bus 0 bus_irq 15 global_irq 15 high edge)
+ACPI: IRQ0 used by override.
+ACPI: IRQ2 used by override.
 ACPI: IRQ9 used by override.
 ACPI: IRQ14 used by override.
 ACPI: IRQ15 used by override.
 Setting APIC routing to flat
+ACPI: HPET id: 0x10de8201 base: 0xfefff000
 Using ACPI (MADT) for SMP configuration information
 mapped APIC to ffffffffff5fd000 (        fee00000)
 mapped IOAPIC to ffffffffff5fc000 (00000000fec00000)
@@ -72,10 +75,8 @@
 netconsole: remote ethernet address ff:ff:ff:ff:ff:ff
 Initializing CPU#0
 PID hash table entries: 4096 (order: 12, 32768 bytes)
-trying to force-enable HPET
-HPET force-enabled at 0xfef00000
 time.c: Using 25.000000 MHz WALL HPET GTOD HPET/TSC timer.
-time.c: Detected 2009.512 MHz processor.
+time.c: Detected 2009.511 MHz processor.
 Console: colour VGA+ 80x60
 Dentry cache hash table entries: 131072 (order: 8, 1048576 bytes)
 Inode-cache hash table entries: 65536 (order: 7, 524288 bytes)
@@ -84,7 +85,7 @@
 Aperture too small (32 MB)
 No AGP bridge found
 Memory: 1025348k/1047424k available (3242k kernel code, 21444k reserved, 1470k data, 200k init)
-Calibrating delay using timer specific routine.. 4023.44 BogoMIPS (lpj=6703119)
+Calibrating delay using timer specific routine.. 4023.45 BogoMIPS (lpj=6703124)
 Mount-cache hash table entries: 256
 CPU: L1 I Cache: 64K (64 bytes/line), D cache 64K (64 bytes/line)
 CPU: L2 Cache: 512K (64 bytes/line)
@@ -95,11 +96,10 @@
 ESR value after enabling vector: 00000000, after 00000004
 ENABLING IO-APIC IRQs
 init IO_APIC IRQs
- IO-APIC (apicid-pin) 2-16, 2-17, 2-18, 2-19, 2-20, 2-21, 2-22, 2-23 not connected.
-..TIMER: vector=0x20 apic1=0 pin1=0 apic2=-1 pin2=-1
-..TIMER: trying IO-APIC=0 PIN=0 with 8259 IRQ0 disabled<3> .. failed
-..TIMER: trying IO-APIC=0 PIN=2 fallback with 8259 IRQ0 disabled<6>Using local APIC timer interrupts.
-result 12559465
+ IO-APIC (apicid-pin) 2-0, 2-16, 2-17, 2-18, 2-19, 2-20, 2-21, 2-22, 2-23 not connected.
+..TIMER: vector=0x20 apic1=0 pin1=2 apic2=-1 pin2=-1
+..TIMER: trying IO-APIC=0 PIN=2 with 8259 IRQ0 disabled<6>Using local APIC timer interrupts.
+result 12559463
 Detected 12.559 MHz APIC timer.
 testing NMI watchdog ... OK.
 NET: Registered protocol family 16
@@ -168,7 +168,7 @@
 usbcore: registered new device driver usb
 PCI: Using ACPI for IRQ routing
 PCI: If a device doesn't work, try "pci=routeirq".  If it helps, post a report
-number of MP IRQ sources: 16.
+number of MP IRQ sources: 15.
 number of IO-APIC #2 registers: 24.
 testing the IO APIC.......................
 
@@ -210,7 +210,6 @@
 IRQ to pin mappings:
 IRQ0 -> 0:2
 IRQ1 -> 0:1
-IRQ2 -> 0:2
 IRQ3 -> 0:3
 IRQ4 -> 0:4
 IRQ5 -> 0:5
@@ -225,7 +224,7 @@
 IRQ14 -> 0:14
 IRQ15 -> 0:15
 .................................... done.
-hpet0: at MMIO 0xfef00000, IRQs 2, 8, 31
+hpet0: at MMIO 0xfefff000, IRQs 2, 8, 31
 hpet0: 3 32-bit timers, 25000000 Hz
 pnp: 00:01: ioport range 0x1000-0x107f could not be reserved
 pnp: 00:01: ioport range 0x1080-0x10ff has been reserved
@@ -312,9 +311,9 @@
 ACPI: Fan [FAN] (on)
 ACPI: Processor [CPU0] (supports 8 throttling states)
 ACPI: Getting cpuindex for acpiid 0x1
-ACPI: Thermal Zone [THRM] (28 C)
+ACPI: Thermal Zone [THRM] (24 C)
 Real Time Clock Driver v1.12ac
-hpet_acpi_add: no address or irqs in _CRS
+hpet_resources: 0xfefff000 is busy
 Linux agpgart interface v0.101 (c) Dave Jones
 loop: loaded (max 8 devices)
 tun: Universal TUN/TAP device driver, 1.6

-- 
Tobias						PGP: http://9ac7e0bc.uguu.de
このメールは十割再利用されたビットで作られています。

Re: 2.6.20-rc3: known unfixed regressions - x86_64 boot failure: "IO-APIC + timer doesn't work"

[Linus Torvalds]

On Mon, 8 Jan 2007, Tobias Diedrich wrote:
>
> Yinghai Lu wrote:
> > Please check the latest version. ( 01/02/2007)
> 
> Works for me, with both BIOS versions / routing variants.

Yinghai, Eric, can you please send me the latest version with 
 (a) explanations for the changelogs
 (b) sign-off's (and acks for Eric, please) on it..

Let's get this one off the table.

		Linus

[PATCH 1/4] x86_64 io_apic: Implement remove_pin_to_irq

[Eric W. Biederman]

To try different irq routing combinations so we can make an informed
guess as to how to route irqs when the BIOS gets it wrong we need
the ability to modify our irq routing data structures.

This adds remove_pin_to_irq which removes the mapping from and apic pin
to an irq.

Signed-off-by: Eric W. Biederman <ebiederm@xmission.com>
---
 arch/x86_64/kernel/io_apic.c |   23 +++++++++++++++++++++++
 1 files changed, 23 insertions(+), 0 deletions(-)

diff --git a/arch/x86_64/kernel/io_apic.c b/arch/x86_64/kernel/io_apic.c
index 2a1dcd5..7365f5f 100644
--- a/arch/x86_64/kernel/io_apic.c
+++ b/arch/x86_64/kernel/io_apic.c
@@ -286,6 +286,29 @@ static void add_pin_to_irq(unsigned int irq, int apic, int pin)
 	entry->pin = pin;
 }
 
+static void remove_pin_to_irq(unsigned int irq, int apic, int pin)
+{
+	struct irq_pin_list *entry = irq_2_pin + irq;
+
+	BUG_ON(irq >= NR_IRQS);
+
+	while (entry->next && ((entry->apic != apic) || (entry->pin != pin)))
+		entry = irq_2_pin + entry->next;
+
+	if (entry->pin == apic && entry->pin == pin) {
+		if (entry->next) {
+			struct irq_pin_list *next = irq_2_pin + entry->next;
+			*entry = *next;
+			next->pin = -1;
+			next->apic = -1;
+			next->next = 0;
+		} else {
+			entry->pin = -1;
+			entry->apic = -1;
+		}
+	}
+}
+
 
 #define DO_ACTION(name,R,ACTION, FINAL)					\
 									\
-- 
1.4.4.1.g278f