From: Andreas Schwab <schwab@suse.de>
To: "Clément Léger" <cleger@rivosinc.com>
Cc: linux-kernel@vger.kernel.org, linux-kselftest@vger.kernel.org,
linux-riscv@lists.infradead.org,
Palmer Dabbelt <palmer@dabbelt.com>,
Paul Walmsley <paul.walmsley@sifive.com>,
Shuah Khan <shuah@kernel.org>, Alexandre Ghiti <alex@ghiti.fr>
Subject: Re: [PATCH v4] selftests: riscv: add misaligned access testing
Date: Thu, 10 Jul 2025 15:53:32 +0200 [thread overview]
Message-ID: <mvmecuognj7.fsf@suse.de> (raw)
In-Reply-To: <20250710133506.994476-1-cleger@rivosinc.com> (=?utf-8?Q?=22C?= =?utf-8?Q?l=C3=A9ment_L=C3=A9ger=22's?= message of "Thu, 10 Jul 2025 15:35:05 +0200")
On Jul 10 2025, Clément Léger wrote:
> This selftest tests all the currently emulated instructions (except for
> the RV32 compressed ones which are left as a future exercise for a RV32
> user). For the FPU instructions, all the FPU registers are tested.
If that didn't catch the missing sign extension that I just fixed in
<https://lore.kernel.org/linux-riscv/mvmikk0goil.fsf@suse.de>, you
should consider extending the tests.
--
Andreas Schwab, SUSE Labs, schwab@suse.de
GPG Key fingerprint = 0196 BAD8 1CE9 1970 F4BE 1748 E4D4 88E3 0EEA B9D7
"And now for something completely different."
next prev parent reply other threads:[~2025-07-10 13:53 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-07-10 13:35 Clément Léger
2025-07-10 13:53 ` Andreas Schwab [this message]
2025-07-10 14:10 ` Clément Léger
2025-07-10 14:23 ` Andreas Schwab
2025-07-10 14:29 ` Clément Léger
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