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From: "Clément Léger" <cleger@rivosinc.com>
To: Andreas Schwab <schwab@suse.de>
Cc: linux-kernel@vger.kernel.org, linux-kselftest@vger.kernel.org,
	linux-riscv@lists.infradead.org,
	Palmer Dabbelt <palmer@dabbelt.com>,
	Paul Walmsley <paul.walmsley@sifive.com>,
	Shuah Khan <shuah@kernel.org>, Alexandre Ghiti <alex@ghiti.fr>
Subject: Re: [PATCH v4] selftests: riscv: add misaligned access testing
Date: Thu, 10 Jul 2025 16:10:03 +0200	[thread overview]
Message-ID: <5db9ec69-d0e4-4113-a989-ac75d0f1e5dd@rivosinc.com> (raw)
In-Reply-To: <mvmecuognj7.fsf@suse.de>



On 10/07/2025 15:53, Andreas Schwab wrote:
> On Jul 10 2025, Clément Léger wrote:
> 
>> This selftest tests all the currently emulated instructions (except for
>> the RV32 compressed ones which are left as a future exercise for a RV32
>> user). For the FPU instructions, all the FPU registers are tested.
> 
> If that didn't catch the missing sign extension that I just fixed in
> <https://lore.kernel.org/linux-riscv/mvmikk0goil.fsf@suse.de>, you
> should consider extending the tests.
> 

Hi Andreas, you link doesn't work and I didn't find anything about sign
extension except a patch you wrote for arch_cmpxg().

Thanks,

Clément


  reply	other threads:[~2025-07-10 14:10 UTC|newest]

Thread overview: 5+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-07-10 13:35 Clément Léger
2025-07-10 13:53 ` Andreas Schwab
2025-07-10 14:10   ` Clément Léger [this message]
2025-07-10 14:23     ` Andreas Schwab
2025-07-10 14:29       ` Clément Léger

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